1/*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This file is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/clock/sun50i-a64-ccu.h>
46#include <dt-bindings/clock/sun8i-r-ccu.h>
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/reset/sun50i-a64-ccu.h>
49
50/ {
51	interrupt-parent = <&gic>;
52	#address-cells = <1>;
53	#size-cells = <1>;
54
55	cpus {
56		#address-cells = <1>;
57		#size-cells = <0>;
58
59		cpu0: cpu@0 {
60			compatible = "arm,cortex-a53", "arm,armv8";
61			device_type = "cpu";
62			reg = <0>;
63			enable-method = "psci";
64		};
65
66		cpu1: cpu@1 {
67			compatible = "arm,cortex-a53", "arm,armv8";
68			device_type = "cpu";
69			reg = <1>;
70			enable-method = "psci";
71		};
72
73		cpu2: cpu@2 {
74			compatible = "arm,cortex-a53", "arm,armv8";
75			device_type = "cpu";
76			reg = <2>;
77			enable-method = "psci";
78		};
79
80		cpu3: cpu@3 {
81			compatible = "arm,cortex-a53", "arm,armv8";
82			device_type = "cpu";
83			reg = <3>;
84			enable-method = "psci";
85		};
86	};
87
88	osc24M: osc24M_clk {
89		#clock-cells = <0>;
90		compatible = "fixed-clock";
91		clock-frequency = <24000000>;
92		clock-output-names = "osc24M";
93	};
94
95	osc32k: osc32k_clk {
96		#clock-cells = <0>;
97		compatible = "fixed-clock";
98		clock-frequency = <32768>;
99		clock-output-names = "osc32k";
100	};
101
102	iosc: internal-osc-clk {
103		#clock-cells = <0>;
104		compatible = "fixed-clock";
105		clock-frequency = <16000000>;
106		clock-accuracy = <300000000>;
107		clock-output-names = "iosc";
108	};
109
110	psci {
111		compatible = "arm,psci-0.2";
112		method = "smc";
113	};
114
115	timer {
116		compatible = "arm,armv8-timer";
117		interrupts = <GIC_PPI 13
118			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
119			     <GIC_PPI 14
120			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121			     <GIC_PPI 11
122			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
123			     <GIC_PPI 10
124			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
125	};
126
127	soc {
128		compatible = "simple-bus";
129		#address-cells = <1>;
130		#size-cells = <1>;
131		ranges;
132
133		syscon: syscon@1c00000 {
134			compatible = "allwinner,sun50i-a64-system-controller",
135				"syscon";
136			reg = <0x01c00000 0x1000>;
137		};
138
139		dma: dma-controller@1c02000 {
140			compatible = "allwinner,sun50i-a64-dma";
141			reg = <0x01c02000 0x1000>;
142			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
143			clocks = <&ccu CLK_BUS_DMA>;
144			dma-channels = <8>;
145			dma-requests = <27>;
146			resets = <&ccu RST_BUS_DMA>;
147			#dma-cells = <1>;
148		};
149
150		mmc0: mmc@1c0f000 {
151			compatible = "allwinner,sun50i-a64-mmc";
152			reg = <0x01c0f000 0x1000>;
153			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
154			clock-names = "ahb", "mmc";
155			resets = <&ccu RST_BUS_MMC0>;
156			reset-names = "ahb";
157			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
158			max-frequency = <150000000>;
159			status = "disabled";
160			#address-cells = <1>;
161			#size-cells = <0>;
162		};
163
164		mmc1: mmc@1c10000 {
165			compatible = "allwinner,sun50i-a64-mmc";
166			reg = <0x01c10000 0x1000>;
167			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
168			clock-names = "ahb", "mmc";
169			resets = <&ccu RST_BUS_MMC1>;
170			reset-names = "ahb";
171			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
172			max-frequency = <150000000>;
173			status = "disabled";
174			#address-cells = <1>;
175			#size-cells = <0>;
176		};
177
178		mmc2: mmc@1c11000 {
179			compatible = "allwinner,sun50i-a64-emmc";
180			reg = <0x01c11000 0x1000>;
181			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
182			clock-names = "ahb", "mmc";
183			resets = <&ccu RST_BUS_MMC2>;
184			reset-names = "ahb";
185			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
186			max-frequency = <200000000>;
187			status = "disabled";
188			#address-cells = <1>;
189			#size-cells = <0>;
190		};
191
192		usb_otg: usb@1c19000 {
193			compatible = "allwinner,sun8i-a33-musb";
194			reg = <0x01c19000 0x0400>;
195			clocks = <&ccu CLK_BUS_OTG>;
196			resets = <&ccu RST_BUS_OTG>;
197			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
198			interrupt-names = "mc";
199			phys = <&usbphy 0>;
200			phy-names = "usb";
201			extcon = <&usbphy 0>;
202			status = "disabled";
203		};
204
205		usbphy: phy@1c19400 {
206			compatible = "allwinner,sun50i-a64-usb-phy";
207			reg = <0x01c19400 0x14>,
208			      <0x01c1a800 0x4>,
209			      <0x01c1b800 0x4>;
210			reg-names = "phy_ctrl",
211				    "pmu0",
212				    "pmu1";
213			clocks = <&ccu CLK_USB_PHY0>,
214				 <&ccu CLK_USB_PHY1>;
215			clock-names = "usb0_phy",
216				      "usb1_phy";
217			resets = <&ccu RST_USB_PHY0>,
218				 <&ccu RST_USB_PHY1>;
219			reset-names = "usb0_reset",
220				      "usb1_reset";
221			status = "disabled";
222			#phy-cells = <1>;
223		};
224
225		ehci0: usb@1c1a000 {
226			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
227			reg = <0x01c1a000 0x100>;
228			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
229			clocks = <&ccu CLK_BUS_OHCI0>,
230				 <&ccu CLK_BUS_EHCI0>,
231				 <&ccu CLK_USB_OHCI0>;
232			resets = <&ccu RST_BUS_OHCI0>,
233				 <&ccu RST_BUS_EHCI0>;
234			status = "disabled";
235		};
236
237		ohci0: usb@1c1a400 {
238			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
239			reg = <0x01c1a400 0x100>;
240			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
241			clocks = <&ccu CLK_BUS_OHCI0>,
242				 <&ccu CLK_USB_OHCI0>;
243			resets = <&ccu RST_BUS_OHCI0>;
244			status = "disabled";
245		};
246
247		ehci1: usb@1c1b000 {
248			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
249			reg = <0x01c1b000 0x100>;
250			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
251			clocks = <&ccu CLK_BUS_OHCI1>,
252				 <&ccu CLK_BUS_EHCI1>,
253				 <&ccu CLK_USB_OHCI1>;
254			resets = <&ccu RST_BUS_OHCI1>,
255				 <&ccu RST_BUS_EHCI1>;
256			phys = <&usbphy 1>;
257			phy-names = "usb";
258			status = "disabled";
259		};
260
261		ohci1: usb@1c1b400 {
262			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
263			reg = <0x01c1b400 0x100>;
264			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
265			clocks = <&ccu CLK_BUS_OHCI1>,
266				 <&ccu CLK_USB_OHCI1>;
267			resets = <&ccu RST_BUS_OHCI1>;
268			phys = <&usbphy 1>;
269			phy-names = "usb";
270			status = "disabled";
271		};
272
273		ccu: clock@1c20000 {
274			compatible = "allwinner,sun50i-a64-ccu";
275			reg = <0x01c20000 0x400>;
276			clocks = <&osc24M>, <&osc32k>;
277			clock-names = "hosc", "losc";
278			#clock-cells = <1>;
279			#reset-cells = <1>;
280		};
281
282		pio: pinctrl@1c20800 {
283			compatible = "allwinner,sun50i-a64-pinctrl";
284			reg = <0x01c20800 0x400>;
285			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
286				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
287				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
288			clocks = <&ccu 58>;
289			gpio-controller;
290			#gpio-cells = <3>;
291			interrupt-controller;
292			#interrupt-cells = <3>;
293
294			i2c1_pins: i2c1_pins {
295				pins = "PH2", "PH3";
296				function = "i2c1";
297			};
298
299			mmc0_pins: mmc0-pins {
300				pins = "PF0", "PF1", "PF2", "PF3",
301				       "PF4", "PF5";
302				function = "mmc0";
303				drive-strength = <30>;
304				bias-pull-up;
305			};
306
307			mmc1_pins: mmc1-pins {
308				pins = "PG0", "PG1", "PG2", "PG3",
309				       "PG4", "PG5";
310				function = "mmc1";
311				drive-strength = <30>;
312				bias-pull-up;
313			};
314
315			mmc2_pins: mmc2-pins {
316				pins = "PC1", "PC5", "PC6", "PC8", "PC9",
317				       "PC10","PC11", "PC12", "PC13",
318				       "PC14", "PC15", "PC16";
319				function = "mmc2";
320				drive-strength = <30>;
321				bias-pull-up;
322			};
323
324			rmii_pins: rmii_pins {
325				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
326				       "PD18", "PD19", "PD20", "PD22", "PD23";
327				function = "emac";
328				drive-strength = <40>;
329			};
330
331			rgmii_pins: rgmii_pins {
332				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
333				       "PD13", "PD15", "PD16", "PD17", "PD18",
334				       "PD19", "PD20", "PD21", "PD22", "PD23";
335				function = "emac";
336				drive-strength = <40>;
337			};
338
339			spi0_pins: spi0 {
340				pins = "PC0", "PC1", "PC2", "PC3";
341				function = "spi0";
342			};
343
344			spi1_pins: spi1 {
345				pins = "PD0", "PD1", "PD2", "PD3";
346				function = "spi1";
347			};
348
349			uart0_pins_a: uart0 {
350				pins = "PB8", "PB9";
351				function = "uart0";
352			};
353
354			uart1_pins: uart1_pins {
355				pins = "PG6", "PG7";
356				function = "uart1";
357			};
358
359			uart1_rts_cts_pins: uart1_rts_cts_pins {
360				pins = "PG8", "PG9";
361				function = "uart1";
362			};
363
364			uart2_pins: uart2-pins {
365				pins = "PB0", "PB1";
366				function = "uart2";
367			};
368
369			uart3_pins: uart3-pins {
370				pins = "PD0", "PD1";
371				function = "uart3";
372			};
373
374			uart4_pins: uart4-pins {
375				pins = "PD2", "PD3";
376				function = "uart4";
377			};
378
379			uart4_rts_cts_pins: uart4-rts-cts-pins {
380				pins = "PD4", "PD5";
381				function = "uart4";
382			};
383		};
384
385		uart0: serial@1c28000 {
386			compatible = "snps,dw-apb-uart";
387			reg = <0x01c28000 0x400>;
388			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
389			reg-shift = <2>;
390			reg-io-width = <4>;
391			clocks = <&ccu CLK_BUS_UART0>;
392			resets = <&ccu RST_BUS_UART0>;
393			status = "disabled";
394		};
395
396		uart1: serial@1c28400 {
397			compatible = "snps,dw-apb-uart";
398			reg = <0x01c28400 0x400>;
399			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
400			reg-shift = <2>;
401			reg-io-width = <4>;
402			clocks = <&ccu CLK_BUS_UART1>;
403			resets = <&ccu RST_BUS_UART1>;
404			status = "disabled";
405		};
406
407		uart2: serial@1c28800 {
408			compatible = "snps,dw-apb-uart";
409			reg = <0x01c28800 0x400>;
410			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
411			reg-shift = <2>;
412			reg-io-width = <4>;
413			clocks = <&ccu CLK_BUS_UART2>;
414			resets = <&ccu RST_BUS_UART2>;
415			status = "disabled";
416		};
417
418		uart3: serial@1c28c00 {
419			compatible = "snps,dw-apb-uart";
420			reg = <0x01c28c00 0x400>;
421			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
422			reg-shift = <2>;
423			reg-io-width = <4>;
424			clocks = <&ccu CLK_BUS_UART3>;
425			resets = <&ccu RST_BUS_UART3>;
426			status = "disabled";
427		};
428
429		uart4: serial@1c29000 {
430			compatible = "snps,dw-apb-uart";
431			reg = <0x01c29000 0x400>;
432			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
433			reg-shift = <2>;
434			reg-io-width = <4>;
435			clocks = <&ccu CLK_BUS_UART4>;
436			resets = <&ccu RST_BUS_UART4>;
437			status = "disabled";
438		};
439
440		i2c0: i2c@1c2ac00 {
441			compatible = "allwinner,sun6i-a31-i2c";
442			reg = <0x01c2ac00 0x400>;
443			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
444			clocks = <&ccu CLK_BUS_I2C0>;
445			resets = <&ccu RST_BUS_I2C0>;
446			status = "disabled";
447			#address-cells = <1>;
448			#size-cells = <0>;
449		};
450
451		i2c1: i2c@1c2b000 {
452			compatible = "allwinner,sun6i-a31-i2c";
453			reg = <0x01c2b000 0x400>;
454			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
455			clocks = <&ccu CLK_BUS_I2C1>;
456			resets = <&ccu RST_BUS_I2C1>;
457			status = "disabled";
458			#address-cells = <1>;
459			#size-cells = <0>;
460		};
461
462		i2c2: i2c@1c2b400 {
463			compatible = "allwinner,sun6i-a31-i2c";
464			reg = <0x01c2b400 0x400>;
465			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
466			clocks = <&ccu CLK_BUS_I2C2>;
467			resets = <&ccu RST_BUS_I2C2>;
468			status = "disabled";
469			#address-cells = <1>;
470			#size-cells = <0>;
471		};
472
473
474		spi0: spi@1c68000 {
475			compatible = "allwinner,sun8i-h3-spi";
476			reg = <0x01c68000 0x1000>;
477			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
478			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
479			clock-names = "ahb", "mod";
480			dmas = <&dma 23>, <&dma 23>;
481			dma-names = "rx", "tx";
482			pinctrl-names = "default";
483			pinctrl-0 = <&spi0_pins>;
484			resets = <&ccu RST_BUS_SPI0>;
485			status = "disabled";
486			num-cs = <1>;
487			#address-cells = <1>;
488			#size-cells = <0>;
489		};
490
491		spi1: spi@1c69000 {
492			compatible = "allwinner,sun8i-h3-spi";
493			reg = <0x01c69000 0x1000>;
494			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
495			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
496			clock-names = "ahb", "mod";
497			dmas = <&dma 24>, <&dma 24>;
498			dma-names = "rx", "tx";
499			pinctrl-names = "default";
500			pinctrl-0 = <&spi1_pins>;
501			resets = <&ccu RST_BUS_SPI1>;
502			status = "disabled";
503			num-cs = <1>;
504			#address-cells = <1>;
505			#size-cells = <0>;
506		};
507
508		emac: ethernet@1c30000 {
509			compatible = "allwinner,sun50i-a64-emac";
510			syscon = <&syscon>;
511			reg = <0x01c30000 0x10000>;
512			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
513			interrupt-names = "macirq";
514			resets = <&ccu RST_BUS_EMAC>;
515			reset-names = "stmmaceth";
516			clocks = <&ccu CLK_BUS_EMAC>;
517			clock-names = "stmmaceth";
518			status = "disabled";
519			#address-cells = <1>;
520			#size-cells = <0>;
521
522			mdio: mdio {
523				compatible = "snps,dwmac-mdio";
524				#address-cells = <1>;
525				#size-cells = <0>;
526			};
527		};
528
529		gic: interrupt-controller@1c81000 {
530			compatible = "arm,gic-400";
531			reg = <0x01c81000 0x1000>,
532			      <0x01c82000 0x2000>,
533			      <0x01c84000 0x2000>,
534			      <0x01c86000 0x2000>;
535			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
536			interrupt-controller;
537			#interrupt-cells = <3>;
538		};
539
540		rtc: rtc@1f00000 {
541			compatible = "allwinner,sun6i-a31-rtc";
542			reg = <0x01f00000 0x54>;
543			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
544				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
545		};
546
547		r_intc: interrupt-controller@1f00c00 {
548			compatible = "allwinner,sun50i-a64-r-intc",
549				     "allwinner,sun6i-a31-r-intc";
550			interrupt-controller;
551			#interrupt-cells = <2>;
552			reg = <0x01f00c00 0x400>;
553			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
554		};
555
556		r_ccu: clock@1f01400 {
557			compatible = "allwinner,sun50i-a64-r-ccu";
558			reg = <0x01f01400 0x100>;
559			clocks = <&osc24M>, <&osc32k>, <&iosc>,
560				 <&ccu 11>;
561			clock-names = "hosc", "losc", "iosc", "pll-periph";
562			#clock-cells = <1>;
563			#reset-cells = <1>;
564		};
565
566		r_pio: pinctrl@1f02c00 {
567			compatible = "allwinner,sun50i-a64-r-pinctrl";
568			reg = <0x01f02c00 0x400>;
569			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
570			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
571			clock-names = "apb", "hosc", "losc";
572			gpio-controller;
573			#gpio-cells = <3>;
574			interrupt-controller;
575			#interrupt-cells = <3>;
576
577			r_rsb_pins: rsb {
578				pins = "PL0", "PL1";
579				function = "s_rsb";
580			};
581		};
582
583		r_rsb: rsb@1f03400 {
584			compatible = "allwinner,sun8i-a23-rsb";
585			reg = <0x01f03400 0x400>;
586			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
587			clocks = <&r_ccu 6>;
588			clock-frequency = <3000000>;
589			resets = <&r_ccu 2>;
590			pinctrl-names = "default";
591			pinctrl-0 = <&r_rsb_pins>;
592			status = "disabled";
593			#address-cells = <1>;
594			#size-cells = <0>;
595		};
596	};
597};
598