1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-r-ccu.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/reset/sun50i-a64-ccu.h> 49 50/ { 51 interrupt-parent = <&gic>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu0: cpu@0 { 60 compatible = "arm,cortex-a53", "arm,armv8"; 61 device_type = "cpu"; 62 reg = <0>; 63 enable-method = "psci"; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 device_type = "cpu"; 69 reg = <1>; 70 enable-method = "psci"; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53", "arm,armv8"; 75 device_type = "cpu"; 76 reg = <2>; 77 enable-method = "psci"; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <3>; 84 enable-method = "psci"; 85 }; 86 }; 87 88 osc24M: osc24M_clk { 89 #clock-cells = <0>; 90 compatible = "fixed-clock"; 91 clock-frequency = <24000000>; 92 clock-output-names = "osc24M"; 93 }; 94 95 osc32k: osc32k_clk { 96 #clock-cells = <0>; 97 compatible = "fixed-clock"; 98 clock-frequency = <32768>; 99 clock-output-names = "osc32k"; 100 }; 101 102 iosc: internal-osc-clk { 103 #clock-cells = <0>; 104 compatible = "fixed-clock"; 105 clock-frequency = <16000000>; 106 clock-accuracy = <300000000>; 107 clock-output-names = "iosc"; 108 }; 109 110 psci { 111 compatible = "arm,psci-0.2"; 112 method = "smc"; 113 }; 114 115 sound_spdif { 116 compatible = "simple-audio-card"; 117 simple-audio-card,name = "On-board SPDIF"; 118 119 simple-audio-card,cpu { 120 sound-dai = <&spdif>; 121 }; 122 123 simple-audio-card,codec { 124 sound-dai = <&spdif_out>; 125 }; 126 }; 127 128 spdif_out: spdif-out { 129 #sound-dai-cells = <0>; 130 compatible = "linux,spdif-dit"; 131 }; 132 133 timer { 134 compatible = "arm,armv8-timer"; 135 interrupts = <GIC_PPI 13 136 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 137 <GIC_PPI 14 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 139 <GIC_PPI 11 140 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 141 <GIC_PPI 10 142 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 143 }; 144 145 soc { 146 compatible = "simple-bus"; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 ranges; 150 151 syscon: syscon@1c00000 { 152 compatible = "allwinner,sun50i-a64-system-controller", 153 "syscon"; 154 reg = <0x01c00000 0x1000>; 155 }; 156 157 dma: dma-controller@1c02000 { 158 compatible = "allwinner,sun50i-a64-dma"; 159 reg = <0x01c02000 0x1000>; 160 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&ccu CLK_BUS_DMA>; 162 dma-channels = <8>; 163 dma-requests = <27>; 164 resets = <&ccu RST_BUS_DMA>; 165 #dma-cells = <1>; 166 }; 167 168 mmc0: mmc@1c0f000 { 169 compatible = "allwinner,sun50i-a64-mmc"; 170 reg = <0x01c0f000 0x1000>; 171 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 172 clock-names = "ahb", "mmc"; 173 resets = <&ccu RST_BUS_MMC0>; 174 reset-names = "ahb"; 175 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 176 max-frequency = <150000000>; 177 status = "disabled"; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 }; 181 182 mmc1: mmc@1c10000 { 183 compatible = "allwinner,sun50i-a64-mmc"; 184 reg = <0x01c10000 0x1000>; 185 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 186 clock-names = "ahb", "mmc"; 187 resets = <&ccu RST_BUS_MMC1>; 188 reset-names = "ahb"; 189 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 190 max-frequency = <150000000>; 191 status = "disabled"; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 }; 195 196 mmc2: mmc@1c11000 { 197 compatible = "allwinner,sun50i-a64-emmc"; 198 reg = <0x01c11000 0x1000>; 199 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 200 clock-names = "ahb", "mmc"; 201 resets = <&ccu RST_BUS_MMC2>; 202 reset-names = "ahb"; 203 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 204 max-frequency = <200000000>; 205 status = "disabled"; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 }; 209 210 usb_otg: usb@1c19000 { 211 compatible = "allwinner,sun8i-a33-musb"; 212 reg = <0x01c19000 0x0400>; 213 clocks = <&ccu CLK_BUS_OTG>; 214 resets = <&ccu RST_BUS_OTG>; 215 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "mc"; 217 phys = <&usbphy 0>; 218 phy-names = "usb"; 219 extcon = <&usbphy 0>; 220 status = "disabled"; 221 }; 222 223 usbphy: phy@1c19400 { 224 compatible = "allwinner,sun50i-a64-usb-phy"; 225 reg = <0x01c19400 0x14>, 226 <0x01c1a800 0x4>, 227 <0x01c1b800 0x4>; 228 reg-names = "phy_ctrl", 229 "pmu0", 230 "pmu1"; 231 clocks = <&ccu CLK_USB_PHY0>, 232 <&ccu CLK_USB_PHY1>; 233 clock-names = "usb0_phy", 234 "usb1_phy"; 235 resets = <&ccu RST_USB_PHY0>, 236 <&ccu RST_USB_PHY1>; 237 reset-names = "usb0_reset", 238 "usb1_reset"; 239 status = "disabled"; 240 #phy-cells = <1>; 241 }; 242 243 ehci0: usb@1c1a000 { 244 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 245 reg = <0x01c1a000 0x100>; 246 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&ccu CLK_BUS_OHCI0>, 248 <&ccu CLK_BUS_EHCI0>, 249 <&ccu CLK_USB_OHCI0>; 250 resets = <&ccu RST_BUS_OHCI0>, 251 <&ccu RST_BUS_EHCI0>; 252 status = "disabled"; 253 }; 254 255 ohci0: usb@1c1a400 { 256 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 257 reg = <0x01c1a400 0x100>; 258 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&ccu CLK_BUS_OHCI0>, 260 <&ccu CLK_USB_OHCI0>; 261 resets = <&ccu RST_BUS_OHCI0>; 262 status = "disabled"; 263 }; 264 265 ehci1: usb@1c1b000 { 266 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 267 reg = <0x01c1b000 0x100>; 268 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&ccu CLK_BUS_OHCI1>, 270 <&ccu CLK_BUS_EHCI1>, 271 <&ccu CLK_USB_OHCI1>; 272 resets = <&ccu RST_BUS_OHCI1>, 273 <&ccu RST_BUS_EHCI1>; 274 phys = <&usbphy 1>; 275 phy-names = "usb"; 276 status = "disabled"; 277 }; 278 279 ohci1: usb@1c1b400 { 280 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 281 reg = <0x01c1b400 0x100>; 282 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&ccu CLK_BUS_OHCI1>, 284 <&ccu CLK_USB_OHCI1>; 285 resets = <&ccu RST_BUS_OHCI1>; 286 phys = <&usbphy 1>; 287 phy-names = "usb"; 288 status = "disabled"; 289 }; 290 291 ccu: clock@1c20000 { 292 compatible = "allwinner,sun50i-a64-ccu"; 293 reg = <0x01c20000 0x400>; 294 clocks = <&osc24M>, <&osc32k>; 295 clock-names = "hosc", "losc"; 296 #clock-cells = <1>; 297 #reset-cells = <1>; 298 }; 299 300 pio: pinctrl@1c20800 { 301 compatible = "allwinner,sun50i-a64-pinctrl"; 302 reg = <0x01c20800 0x400>; 303 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&ccu 58>; 307 gpio-controller; 308 #gpio-cells = <3>; 309 interrupt-controller; 310 #interrupt-cells = <3>; 311 312 i2c0_pins: i2c0_pins { 313 pins = "PH0", "PH1"; 314 function = "i2c0"; 315 }; 316 317 i2c1_pins: i2c1_pins { 318 pins = "PH2", "PH3"; 319 function = "i2c1"; 320 }; 321 322 mmc0_pins: mmc0-pins { 323 pins = "PF0", "PF1", "PF2", "PF3", 324 "PF4", "PF5"; 325 function = "mmc0"; 326 drive-strength = <30>; 327 bias-pull-up; 328 }; 329 330 mmc1_pins: mmc1-pins { 331 pins = "PG0", "PG1", "PG2", "PG3", 332 "PG4", "PG5"; 333 function = "mmc1"; 334 drive-strength = <30>; 335 bias-pull-up; 336 }; 337 338 mmc2_pins: mmc2-pins { 339 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 340 "PC10","PC11", "PC12", "PC13", 341 "PC14", "PC15", "PC16"; 342 function = "mmc2"; 343 drive-strength = <30>; 344 bias-pull-up; 345 }; 346 347 rmii_pins: rmii_pins { 348 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 349 "PD18", "PD19", "PD20", "PD22", "PD23"; 350 function = "emac"; 351 drive-strength = <40>; 352 }; 353 354 rgmii_pins: rgmii_pins { 355 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 356 "PD13", "PD15", "PD16", "PD17", "PD18", 357 "PD19", "PD20", "PD21", "PD22", "PD23"; 358 function = "emac"; 359 drive-strength = <40>; 360 }; 361 362 spdif_tx_pin: spdif { 363 pins = "PH8"; 364 function = "spdif"; 365 }; 366 367 spi0_pins: spi0 { 368 pins = "PC0", "PC1", "PC2", "PC3"; 369 function = "spi0"; 370 }; 371 372 spi1_pins: spi1 { 373 pins = "PD0", "PD1", "PD2", "PD3"; 374 function = "spi1"; 375 }; 376 377 uart0_pins_a: uart0 { 378 pins = "PB8", "PB9"; 379 function = "uart0"; 380 }; 381 382 uart1_pins: uart1_pins { 383 pins = "PG6", "PG7"; 384 function = "uart1"; 385 }; 386 387 uart1_rts_cts_pins: uart1_rts_cts_pins { 388 pins = "PG8", "PG9"; 389 function = "uart1"; 390 }; 391 392 uart2_pins: uart2-pins { 393 pins = "PB0", "PB1"; 394 function = "uart2"; 395 }; 396 397 uart3_pins: uart3-pins { 398 pins = "PD0", "PD1"; 399 function = "uart3"; 400 }; 401 402 uart4_pins: uart4-pins { 403 pins = "PD2", "PD3"; 404 function = "uart4"; 405 }; 406 407 uart4_rts_cts_pins: uart4-rts-cts-pins { 408 pins = "PD4", "PD5"; 409 function = "uart4"; 410 }; 411 }; 412 413 spdif: spdif@1c21000 { 414 #sound-dai-cells = <0>; 415 compatible = "allwinner,sun50i-a64-spdif", 416 "allwinner,sun8i-h3-spdif"; 417 reg = <0x01c21000 0x400>; 418 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 420 resets = <&ccu RST_BUS_SPDIF>; 421 clock-names = "apb", "spdif"; 422 dmas = <&dma 2>; 423 dma-names = "tx"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&spdif_tx_pin>; 426 status = "disabled"; 427 }; 428 429 i2s0: i2s@1c22000 { 430 #sound-dai-cells = <0>; 431 compatible = "allwinner,sun50i-a64-i2s", 432 "allwinner,sun8i-h3-i2s"; 433 reg = <0x01c22000 0x400>; 434 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 436 clock-names = "apb", "mod"; 437 resets = <&ccu RST_BUS_I2S0>; 438 dma-names = "rx", "tx"; 439 dmas = <&dma 3>, <&dma 3>; 440 status = "disabled"; 441 }; 442 443 i2s1: i2s@1c22400 { 444 #sound-dai-cells = <0>; 445 compatible = "allwinner,sun50i-a64-i2s", 446 "allwinner,sun8i-h3-i2s"; 447 reg = <0x01c22400 0x400>; 448 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 450 clock-names = "apb", "mod"; 451 resets = <&ccu RST_BUS_I2S1>; 452 dma-names = "rx", "tx"; 453 dmas = <&dma 4>, <&dma 4>; 454 status = "disabled"; 455 }; 456 457 uart0: serial@1c28000 { 458 compatible = "snps,dw-apb-uart"; 459 reg = <0x01c28000 0x400>; 460 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 461 reg-shift = <2>; 462 reg-io-width = <4>; 463 clocks = <&ccu CLK_BUS_UART0>; 464 resets = <&ccu RST_BUS_UART0>; 465 status = "disabled"; 466 }; 467 468 uart1: serial@1c28400 { 469 compatible = "snps,dw-apb-uart"; 470 reg = <0x01c28400 0x400>; 471 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 472 reg-shift = <2>; 473 reg-io-width = <4>; 474 clocks = <&ccu CLK_BUS_UART1>; 475 resets = <&ccu RST_BUS_UART1>; 476 status = "disabled"; 477 }; 478 479 uart2: serial@1c28800 { 480 compatible = "snps,dw-apb-uart"; 481 reg = <0x01c28800 0x400>; 482 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 483 reg-shift = <2>; 484 reg-io-width = <4>; 485 clocks = <&ccu CLK_BUS_UART2>; 486 resets = <&ccu RST_BUS_UART2>; 487 status = "disabled"; 488 }; 489 490 uart3: serial@1c28c00 { 491 compatible = "snps,dw-apb-uart"; 492 reg = <0x01c28c00 0x400>; 493 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 494 reg-shift = <2>; 495 reg-io-width = <4>; 496 clocks = <&ccu CLK_BUS_UART3>; 497 resets = <&ccu RST_BUS_UART3>; 498 status = "disabled"; 499 }; 500 501 uart4: serial@1c29000 { 502 compatible = "snps,dw-apb-uart"; 503 reg = <0x01c29000 0x400>; 504 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 505 reg-shift = <2>; 506 reg-io-width = <4>; 507 clocks = <&ccu CLK_BUS_UART4>; 508 resets = <&ccu RST_BUS_UART4>; 509 status = "disabled"; 510 }; 511 512 i2c0: i2c@1c2ac00 { 513 compatible = "allwinner,sun6i-a31-i2c"; 514 reg = <0x01c2ac00 0x400>; 515 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&ccu CLK_BUS_I2C0>; 517 resets = <&ccu RST_BUS_I2C0>; 518 status = "disabled"; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 }; 522 523 i2c1: i2c@1c2b000 { 524 compatible = "allwinner,sun6i-a31-i2c"; 525 reg = <0x01c2b000 0x400>; 526 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&ccu CLK_BUS_I2C1>; 528 resets = <&ccu RST_BUS_I2C1>; 529 status = "disabled"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 }; 533 534 i2c2: i2c@1c2b400 { 535 compatible = "allwinner,sun6i-a31-i2c"; 536 reg = <0x01c2b400 0x400>; 537 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&ccu CLK_BUS_I2C2>; 539 resets = <&ccu RST_BUS_I2C2>; 540 status = "disabled"; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 }; 544 545 546 spi0: spi@1c68000 { 547 compatible = "allwinner,sun8i-h3-spi"; 548 reg = <0x01c68000 0x1000>; 549 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 551 clock-names = "ahb", "mod"; 552 dmas = <&dma 23>, <&dma 23>; 553 dma-names = "rx", "tx"; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&spi0_pins>; 556 resets = <&ccu RST_BUS_SPI0>; 557 status = "disabled"; 558 num-cs = <1>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 }; 562 563 spi1: spi@1c69000 { 564 compatible = "allwinner,sun8i-h3-spi"; 565 reg = <0x01c69000 0x1000>; 566 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 568 clock-names = "ahb", "mod"; 569 dmas = <&dma 24>, <&dma 24>; 570 dma-names = "rx", "tx"; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&spi1_pins>; 573 resets = <&ccu RST_BUS_SPI1>; 574 status = "disabled"; 575 num-cs = <1>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 }; 579 580 emac: ethernet@1c30000 { 581 compatible = "allwinner,sun50i-a64-emac"; 582 syscon = <&syscon>; 583 reg = <0x01c30000 0x10000>; 584 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 585 interrupt-names = "macirq"; 586 resets = <&ccu RST_BUS_EMAC>; 587 reset-names = "stmmaceth"; 588 clocks = <&ccu CLK_BUS_EMAC>; 589 clock-names = "stmmaceth"; 590 status = "disabled"; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 594 mdio: mdio { 595 compatible = "snps,dwmac-mdio"; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 }; 599 }; 600 601 gic: interrupt-controller@1c81000 { 602 compatible = "arm,gic-400"; 603 reg = <0x01c81000 0x1000>, 604 <0x01c82000 0x2000>, 605 <0x01c84000 0x2000>, 606 <0x01c86000 0x2000>; 607 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 608 interrupt-controller; 609 #interrupt-cells = <3>; 610 }; 611 612 rtc: rtc@1f00000 { 613 compatible = "allwinner,sun6i-a31-rtc"; 614 reg = <0x01f00000 0x54>; 615 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 617 }; 618 619 r_intc: interrupt-controller@1f00c00 { 620 compatible = "allwinner,sun50i-a64-r-intc", 621 "allwinner,sun6i-a31-r-intc"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 reg = <0x01f00c00 0x400>; 625 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 626 }; 627 628 r_ccu: clock@1f01400 { 629 compatible = "allwinner,sun50i-a64-r-ccu"; 630 reg = <0x01f01400 0x100>; 631 clocks = <&osc24M>, <&osc32k>, <&iosc>, 632 <&ccu 11>; 633 clock-names = "hosc", "losc", "iosc", "pll-periph"; 634 #clock-cells = <1>; 635 #reset-cells = <1>; 636 }; 637 638 r_pio: pinctrl@1f02c00 { 639 compatible = "allwinner,sun50i-a64-r-pinctrl"; 640 reg = <0x01f02c00 0x400>; 641 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 643 clock-names = "apb", "hosc", "losc"; 644 gpio-controller; 645 #gpio-cells = <3>; 646 interrupt-controller; 647 #interrupt-cells = <3>; 648 649 r_rsb_pins: rsb { 650 pins = "PL0", "PL1"; 651 function = "s_rsb"; 652 }; 653 }; 654 655 r_rsb: rsb@1f03400 { 656 compatible = "allwinner,sun8i-a23-rsb"; 657 reg = <0x01f03400 0x400>; 658 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&r_ccu 6>; 660 clock-frequency = <3000000>; 661 resets = <&r_ccu 2>; 662 pinctrl-names = "default"; 663 pinctrl-0 = <&r_rsb_pins>; 664 status = "disabled"; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 }; 668 }; 669}; 670