1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53", "arm,armv8"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53", "arm,armv8"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "osc32k"; 143 }; 144 145 iosc: internal-osc-clk { 146 #clock-cells = <0>; 147 compatible = "fixed-clock"; 148 clock-frequency = <16000000>; 149 clock-accuracy = <300000000>; 150 clock-output-names = "iosc"; 151 }; 152 153 psci { 154 compatible = "arm,psci-0.2"; 155 method = "smc"; 156 }; 157 158 sound: sound { 159 compatible = "simple-audio-card"; 160 simple-audio-card,name = "sun50i-a64-audio"; 161 simple-audio-card,format = "i2s"; 162 simple-audio-card,frame-master = <&cpudai>; 163 simple-audio-card,bitclock-master = <&cpudai>; 164 simple-audio-card,mclk-fs = <128>; 165 simple-audio-card,aux-devs = <&codec_analog>; 166 simple-audio-card,routing = 167 "Left DAC", "AIF1 Slot 0 Left", 168 "Right DAC", "AIF1 Slot 0 Right", 169 "AIF1 Slot 0 Left ADC", "Left ADC", 170 "AIF1 Slot 0 Right ADC", "Right ADC"; 171 status = "disabled"; 172 173 cpudai: simple-audio-card,cpu { 174 sound-dai = <&dai>; 175 }; 176 177 link_codec: simple-audio-card,codec { 178 sound-dai = <&codec>; 179 }; 180 }; 181 182 sound_spdif { 183 compatible = "simple-audio-card"; 184 simple-audio-card,name = "On-board SPDIF"; 185 186 simple-audio-card,cpu { 187 sound-dai = <&spdif>; 188 }; 189 190 simple-audio-card,codec { 191 sound-dai = <&spdif_out>; 192 }; 193 }; 194 195 spdif_out: spdif-out { 196 #sound-dai-cells = <0>; 197 compatible = "linux,spdif-dit"; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupts = <GIC_PPI 13 203 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 204 <GIC_PPI 14 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 11 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 10 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 210 }; 211 212 soc { 213 compatible = "simple-bus"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges; 217 218 de2@1000000 { 219 compatible = "allwinner,sun50i-a64-de2"; 220 reg = <0x1000000 0x400000>; 221 allwinner,sram = <&de2_sram 1>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x1000000 0x400000>; 225 226 display_clocks: clock@0 { 227 compatible = "allwinner,sun50i-a64-de2-clk"; 228 reg = <0x0 0x100000>; 229 clocks = <&ccu CLK_DE>, 230 <&ccu CLK_BUS_DE>; 231 clock-names = "mod", 232 "bus"; 233 resets = <&ccu RST_BUS_DE>; 234 #clock-cells = <1>; 235 #reset-cells = <1>; 236 }; 237 238 mixer0: mixer@100000 { 239 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 240 reg = <0x100000 0x100000>; 241 clocks = <&display_clocks CLK_BUS_MIXER0>, 242 <&display_clocks CLK_MIXER0>; 243 clock-names = "bus", 244 "mod"; 245 resets = <&display_clocks RST_MIXER0>; 246 247 ports { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 mixer0_out: port@1 { 252 reg = <1>; 253 254 mixer0_out_tcon0: endpoint { 255 remote-endpoint = <&tcon0_in_mixer0>; 256 }; 257 }; 258 }; 259 }; 260 261 mixer1: mixer@200000 { 262 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 263 reg = <0x200000 0x100000>; 264 clocks = <&display_clocks CLK_BUS_MIXER1>, 265 <&display_clocks CLK_MIXER1>; 266 clock-names = "bus", 267 "mod"; 268 resets = <&display_clocks RST_MIXER1>; 269 270 ports { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 mixer1_out: port@1 { 275 reg = <1>; 276 277 mixer1_out_tcon1: endpoint { 278 remote-endpoint = <&tcon1_in_mixer1>; 279 }; 280 }; 281 }; 282 }; 283 }; 284 285 syscon: syscon@1c00000 { 286 compatible = "allwinner,sun50i-a64-system-control"; 287 reg = <0x01c00000 0x1000>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges; 291 292 sram_c: sram@18000 { 293 compatible = "mmio-sram"; 294 reg = <0x00018000 0x28000>; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 ranges = <0 0x00018000 0x28000>; 298 299 de2_sram: sram-section@0 { 300 compatible = "allwinner,sun50i-a64-sram-c"; 301 reg = <0x0000 0x28000>; 302 }; 303 }; 304 305 sram_c1: sram@1d00000 { 306 compatible = "mmio-sram"; 307 reg = <0x01d00000 0x40000>; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges = <0 0x01d00000 0x40000>; 311 312 ve_sram: sram-section@0 { 313 compatible = "allwinner,sun50i-a64-sram-c1", 314 "allwinner,sun4i-a10-sram-c1"; 315 reg = <0x000000 0x40000>; 316 }; 317 }; 318 }; 319 320 dma: dma-controller@1c02000 { 321 compatible = "allwinner,sun50i-a64-dma"; 322 reg = <0x01c02000 0x1000>; 323 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&ccu CLK_BUS_DMA>; 325 dma-channels = <8>; 326 dma-requests = <27>; 327 resets = <&ccu RST_BUS_DMA>; 328 #dma-cells = <1>; 329 }; 330 331 tcon0: lcd-controller@1c0c000 { 332 compatible = "allwinner,sun50i-a64-tcon-lcd", 333 "allwinner,sun8i-a83t-tcon-lcd"; 334 reg = <0x01c0c000 0x1000>; 335 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 337 clock-names = "ahb", "tcon-ch0"; 338 clock-output-names = "tcon-pixel-clock"; 339 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 340 reset-names = "lcd", "lvds"; 341 342 ports { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 346 tcon0_in: port@0 { 347 #address-cells = <1>; 348 #size-cells = <0>; 349 reg = <0>; 350 351 tcon0_in_mixer0: endpoint@0 { 352 reg = <0>; 353 remote-endpoint = <&mixer0_out_tcon0>; 354 }; 355 }; 356 357 tcon0_out: port@1 { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 reg = <1>; 361 }; 362 }; 363 }; 364 365 tcon1: lcd-controller@1c0d000 { 366 compatible = "allwinner,sun50i-a64-tcon-tv", 367 "allwinner,sun8i-a83t-tcon-tv"; 368 reg = <0x01c0d000 0x1000>; 369 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 371 clock-names = "ahb", "tcon-ch1"; 372 resets = <&ccu RST_BUS_TCON1>; 373 reset-names = "lcd"; 374 375 ports { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 379 tcon1_in: port@0 { 380 reg = <0>; 381 382 tcon1_in_mixer1: endpoint { 383 remote-endpoint = <&mixer1_out_tcon1>; 384 }; 385 }; 386 387 tcon1_out: port@1 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <1>; 391 392 tcon1_out_hdmi: endpoint@1 { 393 reg = <1>; 394 remote-endpoint = <&hdmi_in_tcon1>; 395 }; 396 }; 397 }; 398 }; 399 400 mmc0: mmc@1c0f000 { 401 compatible = "allwinner,sun50i-a64-mmc"; 402 reg = <0x01c0f000 0x1000>; 403 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 404 clock-names = "ahb", "mmc"; 405 resets = <&ccu RST_BUS_MMC0>; 406 reset-names = "ahb"; 407 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 408 max-frequency = <150000000>; 409 status = "disabled"; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 }; 413 414 mmc1: mmc@1c10000 { 415 compatible = "allwinner,sun50i-a64-mmc"; 416 reg = <0x01c10000 0x1000>; 417 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 418 clock-names = "ahb", "mmc"; 419 resets = <&ccu RST_BUS_MMC1>; 420 reset-names = "ahb"; 421 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 422 max-frequency = <150000000>; 423 status = "disabled"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 }; 427 428 mmc2: mmc@1c11000 { 429 compatible = "allwinner,sun50i-a64-emmc"; 430 reg = <0x01c11000 0x1000>; 431 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 432 clock-names = "ahb", "mmc"; 433 resets = <&ccu RST_BUS_MMC2>; 434 reset-names = "ahb"; 435 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 436 max-frequency = <200000000>; 437 status = "disabled"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 }; 441 442 sid: eeprom@1c14000 { 443 compatible = "allwinner,sun50i-a64-sid"; 444 reg = <0x1c14000 0x400>; 445 }; 446 447 usb_otg: usb@1c19000 { 448 compatible = "allwinner,sun8i-a33-musb"; 449 reg = <0x01c19000 0x0400>; 450 clocks = <&ccu CLK_BUS_OTG>; 451 resets = <&ccu RST_BUS_OTG>; 452 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-names = "mc"; 454 phys = <&usbphy 0>; 455 phy-names = "usb"; 456 extcon = <&usbphy 0>; 457 status = "disabled"; 458 }; 459 460 usbphy: phy@1c19400 { 461 compatible = "allwinner,sun50i-a64-usb-phy"; 462 reg = <0x01c19400 0x14>, 463 <0x01c1a800 0x4>, 464 <0x01c1b800 0x4>; 465 reg-names = "phy_ctrl", 466 "pmu0", 467 "pmu1"; 468 clocks = <&ccu CLK_USB_PHY0>, 469 <&ccu CLK_USB_PHY1>; 470 clock-names = "usb0_phy", 471 "usb1_phy"; 472 resets = <&ccu RST_USB_PHY0>, 473 <&ccu RST_USB_PHY1>; 474 reset-names = "usb0_reset", 475 "usb1_reset"; 476 status = "disabled"; 477 #phy-cells = <1>; 478 }; 479 480 ehci0: usb@1c1a000 { 481 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 482 reg = <0x01c1a000 0x100>; 483 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&ccu CLK_BUS_OHCI0>, 485 <&ccu CLK_BUS_EHCI0>, 486 <&ccu CLK_USB_OHCI0>; 487 resets = <&ccu RST_BUS_OHCI0>, 488 <&ccu RST_BUS_EHCI0>; 489 status = "disabled"; 490 }; 491 492 ohci0: usb@1c1a400 { 493 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 494 reg = <0x01c1a400 0x100>; 495 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&ccu CLK_BUS_OHCI0>, 497 <&ccu CLK_USB_OHCI0>; 498 resets = <&ccu RST_BUS_OHCI0>; 499 status = "disabled"; 500 }; 501 502 ehci1: usb@1c1b000 { 503 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 504 reg = <0x01c1b000 0x100>; 505 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&ccu CLK_BUS_OHCI1>, 507 <&ccu CLK_BUS_EHCI1>, 508 <&ccu CLK_USB_OHCI1>; 509 resets = <&ccu RST_BUS_OHCI1>, 510 <&ccu RST_BUS_EHCI1>; 511 phys = <&usbphy 1>; 512 phy-names = "usb"; 513 status = "disabled"; 514 }; 515 516 ohci1: usb@1c1b400 { 517 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 518 reg = <0x01c1b400 0x100>; 519 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&ccu CLK_BUS_OHCI1>, 521 <&ccu CLK_USB_OHCI1>; 522 resets = <&ccu RST_BUS_OHCI1>; 523 phys = <&usbphy 1>; 524 phy-names = "usb"; 525 status = "disabled"; 526 }; 527 528 ccu: clock@1c20000 { 529 compatible = "allwinner,sun50i-a64-ccu"; 530 reg = <0x01c20000 0x400>; 531 clocks = <&osc24M>, <&osc32k>; 532 clock-names = "hosc", "losc"; 533 #clock-cells = <1>; 534 #reset-cells = <1>; 535 }; 536 537 pio: pinctrl@1c20800 { 538 compatible = "allwinner,sun50i-a64-pinctrl"; 539 reg = <0x01c20800 0x400>; 540 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&ccu 58>; 544 gpio-controller; 545 #gpio-cells = <3>; 546 interrupt-controller; 547 #interrupt-cells = <3>; 548 549 i2c0_pins: i2c0_pins { 550 pins = "PH0", "PH1"; 551 function = "i2c0"; 552 }; 553 554 i2c1_pins: i2c1_pins { 555 pins = "PH2", "PH3"; 556 function = "i2c1"; 557 }; 558 559 mmc0_pins: mmc0-pins { 560 pins = "PF0", "PF1", "PF2", "PF3", 561 "PF4", "PF5"; 562 function = "mmc0"; 563 drive-strength = <30>; 564 bias-pull-up; 565 }; 566 567 mmc1_pins: mmc1-pins { 568 pins = "PG0", "PG1", "PG2", "PG3", 569 "PG4", "PG5"; 570 function = "mmc1"; 571 drive-strength = <30>; 572 bias-pull-up; 573 }; 574 575 mmc2_pins: mmc2-pins { 576 pins = "PC5", "PC6", "PC8", "PC9", 577 "PC10","PC11", "PC12", "PC13", 578 "PC14", "PC15", "PC16"; 579 function = "mmc2"; 580 drive-strength = <30>; 581 bias-pull-up; 582 }; 583 584 mmc2_ds_pin: mmc2-ds-pin { 585 pins = "PC1"; 586 function = "mmc2"; 587 drive-strength = <30>; 588 bias-pull-up; 589 }; 590 591 pwm_pin: pwm_pin { 592 pins = "PD22"; 593 function = "pwm"; 594 }; 595 596 rmii_pins: rmii_pins { 597 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 598 "PD18", "PD19", "PD20", "PD22", "PD23"; 599 function = "emac"; 600 drive-strength = <40>; 601 }; 602 603 rgmii_pins: rgmii_pins { 604 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 605 "PD13", "PD15", "PD16", "PD17", "PD18", 606 "PD19", "PD20", "PD21", "PD22", "PD23"; 607 function = "emac"; 608 drive-strength = <40>; 609 }; 610 611 spdif_tx_pin: spdif { 612 pins = "PH8"; 613 function = "spdif"; 614 }; 615 616 spi0_pins: spi0 { 617 pins = "PC0", "PC1", "PC2", "PC3"; 618 function = "spi0"; 619 }; 620 621 spi1_pins: spi1 { 622 pins = "PD0", "PD1", "PD2", "PD3"; 623 function = "spi1"; 624 }; 625 626 uart0_pb_pins: uart0-pb-pins { 627 pins = "PB8", "PB9"; 628 function = "uart0"; 629 }; 630 631 uart1_pins: uart1_pins { 632 pins = "PG6", "PG7"; 633 function = "uart1"; 634 }; 635 636 uart1_rts_cts_pins: uart1_rts_cts_pins { 637 pins = "PG8", "PG9"; 638 function = "uart1"; 639 }; 640 641 uart2_pins: uart2-pins { 642 pins = "PB0", "PB1"; 643 function = "uart2"; 644 }; 645 646 uart3_pins: uart3-pins { 647 pins = "PD0", "PD1"; 648 function = "uart3"; 649 }; 650 651 uart4_pins: uart4-pins { 652 pins = "PD2", "PD3"; 653 function = "uart4"; 654 }; 655 656 uart4_rts_cts_pins: uart4-rts-cts-pins { 657 pins = "PD4", "PD5"; 658 function = "uart4"; 659 }; 660 }; 661 662 spdif: spdif@1c21000 { 663 #sound-dai-cells = <0>; 664 compatible = "allwinner,sun50i-a64-spdif", 665 "allwinner,sun8i-h3-spdif"; 666 reg = <0x01c21000 0x400>; 667 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 669 resets = <&ccu RST_BUS_SPDIF>; 670 clock-names = "apb", "spdif"; 671 dmas = <&dma 2>; 672 dma-names = "tx"; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&spdif_tx_pin>; 675 status = "disabled"; 676 }; 677 678 i2s0: i2s@1c22000 { 679 #sound-dai-cells = <0>; 680 compatible = "allwinner,sun50i-a64-i2s", 681 "allwinner,sun8i-h3-i2s"; 682 reg = <0x01c22000 0x400>; 683 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 685 clock-names = "apb", "mod"; 686 resets = <&ccu RST_BUS_I2S0>; 687 dma-names = "rx", "tx"; 688 dmas = <&dma 3>, <&dma 3>; 689 status = "disabled"; 690 }; 691 692 i2s1: i2s@1c22400 { 693 #sound-dai-cells = <0>; 694 compatible = "allwinner,sun50i-a64-i2s", 695 "allwinner,sun8i-h3-i2s"; 696 reg = <0x01c22400 0x400>; 697 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 699 clock-names = "apb", "mod"; 700 resets = <&ccu RST_BUS_I2S1>; 701 dma-names = "rx", "tx"; 702 dmas = <&dma 4>, <&dma 4>; 703 status = "disabled"; 704 }; 705 706 dai: dai@1c22c00 { 707 #sound-dai-cells = <0>; 708 compatible = "allwinner,sun50i-a64-codec-i2s"; 709 reg = <0x01c22c00 0x200>; 710 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 712 clock-names = "apb", "mod"; 713 resets = <&ccu RST_BUS_CODEC>; 714 reset-names = "rst"; 715 dmas = <&dma 15>, <&dma 15>; 716 dma-names = "rx", "tx"; 717 status = "disabled"; 718 }; 719 720 codec: codec@1c22e00 { 721 #sound-dai-cells = <0>; 722 compatible = "allwinner,sun8i-a33-codec"; 723 reg = <0x01c22e00 0x600>; 724 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 726 clock-names = "bus", "mod"; 727 status = "disabled"; 728 }; 729 730 uart0: serial@1c28000 { 731 compatible = "snps,dw-apb-uart"; 732 reg = <0x01c28000 0x400>; 733 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 734 reg-shift = <2>; 735 reg-io-width = <4>; 736 clocks = <&ccu CLK_BUS_UART0>; 737 resets = <&ccu RST_BUS_UART0>; 738 status = "disabled"; 739 }; 740 741 uart1: serial@1c28400 { 742 compatible = "snps,dw-apb-uart"; 743 reg = <0x01c28400 0x400>; 744 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 745 reg-shift = <2>; 746 reg-io-width = <4>; 747 clocks = <&ccu CLK_BUS_UART1>; 748 resets = <&ccu RST_BUS_UART1>; 749 status = "disabled"; 750 }; 751 752 uart2: serial@1c28800 { 753 compatible = "snps,dw-apb-uart"; 754 reg = <0x01c28800 0x400>; 755 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 756 reg-shift = <2>; 757 reg-io-width = <4>; 758 clocks = <&ccu CLK_BUS_UART2>; 759 resets = <&ccu RST_BUS_UART2>; 760 status = "disabled"; 761 }; 762 763 uart3: serial@1c28c00 { 764 compatible = "snps,dw-apb-uart"; 765 reg = <0x01c28c00 0x400>; 766 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 767 reg-shift = <2>; 768 reg-io-width = <4>; 769 clocks = <&ccu CLK_BUS_UART3>; 770 resets = <&ccu RST_BUS_UART3>; 771 status = "disabled"; 772 }; 773 774 uart4: serial@1c29000 { 775 compatible = "snps,dw-apb-uart"; 776 reg = <0x01c29000 0x400>; 777 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 778 reg-shift = <2>; 779 reg-io-width = <4>; 780 clocks = <&ccu CLK_BUS_UART4>; 781 resets = <&ccu RST_BUS_UART4>; 782 status = "disabled"; 783 }; 784 785 i2c0: i2c@1c2ac00 { 786 compatible = "allwinner,sun6i-a31-i2c"; 787 reg = <0x01c2ac00 0x400>; 788 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&ccu CLK_BUS_I2C0>; 790 resets = <&ccu RST_BUS_I2C0>; 791 status = "disabled"; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 }; 795 796 i2c1: i2c@1c2b000 { 797 compatible = "allwinner,sun6i-a31-i2c"; 798 reg = <0x01c2b000 0x400>; 799 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&ccu CLK_BUS_I2C1>; 801 resets = <&ccu RST_BUS_I2C1>; 802 status = "disabled"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 }; 806 807 i2c2: i2c@1c2b400 { 808 compatible = "allwinner,sun6i-a31-i2c"; 809 reg = <0x01c2b400 0x400>; 810 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&ccu CLK_BUS_I2C2>; 812 resets = <&ccu RST_BUS_I2C2>; 813 status = "disabled"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 }; 817 818 819 spi0: spi@1c68000 { 820 compatible = "allwinner,sun8i-h3-spi"; 821 reg = <0x01c68000 0x1000>; 822 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 824 clock-names = "ahb", "mod"; 825 dmas = <&dma 23>, <&dma 23>; 826 dma-names = "rx", "tx"; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&spi0_pins>; 829 resets = <&ccu RST_BUS_SPI0>; 830 status = "disabled"; 831 num-cs = <1>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 }; 835 836 spi1: spi@1c69000 { 837 compatible = "allwinner,sun8i-h3-spi"; 838 reg = <0x01c69000 0x1000>; 839 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 841 clock-names = "ahb", "mod"; 842 dmas = <&dma 24>, <&dma 24>; 843 dma-names = "rx", "tx"; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&spi1_pins>; 846 resets = <&ccu RST_BUS_SPI1>; 847 status = "disabled"; 848 num-cs = <1>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 }; 852 853 emac: ethernet@1c30000 { 854 compatible = "allwinner,sun50i-a64-emac"; 855 syscon = <&syscon>; 856 reg = <0x01c30000 0x10000>; 857 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 858 interrupt-names = "macirq"; 859 resets = <&ccu RST_BUS_EMAC>; 860 reset-names = "stmmaceth"; 861 clocks = <&ccu CLK_BUS_EMAC>; 862 clock-names = "stmmaceth"; 863 status = "disabled"; 864 865 mdio: mdio { 866 compatible = "snps,dwmac-mdio"; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 }; 870 }; 871 872 mali: gpu@1c40000 { 873 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 874 reg = <0x01c40000 0x10000>; 875 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 882 interrupt-names = "gp", 883 "gpmmu", 884 "pp0", 885 "ppmmu0", 886 "pp1", 887 "ppmmu1", 888 "pmu"; 889 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 890 clock-names = "bus", "core"; 891 resets = <&ccu RST_BUS_GPU>; 892 }; 893 894 gic: interrupt-controller@1c81000 { 895 compatible = "arm,gic-400"; 896 reg = <0x01c81000 0x1000>, 897 <0x01c82000 0x2000>, 898 <0x01c84000 0x2000>, 899 <0x01c86000 0x2000>; 900 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 901 interrupt-controller; 902 #interrupt-cells = <3>; 903 }; 904 905 pwm: pwm@1c21400 { 906 compatible = "allwinner,sun50i-a64-pwm", 907 "allwinner,sun5i-a13-pwm"; 908 reg = <0x01c21400 0x400>; 909 clocks = <&osc24M>; 910 pinctrl-names = "default"; 911 pinctrl-0 = <&pwm_pin>; 912 #pwm-cells = <3>; 913 status = "disabled"; 914 }; 915 916 hdmi: hdmi@1ee0000 { 917 compatible = "allwinner,sun50i-a64-dw-hdmi", 918 "allwinner,sun8i-a83t-dw-hdmi"; 919 reg = <0x01ee0000 0x10000>; 920 reg-io-width = <1>; 921 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 923 <&ccu CLK_HDMI>; 924 clock-names = "iahb", "isfr", "tmds"; 925 resets = <&ccu RST_BUS_HDMI1>; 926 reset-names = "ctrl"; 927 phys = <&hdmi_phy>; 928 phy-names = "hdmi-phy"; 929 status = "disabled"; 930 931 ports { 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 hdmi_in: port@0 { 936 reg = <0>; 937 938 hdmi_in_tcon1: endpoint { 939 remote-endpoint = <&tcon1_out_hdmi>; 940 }; 941 }; 942 943 hdmi_out: port@1 { 944 reg = <1>; 945 }; 946 }; 947 }; 948 949 hdmi_phy: hdmi-phy@1ef0000 { 950 compatible = "allwinner,sun50i-a64-hdmi-phy"; 951 reg = <0x01ef0000 0x10000>; 952 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 953 <&ccu 7>; 954 clock-names = "bus", "mod", "pll-0"; 955 resets = <&ccu RST_BUS_HDMI0>; 956 reset-names = "phy"; 957 #phy-cells = <0>; 958 }; 959 960 rtc: rtc@1f00000 { 961 compatible = "allwinner,sun6i-a31-rtc"; 962 reg = <0x01f00000 0x54>; 963 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 965 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 966 clocks = <&osc32k>; 967 #clock-cells = <1>; 968 }; 969 970 r_intc: interrupt-controller@1f00c00 { 971 compatible = "allwinner,sun50i-a64-r-intc", 972 "allwinner,sun6i-a31-r-intc"; 973 interrupt-controller; 974 #interrupt-cells = <2>; 975 reg = <0x01f00c00 0x400>; 976 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 977 }; 978 979 r_ccu: clock@1f01400 { 980 compatible = "allwinner,sun50i-a64-r-ccu"; 981 reg = <0x01f01400 0x100>; 982 clocks = <&osc24M>, <&osc32k>, <&iosc>, 983 <&ccu 11>; 984 clock-names = "hosc", "losc", "iosc", "pll-periph"; 985 #clock-cells = <1>; 986 #reset-cells = <1>; 987 }; 988 989 codec_analog: codec-analog@1f015c0 { 990 compatible = "allwinner,sun50i-a64-codec-analog"; 991 reg = <0x01f015c0 0x4>; 992 status = "disabled"; 993 }; 994 995 r_i2c: i2c@1f02400 { 996 compatible = "allwinner,sun50i-a64-i2c", 997 "allwinner,sun6i-a31-i2c"; 998 reg = <0x01f02400 0x400>; 999 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&r_ccu CLK_APB0_I2C>; 1001 resets = <&r_ccu RST_APB0_I2C>; 1002 status = "disabled"; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 }; 1006 1007 r_pwm: pwm@1f03800 { 1008 compatible = "allwinner,sun50i-a64-pwm", 1009 "allwinner,sun5i-a13-pwm"; 1010 reg = <0x01f03800 0x400>; 1011 clocks = <&osc24M>; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&r_pwm_pin>; 1014 #pwm-cells = <3>; 1015 status = "disabled"; 1016 }; 1017 1018 r_pio: pinctrl@1f02c00 { 1019 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1020 reg = <0x01f02c00 0x400>; 1021 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1023 clock-names = "apb", "hosc", "losc"; 1024 gpio-controller; 1025 #gpio-cells = <3>; 1026 interrupt-controller; 1027 #interrupt-cells = <3>; 1028 1029 r_i2c_pl89_pins: r-i2c-pl89-pins { 1030 pins = "PL8", "PL9"; 1031 function = "s_i2c"; 1032 }; 1033 1034 r_pwm_pin: pwm { 1035 pins = "PL10"; 1036 function = "s_pwm"; 1037 }; 1038 1039 r_rsb_pins: rsb { 1040 pins = "PL0", "PL1"; 1041 function = "s_rsb"; 1042 }; 1043 }; 1044 1045 r_rsb: rsb@1f03400 { 1046 compatible = "allwinner,sun8i-a23-rsb"; 1047 reg = <0x01f03400 0x400>; 1048 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&r_ccu 6>; 1050 clock-frequency = <3000000>; 1051 resets = <&r_ccu 2>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&r_rsb_pins>; 1054 status = "disabled"; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 }; 1058 1059 wdt0: watchdog@1c20ca0 { 1060 compatible = "allwinner,sun50i-a64-wdt", 1061 "allwinner,sun6i-a31-wdt"; 1062 reg = <0x01c20ca0 0x20>; 1063 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1064 }; 1065 }; 1066}; 1067