1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 sound: sound { 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "sun50i-a64-audio"; 162 simple-audio-card,format = "i2s"; 163 simple-audio-card,frame-master = <&cpudai>; 164 simple-audio-card,bitclock-master = <&cpudai>; 165 simple-audio-card,mclk-fs = <128>; 166 simple-audio-card,aux-devs = <&codec_analog>; 167 simple-audio-card,routing = 168 "Left DAC", "AIF1 Slot 0 Left", 169 "Right DAC", "AIF1 Slot 0 Right", 170 "AIF1 Slot 0 Left ADC", "Left ADC", 171 "AIF1 Slot 0 Right ADC", "Right ADC"; 172 status = "disabled"; 173 174 cpudai: simple-audio-card,cpu { 175 sound-dai = <&dai>; 176 }; 177 178 link_codec: simple-audio-card,codec { 179 sound-dai = <&codec>; 180 }; 181 }; 182 183 sound_spdif { 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "On-board SPDIF"; 186 187 simple-audio-card,cpu { 188 sound-dai = <&spdif>; 189 }; 190 191 simple-audio-card,codec { 192 sound-dai = <&spdif_out>; 193 }; 194 }; 195 196 spdif_out: spdif-out { 197 #sound-dai-cells = <0>; 198 compatible = "linux,spdif-dit"; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 allwinner,erratum-unknown1; 204 interrupts = <GIC_PPI 13 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 206 <GIC_PPI 14 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 208 <GIC_PPI 11 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 210 <GIC_PPI 10 211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 soc { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 bus@1000000 { 221 compatible = "allwinner,sun50i-a64-de2"; 222 reg = <0x1000000 0x400000>; 223 allwinner,sram = <&de2_sram 1>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0 0x1000000 0x400000>; 227 228 display_clocks: clock@0 { 229 compatible = "allwinner,sun50i-a64-de2-clk"; 230 reg = <0x0 0x100000>; 231 clocks = <&ccu CLK_BUS_DE>, 232 <&ccu CLK_DE>; 233 clock-names = "bus", 234 "mod"; 235 resets = <&ccu RST_BUS_DE>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 mixer0: mixer@100000 { 241 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 242 reg = <0x100000 0x100000>; 243 clocks = <&display_clocks CLK_BUS_MIXER0>, 244 <&display_clocks CLK_MIXER0>; 245 clock-names = "bus", 246 "mod"; 247 resets = <&display_clocks RST_MIXER0>; 248 249 ports { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 mixer0_out: port@1 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 reg = <1>; 257 258 mixer0_out_tcon0: endpoint@0 { 259 reg = <0>; 260 remote-endpoint = <&tcon0_in_mixer0>; 261 }; 262 263 mixer0_out_tcon1: endpoint@1 { 264 reg = <1>; 265 remote-endpoint = <&tcon1_in_mixer0>; 266 }; 267 }; 268 }; 269 }; 270 271 mixer1: mixer@200000 { 272 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 273 reg = <0x200000 0x100000>; 274 clocks = <&display_clocks CLK_BUS_MIXER1>, 275 <&display_clocks CLK_MIXER1>; 276 clock-names = "bus", 277 "mod"; 278 resets = <&display_clocks RST_MIXER1>; 279 280 ports { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 284 mixer1_out: port@1 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <1>; 288 289 mixer1_out_tcon0: endpoint@0 { 290 reg = <0>; 291 remote-endpoint = <&tcon0_in_mixer1>; 292 }; 293 294 mixer1_out_tcon1: endpoint@1 { 295 reg = <1>; 296 remote-endpoint = <&tcon1_in_mixer1>; 297 }; 298 }; 299 }; 300 }; 301 }; 302 303 syscon: syscon@1c00000 { 304 compatible = "allwinner,sun50i-a64-system-control"; 305 reg = <0x01c00000 0x1000>; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 ranges; 309 310 sram_c: sram@18000 { 311 compatible = "mmio-sram"; 312 reg = <0x00018000 0x28000>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 ranges = <0 0x00018000 0x28000>; 316 317 de2_sram: sram-section@0 { 318 compatible = "allwinner,sun50i-a64-sram-c"; 319 reg = <0x0000 0x28000>; 320 }; 321 }; 322 323 sram_c1: sram@1d00000 { 324 compatible = "mmio-sram"; 325 reg = <0x01d00000 0x40000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0 0x01d00000 0x40000>; 329 330 ve_sram: sram-section@0 { 331 compatible = "allwinner,sun50i-a64-sram-c1", 332 "allwinner,sun4i-a10-sram-c1"; 333 reg = <0x000000 0x40000>; 334 }; 335 }; 336 }; 337 338 dma: dma-controller@1c02000 { 339 compatible = "allwinner,sun50i-a64-dma"; 340 reg = <0x01c02000 0x1000>; 341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&ccu CLK_BUS_DMA>; 343 dma-channels = <8>; 344 dma-requests = <27>; 345 resets = <&ccu RST_BUS_DMA>; 346 #dma-cells = <1>; 347 }; 348 349 tcon0: lcd-controller@1c0c000 { 350 compatible = "allwinner,sun50i-a64-tcon-lcd", 351 "allwinner,sun8i-a83t-tcon-lcd"; 352 reg = <0x01c0c000 0x1000>; 353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 355 clock-names = "ahb", "tcon-ch0"; 356 clock-output-names = "tcon-pixel-clock"; 357 #clock-cells = <0>; 358 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 359 reset-names = "lcd", "lvds"; 360 361 ports { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 tcon0_in: port@0 { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0>; 369 370 tcon0_in_mixer0: endpoint@0 { 371 reg = <0>; 372 remote-endpoint = <&mixer0_out_tcon0>; 373 }; 374 375 tcon0_in_mixer1: endpoint@1 { 376 reg = <1>; 377 remote-endpoint = <&mixer1_out_tcon0>; 378 }; 379 }; 380 381 tcon0_out: port@1 { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 reg = <1>; 385 }; 386 }; 387 }; 388 389 tcon1: lcd-controller@1c0d000 { 390 compatible = "allwinner,sun50i-a64-tcon-tv", 391 "allwinner,sun8i-a83t-tcon-tv"; 392 reg = <0x01c0d000 0x1000>; 393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 395 clock-names = "ahb", "tcon-ch1"; 396 resets = <&ccu RST_BUS_TCON1>; 397 reset-names = "lcd"; 398 399 ports { 400 #address-cells = <1>; 401 #size-cells = <0>; 402 403 tcon1_in: port@0 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0>; 407 408 tcon1_in_mixer0: endpoint@0 { 409 reg = <0>; 410 remote-endpoint = <&mixer0_out_tcon1>; 411 }; 412 413 tcon1_in_mixer1: endpoint@1 { 414 reg = <1>; 415 remote-endpoint = <&mixer1_out_tcon1>; 416 }; 417 }; 418 419 tcon1_out: port@1 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <1>; 423 424 tcon1_out_hdmi: endpoint@1 { 425 reg = <1>; 426 remote-endpoint = <&hdmi_in_tcon1>; 427 }; 428 }; 429 }; 430 }; 431 432 video-codec@1c0e000 { 433 compatible = "allwinner,sun50i-a64-video-engine"; 434 reg = <0x01c0e000 0x1000>; 435 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 436 <&ccu CLK_DRAM_VE>; 437 clock-names = "ahb", "mod", "ram"; 438 resets = <&ccu RST_BUS_VE>; 439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 440 allwinner,sram = <&ve_sram 1>; 441 }; 442 443 mmc0: mmc@1c0f000 { 444 compatible = "allwinner,sun50i-a64-mmc"; 445 reg = <0x01c0f000 0x1000>; 446 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 447 clock-names = "ahb", "mmc"; 448 resets = <&ccu RST_BUS_MMC0>; 449 reset-names = "ahb"; 450 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 451 max-frequency = <150000000>; 452 status = "disabled"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 }; 456 457 mmc1: mmc@1c10000 { 458 compatible = "allwinner,sun50i-a64-mmc"; 459 reg = <0x01c10000 0x1000>; 460 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 461 clock-names = "ahb", "mmc"; 462 resets = <&ccu RST_BUS_MMC1>; 463 reset-names = "ahb"; 464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 465 max-frequency = <150000000>; 466 status = "disabled"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 }; 470 471 mmc2: mmc@1c11000 { 472 compatible = "allwinner,sun50i-a64-emmc"; 473 reg = <0x01c11000 0x1000>; 474 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 475 clock-names = "ahb", "mmc"; 476 resets = <&ccu RST_BUS_MMC2>; 477 reset-names = "ahb"; 478 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 479 max-frequency = <200000000>; 480 status = "disabled"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 }; 484 485 sid: eeprom@1c14000 { 486 compatible = "allwinner,sun50i-a64-sid"; 487 reg = <0x1c14000 0x400>; 488 }; 489 490 crypto: crypto@1c15000 { 491 compatible = "allwinner,sun50i-a64-crypto"; 492 reg = <0x01c15000 0x1000>; 493 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 495 clock-names = "bus", "mod"; 496 resets = <&ccu RST_BUS_CE>; 497 }; 498 499 usb_otg: usb@1c19000 { 500 compatible = "allwinner,sun8i-a33-musb"; 501 reg = <0x01c19000 0x0400>; 502 clocks = <&ccu CLK_BUS_OTG>; 503 resets = <&ccu RST_BUS_OTG>; 504 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "mc"; 506 phys = <&usbphy 0>; 507 phy-names = "usb"; 508 extcon = <&usbphy 0>; 509 dr_mode = "otg"; 510 status = "disabled"; 511 }; 512 513 usbphy: phy@1c19400 { 514 compatible = "allwinner,sun50i-a64-usb-phy"; 515 reg = <0x01c19400 0x14>, 516 <0x01c1a800 0x4>, 517 <0x01c1b800 0x4>; 518 reg-names = "phy_ctrl", 519 "pmu0", 520 "pmu1"; 521 clocks = <&ccu CLK_USB_PHY0>, 522 <&ccu CLK_USB_PHY1>; 523 clock-names = "usb0_phy", 524 "usb1_phy"; 525 resets = <&ccu RST_USB_PHY0>, 526 <&ccu RST_USB_PHY1>; 527 reset-names = "usb0_reset", 528 "usb1_reset"; 529 status = "disabled"; 530 #phy-cells = <1>; 531 }; 532 533 ehci0: usb@1c1a000 { 534 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 535 reg = <0x01c1a000 0x100>; 536 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&ccu CLK_BUS_OHCI0>, 538 <&ccu CLK_BUS_EHCI0>, 539 <&ccu CLK_USB_OHCI0>; 540 resets = <&ccu RST_BUS_OHCI0>, 541 <&ccu RST_BUS_EHCI0>; 542 status = "disabled"; 543 }; 544 545 ohci0: usb@1c1a400 { 546 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 547 reg = <0x01c1a400 0x100>; 548 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&ccu CLK_BUS_OHCI0>, 550 <&ccu CLK_USB_OHCI0>; 551 resets = <&ccu RST_BUS_OHCI0>; 552 status = "disabled"; 553 }; 554 555 ehci1: usb@1c1b000 { 556 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 557 reg = <0x01c1b000 0x100>; 558 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&ccu CLK_BUS_OHCI1>, 560 <&ccu CLK_BUS_EHCI1>, 561 <&ccu CLK_USB_OHCI1>; 562 resets = <&ccu RST_BUS_OHCI1>, 563 <&ccu RST_BUS_EHCI1>; 564 phys = <&usbphy 1>; 565 status = "disabled"; 566 }; 567 568 ohci1: usb@1c1b400 { 569 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 570 reg = <0x01c1b400 0x100>; 571 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&ccu CLK_BUS_OHCI1>, 573 <&ccu CLK_USB_OHCI1>; 574 resets = <&ccu RST_BUS_OHCI1>; 575 phys = <&usbphy 1>; 576 status = "disabled"; 577 }; 578 579 ccu: clock@1c20000 { 580 compatible = "allwinner,sun50i-a64-ccu"; 581 reg = <0x01c20000 0x400>; 582 clocks = <&osc24M>, <&rtc 0>; 583 clock-names = "hosc", "losc"; 584 #clock-cells = <1>; 585 #reset-cells = <1>; 586 }; 587 588 pio: pinctrl@1c20800 { 589 compatible = "allwinner,sun50i-a64-pinctrl"; 590 reg = <0x01c20800 0x400>; 591 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 595 clock-names = "apb", "hosc", "losc"; 596 gpio-controller; 597 #gpio-cells = <3>; 598 interrupt-controller; 599 #interrupt-cells = <3>; 600 601 csi_pins: csi-pins { 602 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 603 "PE7", "PE8", "PE9", "PE10", "PE11"; 604 function = "csi"; 605 }; 606 607 /omit-if-no-ref/ 608 csi_mclk_pin: csi-mclk-pin { 609 pins = "PE1"; 610 function = "csi"; 611 }; 612 613 i2c0_pins: i2c0-pins { 614 pins = "PH0", "PH1"; 615 function = "i2c0"; 616 }; 617 618 i2c1_pins: i2c1-pins { 619 pins = "PH2", "PH3"; 620 function = "i2c1"; 621 }; 622 623 /omit-if-no-ref/ 624 lcd_rgb666_pins: lcd-rgb666-pins { 625 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 626 "PD5", "PD6", "PD7", "PD8", "PD9", 627 "PD10", "PD11", "PD12", "PD13", 628 "PD14", "PD15", "PD16", "PD17", 629 "PD18", "PD19", "PD20", "PD21"; 630 function = "lcd0"; 631 }; 632 633 mmc0_pins: mmc0-pins { 634 pins = "PF0", "PF1", "PF2", "PF3", 635 "PF4", "PF5"; 636 function = "mmc0"; 637 drive-strength = <30>; 638 bias-pull-up; 639 }; 640 641 mmc1_pins: mmc1-pins { 642 pins = "PG0", "PG1", "PG2", "PG3", 643 "PG4", "PG5"; 644 function = "mmc1"; 645 drive-strength = <30>; 646 bias-pull-up; 647 }; 648 649 mmc2_pins: mmc2-pins { 650 pins = "PC5", "PC6", "PC8", "PC9", 651 "PC10","PC11", "PC12", "PC13", 652 "PC14", "PC15", "PC16"; 653 function = "mmc2"; 654 drive-strength = <30>; 655 bias-pull-up; 656 }; 657 658 mmc2_ds_pin: mmc2-ds-pin { 659 pins = "PC1"; 660 function = "mmc2"; 661 drive-strength = <30>; 662 bias-pull-up; 663 }; 664 665 pwm_pin: pwm-pin { 666 pins = "PD22"; 667 function = "pwm"; 668 }; 669 670 rmii_pins: rmii-pins { 671 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 672 "PD18", "PD19", "PD20", "PD22", "PD23"; 673 function = "emac"; 674 drive-strength = <40>; 675 }; 676 677 rgmii_pins: rgmii-pins { 678 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 679 "PD13", "PD15", "PD16", "PD17", "PD18", 680 "PD19", "PD20", "PD21", "PD22", "PD23"; 681 function = "emac"; 682 drive-strength = <40>; 683 }; 684 685 spdif_tx_pin: spdif-tx-pin { 686 pins = "PH8"; 687 function = "spdif"; 688 }; 689 690 spi0_pins: spi0-pins { 691 pins = "PC0", "PC1", "PC2", "PC3"; 692 function = "spi0"; 693 }; 694 695 spi1_pins: spi1-pins { 696 pins = "PD0", "PD1", "PD2", "PD3"; 697 function = "spi1"; 698 }; 699 700 uart0_pb_pins: uart0-pb-pins { 701 pins = "PB8", "PB9"; 702 function = "uart0"; 703 }; 704 705 uart1_pins: uart1-pins { 706 pins = "PG6", "PG7"; 707 function = "uart1"; 708 }; 709 710 uart1_rts_cts_pins: uart1-rts-cts-pins { 711 pins = "PG8", "PG9"; 712 function = "uart1"; 713 }; 714 715 uart2_pins: uart2-pins { 716 pins = "PB0", "PB1"; 717 function = "uart2"; 718 }; 719 720 uart3_pins: uart3-pins { 721 pins = "PD0", "PD1"; 722 function = "uart3"; 723 }; 724 725 uart4_pins: uart4-pins { 726 pins = "PD2", "PD3"; 727 function = "uart4"; 728 }; 729 730 uart4_rts_cts_pins: uart4-rts-cts-pins { 731 pins = "PD4", "PD5"; 732 function = "uart4"; 733 }; 734 }; 735 736 spdif: spdif@1c21000 { 737 #sound-dai-cells = <0>; 738 compatible = "allwinner,sun50i-a64-spdif", 739 "allwinner,sun8i-h3-spdif"; 740 reg = <0x01c21000 0x400>; 741 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 743 resets = <&ccu RST_BUS_SPDIF>; 744 clock-names = "apb", "spdif"; 745 dmas = <&dma 2>; 746 dma-names = "tx"; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&spdif_tx_pin>; 749 status = "disabled"; 750 }; 751 752 lradc: lradc@1c21800 { 753 compatible = "allwinner,sun50i-a64-lradc", 754 "allwinner,sun8i-a83t-r-lradc"; 755 reg = <0x01c21800 0x400>; 756 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 757 status = "disabled"; 758 }; 759 760 i2s0: i2s@1c22000 { 761 #sound-dai-cells = <0>; 762 compatible = "allwinner,sun50i-a64-i2s", 763 "allwinner,sun8i-h3-i2s"; 764 reg = <0x01c22000 0x400>; 765 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 767 clock-names = "apb", "mod"; 768 resets = <&ccu RST_BUS_I2S0>; 769 dma-names = "rx", "tx"; 770 dmas = <&dma 3>, <&dma 3>; 771 status = "disabled"; 772 }; 773 774 i2s1: i2s@1c22400 { 775 #sound-dai-cells = <0>; 776 compatible = "allwinner,sun50i-a64-i2s", 777 "allwinner,sun8i-h3-i2s"; 778 reg = <0x01c22400 0x400>; 779 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 781 clock-names = "apb", "mod"; 782 resets = <&ccu RST_BUS_I2S1>; 783 dma-names = "rx", "tx"; 784 dmas = <&dma 4>, <&dma 4>; 785 status = "disabled"; 786 }; 787 788 dai: dai@1c22c00 { 789 #sound-dai-cells = <0>; 790 compatible = "allwinner,sun50i-a64-codec-i2s"; 791 reg = <0x01c22c00 0x200>; 792 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 794 clock-names = "apb", "mod"; 795 resets = <&ccu RST_BUS_CODEC>; 796 dmas = <&dma 15>, <&dma 15>; 797 dma-names = "rx", "tx"; 798 status = "disabled"; 799 }; 800 801 codec: codec@1c22e00 { 802 #sound-dai-cells = <0>; 803 compatible = "allwinner,sun8i-a33-codec"; 804 reg = <0x01c22e00 0x600>; 805 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 807 clock-names = "bus", "mod"; 808 status = "disabled"; 809 }; 810 811 uart0: serial@1c28000 { 812 compatible = "snps,dw-apb-uart"; 813 reg = <0x01c28000 0x400>; 814 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 815 reg-shift = <2>; 816 reg-io-width = <4>; 817 clocks = <&ccu CLK_BUS_UART0>; 818 resets = <&ccu RST_BUS_UART0>; 819 status = "disabled"; 820 }; 821 822 uart1: serial@1c28400 { 823 compatible = "snps,dw-apb-uart"; 824 reg = <0x01c28400 0x400>; 825 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 826 reg-shift = <2>; 827 reg-io-width = <4>; 828 clocks = <&ccu CLK_BUS_UART1>; 829 resets = <&ccu RST_BUS_UART1>; 830 status = "disabled"; 831 }; 832 833 uart2: serial@1c28800 { 834 compatible = "snps,dw-apb-uart"; 835 reg = <0x01c28800 0x400>; 836 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 837 reg-shift = <2>; 838 reg-io-width = <4>; 839 clocks = <&ccu CLK_BUS_UART2>; 840 resets = <&ccu RST_BUS_UART2>; 841 status = "disabled"; 842 }; 843 844 uart3: serial@1c28c00 { 845 compatible = "snps,dw-apb-uart"; 846 reg = <0x01c28c00 0x400>; 847 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 848 reg-shift = <2>; 849 reg-io-width = <4>; 850 clocks = <&ccu CLK_BUS_UART3>; 851 resets = <&ccu RST_BUS_UART3>; 852 status = "disabled"; 853 }; 854 855 uart4: serial@1c29000 { 856 compatible = "snps,dw-apb-uart"; 857 reg = <0x01c29000 0x400>; 858 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 859 reg-shift = <2>; 860 reg-io-width = <4>; 861 clocks = <&ccu CLK_BUS_UART4>; 862 resets = <&ccu RST_BUS_UART4>; 863 status = "disabled"; 864 }; 865 866 i2c0: i2c@1c2ac00 { 867 compatible = "allwinner,sun6i-a31-i2c"; 868 reg = <0x01c2ac00 0x400>; 869 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&ccu CLK_BUS_I2C0>; 871 resets = <&ccu RST_BUS_I2C0>; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&i2c0_pins>; 874 status = "disabled"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 }; 878 879 i2c1: i2c@1c2b000 { 880 compatible = "allwinner,sun6i-a31-i2c"; 881 reg = <0x01c2b000 0x400>; 882 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&ccu CLK_BUS_I2C1>; 884 resets = <&ccu RST_BUS_I2C1>; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&i2c1_pins>; 887 status = "disabled"; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 }; 891 892 i2c2: i2c@1c2b400 { 893 compatible = "allwinner,sun6i-a31-i2c"; 894 reg = <0x01c2b400 0x400>; 895 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&ccu CLK_BUS_I2C2>; 897 resets = <&ccu RST_BUS_I2C2>; 898 status = "disabled"; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 }; 902 903 904 spi0: spi@1c68000 { 905 compatible = "allwinner,sun8i-h3-spi"; 906 reg = <0x01c68000 0x1000>; 907 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 909 clock-names = "ahb", "mod"; 910 dmas = <&dma 23>, <&dma 23>; 911 dma-names = "rx", "tx"; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&spi0_pins>; 914 resets = <&ccu RST_BUS_SPI0>; 915 status = "disabled"; 916 num-cs = <1>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 }; 920 921 spi1: spi@1c69000 { 922 compatible = "allwinner,sun8i-h3-spi"; 923 reg = <0x01c69000 0x1000>; 924 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 926 clock-names = "ahb", "mod"; 927 dmas = <&dma 24>, <&dma 24>; 928 dma-names = "rx", "tx"; 929 pinctrl-names = "default"; 930 pinctrl-0 = <&spi1_pins>; 931 resets = <&ccu RST_BUS_SPI1>; 932 status = "disabled"; 933 num-cs = <1>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 }; 937 938 emac: ethernet@1c30000 { 939 compatible = "allwinner,sun50i-a64-emac"; 940 syscon = <&syscon>; 941 reg = <0x01c30000 0x10000>; 942 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "macirq"; 944 resets = <&ccu RST_BUS_EMAC>; 945 reset-names = "stmmaceth"; 946 clocks = <&ccu CLK_BUS_EMAC>; 947 clock-names = "stmmaceth"; 948 status = "disabled"; 949 950 mdio: mdio { 951 compatible = "snps,dwmac-mdio"; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 }; 955 }; 956 957 mali: gpu@1c40000 { 958 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 959 reg = <0x01c40000 0x10000>; 960 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 967 interrupt-names = "gp", 968 "gpmmu", 969 "pp0", 970 "ppmmu0", 971 "pp1", 972 "ppmmu1", 973 "pmu"; 974 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 975 clock-names = "bus", "core"; 976 resets = <&ccu RST_BUS_GPU>; 977 }; 978 979 gic: interrupt-controller@1c81000 { 980 compatible = "arm,gic-400"; 981 reg = <0x01c81000 0x1000>, 982 <0x01c82000 0x2000>, 983 <0x01c84000 0x2000>, 984 <0x01c86000 0x2000>; 985 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 986 interrupt-controller; 987 #interrupt-cells = <3>; 988 }; 989 990 pwm: pwm@1c21400 { 991 compatible = "allwinner,sun50i-a64-pwm", 992 "allwinner,sun5i-a13-pwm"; 993 reg = <0x01c21400 0x400>; 994 clocks = <&osc24M>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&pwm_pin>; 997 #pwm-cells = <3>; 998 status = "disabled"; 999 }; 1000 1001 csi: csi@1cb0000 { 1002 compatible = "allwinner,sun50i-a64-csi"; 1003 reg = <0x01cb0000 0x1000>; 1004 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&ccu CLK_BUS_CSI>, 1006 <&ccu CLK_CSI_SCLK>, 1007 <&ccu CLK_DRAM_CSI>; 1008 clock-names = "bus", "mod", "ram"; 1009 resets = <&ccu RST_BUS_CSI>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&csi_pins>; 1012 status = "disabled"; 1013 }; 1014 1015 hdmi: hdmi@1ee0000 { 1016 compatible = "allwinner,sun50i-a64-dw-hdmi", 1017 "allwinner,sun8i-a83t-dw-hdmi"; 1018 reg = <0x01ee0000 0x10000>; 1019 reg-io-width = <1>; 1020 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1022 <&ccu CLK_HDMI>; 1023 clock-names = "iahb", "isfr", "tmds"; 1024 resets = <&ccu RST_BUS_HDMI1>; 1025 reset-names = "ctrl"; 1026 phys = <&hdmi_phy>; 1027 phy-names = "phy"; 1028 status = "disabled"; 1029 1030 ports { 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 1034 hdmi_in: port@0 { 1035 reg = <0>; 1036 1037 hdmi_in_tcon1: endpoint { 1038 remote-endpoint = <&tcon1_out_hdmi>; 1039 }; 1040 }; 1041 1042 hdmi_out: port@1 { 1043 reg = <1>; 1044 }; 1045 }; 1046 }; 1047 1048 hdmi_phy: hdmi-phy@1ef0000 { 1049 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1050 reg = <0x01ef0000 0x10000>; 1051 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1052 <&ccu 7>; 1053 clock-names = "bus", "mod", "pll-0"; 1054 resets = <&ccu RST_BUS_HDMI0>; 1055 reset-names = "phy"; 1056 #phy-cells = <0>; 1057 }; 1058 1059 rtc: rtc@1f00000 { 1060 compatible = "allwinner,sun50i-a64-rtc", 1061 "allwinner,sun8i-h3-rtc"; 1062 reg = <0x01f00000 0x400>; 1063 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1065 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1066 clocks = <&osc32k>; 1067 #clock-cells = <1>; 1068 }; 1069 1070 r_intc: interrupt-controller@1f00c00 { 1071 compatible = "allwinner,sun50i-a64-r-intc", 1072 "allwinner,sun6i-a31-r-intc"; 1073 interrupt-controller; 1074 #interrupt-cells = <2>; 1075 reg = <0x01f00c00 0x400>; 1076 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1077 }; 1078 1079 r_ccu: clock@1f01400 { 1080 compatible = "allwinner,sun50i-a64-r-ccu"; 1081 reg = <0x01f01400 0x100>; 1082 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1083 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1084 #clock-cells = <1>; 1085 #reset-cells = <1>; 1086 }; 1087 1088 codec_analog: codec-analog@1f015c0 { 1089 compatible = "allwinner,sun50i-a64-codec-analog"; 1090 reg = <0x01f015c0 0x4>; 1091 status = "disabled"; 1092 }; 1093 1094 r_i2c: i2c@1f02400 { 1095 compatible = "allwinner,sun50i-a64-i2c", 1096 "allwinner,sun6i-a31-i2c"; 1097 reg = <0x01f02400 0x400>; 1098 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&r_ccu CLK_APB0_I2C>; 1100 resets = <&r_ccu RST_APB0_I2C>; 1101 status = "disabled"; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 }; 1105 1106 r_ir: ir@1f02000 { 1107 compatible = "allwinner,sun50i-a64-ir", 1108 "allwinner,sun6i-a31-ir"; 1109 reg = <0x01f02000 0x400>; 1110 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1111 clock-names = "apb", "ir"; 1112 resets = <&r_ccu RST_APB0_IR>; 1113 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&r_ir_rx_pin>; 1116 status = "disabled"; 1117 }; 1118 1119 r_pwm: pwm@1f03800 { 1120 compatible = "allwinner,sun50i-a64-pwm", 1121 "allwinner,sun5i-a13-pwm"; 1122 reg = <0x01f03800 0x400>; 1123 clocks = <&osc24M>; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&r_pwm_pin>; 1126 #pwm-cells = <3>; 1127 status = "disabled"; 1128 }; 1129 1130 r_pio: pinctrl@1f02c00 { 1131 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1132 reg = <0x01f02c00 0x400>; 1133 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1135 clock-names = "apb", "hosc", "losc"; 1136 gpio-controller; 1137 #gpio-cells = <3>; 1138 interrupt-controller; 1139 #interrupt-cells = <3>; 1140 1141 r_i2c_pl89_pins: r-i2c-pl89-pins { 1142 pins = "PL8", "PL9"; 1143 function = "s_i2c"; 1144 }; 1145 1146 r_ir_rx_pin: r-ir-rx-pin { 1147 pins = "PL11"; 1148 function = "s_cir_rx"; 1149 }; 1150 1151 r_pwm_pin: r-pwm-pin { 1152 pins = "PL10"; 1153 function = "s_pwm"; 1154 }; 1155 1156 r_rsb_pins: r-rsb-pins { 1157 pins = "PL0", "PL1"; 1158 function = "s_rsb"; 1159 }; 1160 }; 1161 1162 r_rsb: rsb@1f03400 { 1163 compatible = "allwinner,sun8i-a23-rsb"; 1164 reg = <0x01f03400 0x400>; 1165 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&r_ccu 6>; 1167 clock-frequency = <3000000>; 1168 resets = <&r_ccu 2>; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&r_rsb_pins>; 1171 status = "disabled"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 }; 1175 1176 wdt0: watchdog@1c20ca0 { 1177 compatible = "allwinner,sun50i-a64-wdt", 1178 "allwinner,sun6i-a31-wdt"; 1179 reg = <0x01c20ca0 0x20>; 1180 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&osc24M>; 1182 }; 1183 }; 1184}; 1185