1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun50i-a64-ccu.h> 48 49/ { 50 interrupt-parent = <&gic>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 device_type = "cpu"; 61 reg = <0>; 62 enable-method = "psci"; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 device_type = "cpu"; 68 reg = <1>; 69 enable-method = "psci"; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <2>; 76 enable-method = "psci"; 77 }; 78 79 cpu3: cpu@3 { 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 device_type = "cpu"; 82 reg = <3>; 83 enable-method = "psci"; 84 }; 85 }; 86 87 osc24M: osc24M_clk { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc24M"; 92 }; 93 94 osc32k: osc32k_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32768>; 98 clock-output-names = "osc32k"; 99 }; 100 101 psci { 102 compatible = "arm,psci-0.2"; 103 method = "smc"; 104 }; 105 106 timer { 107 compatible = "arm,armv8-timer"; 108 interrupts = <GIC_PPI 13 109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 110 <GIC_PPI 14 111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 112 <GIC_PPI 11 113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 114 <GIC_PPI 10 115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges; 123 124 mmc0: mmc@1c0f000 { 125 compatible = "allwinner,sun50i-a64-mmc"; 126 reg = <0x01c0f000 0x1000>; 127 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 128 clock-names = "ahb", "mmc"; 129 resets = <&ccu RST_BUS_MMC0>; 130 reset-names = "ahb"; 131 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 132 max-frequency = <150000000>; 133 status = "disabled"; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 138 mmc1: mmc@1c10000 { 139 compatible = "allwinner,sun50i-a64-mmc"; 140 reg = <0x01c10000 0x1000>; 141 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 142 clock-names = "ahb", "mmc"; 143 resets = <&ccu RST_BUS_MMC1>; 144 reset-names = "ahb"; 145 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 146 max-frequency = <150000000>; 147 status = "disabled"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 }; 151 152 mmc2: mmc@1c11000 { 153 compatible = "allwinner,sun50i-a64-emmc"; 154 reg = <0x01c11000 0x1000>; 155 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 156 clock-names = "ahb", "mmc"; 157 resets = <&ccu RST_BUS_MMC2>; 158 reset-names = "ahb"; 159 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 160 max-frequency = <200000000>; 161 status = "disabled"; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 }; 165 166 usb_otg: usb@01c19000 { 167 compatible = "allwinner,sun8i-a33-musb"; 168 reg = <0x01c19000 0x0400>; 169 clocks = <&ccu CLK_BUS_OTG>; 170 resets = <&ccu RST_BUS_OTG>; 171 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-names = "mc"; 173 phys = <&usbphy 0>; 174 phy-names = "usb"; 175 extcon = <&usbphy 0>; 176 status = "disabled"; 177 }; 178 179 usbphy: phy@01c19400 { 180 compatible = "allwinner,sun50i-a64-usb-phy"; 181 reg = <0x01c19400 0x14>, 182 <0x01c1a800 0x4>, 183 <0x01c1b800 0x4>; 184 reg-names = "phy_ctrl", 185 "pmu0", 186 "pmu1"; 187 clocks = <&ccu CLK_USB_PHY0>, 188 <&ccu CLK_USB_PHY1>; 189 clock-names = "usb0_phy", 190 "usb1_phy"; 191 resets = <&ccu RST_USB_PHY0>, 192 <&ccu RST_USB_PHY1>; 193 reset-names = "usb0_reset", 194 "usb1_reset"; 195 status = "disabled"; 196 #phy-cells = <1>; 197 }; 198 199 ehci1: usb@01c1b000 { 200 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 201 reg = <0x01c1b000 0x100>; 202 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&ccu CLK_BUS_OHCI1>, 204 <&ccu CLK_BUS_EHCI1>, 205 <&ccu CLK_USB_OHCI1>; 206 resets = <&ccu RST_BUS_OHCI1>, 207 <&ccu RST_BUS_EHCI1>; 208 phys = <&usbphy 1>; 209 phy-names = "usb"; 210 status = "disabled"; 211 }; 212 213 ohci1: usb@01c1b400 { 214 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 215 reg = <0x01c1b400 0x100>; 216 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&ccu CLK_BUS_OHCI1>, 218 <&ccu CLK_USB_OHCI1>; 219 resets = <&ccu RST_BUS_OHCI1>; 220 phys = <&usbphy 1>; 221 phy-names = "usb"; 222 status = "disabled"; 223 }; 224 225 ccu: clock@01c20000 { 226 compatible = "allwinner,sun50i-a64-ccu"; 227 reg = <0x01c20000 0x400>; 228 clocks = <&osc24M>, <&osc32k>; 229 clock-names = "hosc", "losc"; 230 #clock-cells = <1>; 231 #reset-cells = <1>; 232 }; 233 234 pio: pinctrl@1c20800 { 235 compatible = "allwinner,sun50i-a64-pinctrl"; 236 reg = <0x01c20800 0x400>; 237 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&ccu 58>; 241 gpio-controller; 242 #gpio-cells = <3>; 243 interrupt-controller; 244 #interrupt-cells = <3>; 245 246 i2c1_pins: i2c1_pins { 247 pins = "PH2", "PH3"; 248 function = "i2c1"; 249 }; 250 251 mmc0_pins: mmc0-pins { 252 pins = "PF0", "PF1", "PF2", "PF3", 253 "PF4", "PF5"; 254 function = "mmc0"; 255 drive-strength = <30>; 256 bias-pull-up; 257 }; 258 259 mmc1_pins: mmc1-pins { 260 pins = "PG0", "PG1", "PG2", "PG3", 261 "PG4", "PG5"; 262 function = "mmc1"; 263 drive-strength = <30>; 264 bias-pull-up; 265 }; 266 267 mmc2_pins: mmc2-pins { 268 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 269 "PC10","PC11", "PC12", "PC13", 270 "PC14", "PC15", "PC16"; 271 function = "mmc2"; 272 drive-strength = <30>; 273 bias-pull-up; 274 }; 275 276 uart0_pins_a: uart0@0 { 277 pins = "PB8", "PB9"; 278 function = "uart0"; 279 }; 280 281 uart1_pins: uart1_pins { 282 pins = "PG6", "PG7"; 283 function = "uart1"; 284 }; 285 286 uart1_rts_cts_pins: uart1_rts_cts_pins { 287 pins = "PG8", "PG9"; 288 function = "uart1"; 289 }; 290 }; 291 292 uart0: serial@1c28000 { 293 compatible = "snps,dw-apb-uart"; 294 reg = <0x01c28000 0x400>; 295 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 clocks = <&ccu 67>; 299 resets = <&ccu 46>; 300 status = "disabled"; 301 }; 302 303 uart1: serial@1c28400 { 304 compatible = "snps,dw-apb-uart"; 305 reg = <0x01c28400 0x400>; 306 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 307 reg-shift = <2>; 308 reg-io-width = <4>; 309 clocks = <&ccu 68>; 310 resets = <&ccu 47>; 311 status = "disabled"; 312 }; 313 314 uart2: serial@1c28800 { 315 compatible = "snps,dw-apb-uart"; 316 reg = <0x01c28800 0x400>; 317 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 318 reg-shift = <2>; 319 reg-io-width = <4>; 320 clocks = <&ccu 69>; 321 resets = <&ccu 48>; 322 status = "disabled"; 323 }; 324 325 uart3: serial@1c28c00 { 326 compatible = "snps,dw-apb-uart"; 327 reg = <0x01c28c00 0x400>; 328 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 329 reg-shift = <2>; 330 reg-io-width = <4>; 331 clocks = <&ccu 70>; 332 resets = <&ccu 49>; 333 status = "disabled"; 334 }; 335 336 uart4: serial@1c29000 { 337 compatible = "snps,dw-apb-uart"; 338 reg = <0x01c29000 0x400>; 339 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 340 reg-shift = <2>; 341 reg-io-width = <4>; 342 clocks = <&ccu 71>; 343 resets = <&ccu 50>; 344 status = "disabled"; 345 }; 346 347 i2c0: i2c@1c2ac00 { 348 compatible = "allwinner,sun6i-a31-i2c"; 349 reg = <0x01c2ac00 0x400>; 350 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&ccu 63>; 352 resets = <&ccu 42>; 353 status = "disabled"; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 }; 357 358 i2c1: i2c@1c2b000 { 359 compatible = "allwinner,sun6i-a31-i2c"; 360 reg = <0x01c2b000 0x400>; 361 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&ccu 64>; 363 resets = <&ccu 43>; 364 status = "disabled"; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 }; 368 369 i2c2: i2c@1c2b400 { 370 compatible = "allwinner,sun6i-a31-i2c"; 371 reg = <0x01c2b400 0x400>; 372 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&ccu 65>; 374 resets = <&ccu 44>; 375 status = "disabled"; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 }; 379 380 gic: interrupt-controller@1c81000 { 381 compatible = "arm,gic-400"; 382 reg = <0x01c81000 0x1000>, 383 <0x01c82000 0x2000>, 384 <0x01c84000 0x2000>, 385 <0x01c86000 0x2000>; 386 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 387 interrupt-controller; 388 #interrupt-cells = <3>; 389 }; 390 391 rtc: rtc@1f00000 { 392 compatible = "allwinner,sun6i-a31-rtc"; 393 reg = <0x01f00000 0x54>; 394 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 396 }; 397 }; 398}; 399