1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2016 ARM Ltd.
3// based on the Allwinner H3 dtsi:
4//    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5
6#include <dt-bindings/clock/sun50i-a64-ccu.h>
7#include <dt-bindings/clock/sun8i-de2.h>
8#include <dt-bindings/clock/sun8i-r-ccu.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/reset/sun50i-a64-ccu.h>
11#include <dt-bindings/reset/sun8i-de2.h>
12#include <dt-bindings/reset/sun8i-r-ccu.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	chosen {
21		#address-cells = <1>;
22		#size-cells = <1>;
23		ranges;
24
25		simplefb_lcd: framebuffer-lcd {
26			compatible = "allwinner,simple-framebuffer",
27				     "simple-framebuffer";
28			allwinner,pipeline = "mixer0-lcd0";
29			clocks = <&ccu CLK_TCON0>,
30				 <&display_clocks CLK_MIXER0>;
31			status = "disabled";
32		};
33
34		simplefb_hdmi: framebuffer-hdmi {
35			compatible = "allwinner,simple-framebuffer",
36				     "simple-framebuffer";
37			allwinner,pipeline = "mixer1-lcd1-hdmi";
38			clocks = <&display_clocks CLK_MIXER1>,
39				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
40			status = "disabled";
41		};
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		cpu0: cpu@0 {
49			compatible = "arm,cortex-a53";
50			device_type = "cpu";
51			reg = <0>;
52			enable-method = "psci";
53			next-level-cache = <&L2>;
54			clocks = <&ccu CLK_CPUX>;
55			clock-names = "cpu";
56			#cooling-cells = <2>;
57		};
58
59		cpu1: cpu@1 {
60			compatible = "arm,cortex-a53";
61			device_type = "cpu";
62			reg = <1>;
63			enable-method = "psci";
64			next-level-cache = <&L2>;
65			clocks = <&ccu CLK_CPUX>;
66			clock-names = "cpu";
67			#cooling-cells = <2>;
68		};
69
70		cpu2: cpu@2 {
71			compatible = "arm,cortex-a53";
72			device_type = "cpu";
73			reg = <2>;
74			enable-method = "psci";
75			next-level-cache = <&L2>;
76			clocks = <&ccu CLK_CPUX>;
77			clock-names = "cpu";
78			#cooling-cells = <2>;
79		};
80
81		cpu3: cpu@3 {
82			compatible = "arm,cortex-a53";
83			device_type = "cpu";
84			reg = <3>;
85			enable-method = "psci";
86			next-level-cache = <&L2>;
87			clocks = <&ccu CLK_CPUX>;
88			clock-names = "cpu";
89			#cooling-cells = <2>;
90		};
91
92		L2: l2-cache {
93			compatible = "cache";
94			cache-level = <2>;
95		};
96	};
97
98	de: display-engine {
99		compatible = "allwinner,sun50i-a64-display-engine";
100		allwinner,pipelines = <&mixer0>,
101				      <&mixer1>;
102		status = "disabled";
103	};
104
105	osc24M: osc24M_clk {
106		#clock-cells = <0>;
107		compatible = "fixed-clock";
108		clock-frequency = <24000000>;
109		clock-output-names = "osc24M";
110	};
111
112	osc32k: osc32k_clk {
113		#clock-cells = <0>;
114		compatible = "fixed-clock";
115		clock-frequency = <32768>;
116		clock-output-names = "ext-osc32k";
117	};
118
119	pmu {
120		compatible = "arm,cortex-a53-pmu";
121		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
122			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
123			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
124			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
125		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
126	};
127
128	psci {
129		compatible = "arm,psci-0.2";
130		method = "smc";
131	};
132
133	sound: sound {
134		compatible = "simple-audio-card";
135		simple-audio-card,name = "sun50i-a64-audio";
136		simple-audio-card,format = "i2s";
137		simple-audio-card,frame-master = <&cpudai>;
138		simple-audio-card,bitclock-master = <&cpudai>;
139		simple-audio-card,mclk-fs = <128>;
140		simple-audio-card,aux-devs = <&codec_analog>;
141		simple-audio-card,routing =
142				"Left DAC", "DACL",
143				"Right DAC", "DACR",
144				"ADCL", "Left ADC",
145				"ADCR", "Right ADC";
146		status = "disabled";
147
148		cpudai: simple-audio-card,cpu {
149			sound-dai = <&dai>;
150		};
151
152		link_codec: simple-audio-card,codec {
153			sound-dai = <&codec 0>;
154		};
155	};
156
157	timer {
158		compatible = "arm,armv8-timer";
159		allwinner,erratum-unknown1;
160		arm,no-tick-in-suspend;
161		interrupts = <GIC_PPI 13
162			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
163			     <GIC_PPI 14
164			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
165			     <GIC_PPI 11
166			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
167			     <GIC_PPI 10
168			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
169	};
170
171	thermal-zones {
172		cpu_thermal: cpu0-thermal {
173			/* milliseconds */
174			polling-delay-passive = <0>;
175			polling-delay = <0>;
176			thermal-sensors = <&ths 0>;
177
178			cooling-maps {
179				map0 {
180					trip = <&cpu_alert0>;
181					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
182							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
183							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
184							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
185				};
186				map1 {
187					trip = <&cpu_alert1>;
188					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
189							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
191							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
192				};
193			};
194
195			trips {
196				cpu_alert0: cpu_alert0 {
197					/* milliCelsius */
198					temperature = <75000>;
199					hysteresis = <2000>;
200					type = "passive";
201				};
202
203				cpu_alert1: cpu_alert1 {
204					/* milliCelsius */
205					temperature = <90000>;
206					hysteresis = <2000>;
207					type = "hot";
208				};
209
210				cpu_crit: cpu_crit {
211					/* milliCelsius */
212					temperature = <110000>;
213					hysteresis = <2000>;
214					type = "critical";
215				};
216			};
217		};
218
219		gpu0_thermal: gpu0-thermal {
220			/* milliseconds */
221			polling-delay-passive = <0>;
222			polling-delay = <0>;
223			thermal-sensors = <&ths 1>;
224		};
225
226		gpu1_thermal: gpu1-thermal {
227			/* milliseconds */
228			polling-delay-passive = <0>;
229			polling-delay = <0>;
230			thermal-sensors = <&ths 2>;
231		};
232	};
233
234	soc {
235		compatible = "simple-bus";
236		#address-cells = <1>;
237		#size-cells = <1>;
238		ranges;
239
240		bus@1000000 {
241			compatible = "allwinner,sun50i-a64-de2";
242			reg = <0x1000000 0x400000>;
243			allwinner,sram = <&de2_sram 1>;
244			#address-cells = <1>;
245			#size-cells = <1>;
246			ranges = <0 0x1000000 0x400000>;
247
248			display_clocks: clock@0 {
249				compatible = "allwinner,sun50i-a64-de2-clk";
250				reg = <0x0 0x10000>;
251				clocks = <&ccu CLK_BUS_DE>,
252					 <&ccu CLK_DE>;
253				clock-names = "bus",
254					      "mod";
255				resets = <&ccu RST_BUS_DE>;
256				#clock-cells = <1>;
257				#reset-cells = <1>;
258			};
259
260			rotate: rotate@20000 {
261				compatible = "allwinner,sun50i-a64-de2-rotate",
262					     "allwinner,sun8i-a83t-de2-rotate";
263				reg = <0x20000 0x10000>;
264				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
265				clocks = <&display_clocks CLK_BUS_ROT>,
266					 <&display_clocks CLK_ROT>;
267				clock-names = "bus",
268					      "mod";
269				resets = <&display_clocks RST_ROT>;
270			};
271
272			mixer0: mixer@100000 {
273				compatible = "allwinner,sun50i-a64-de2-mixer-0";
274				reg = <0x100000 0x100000>;
275				clocks = <&display_clocks CLK_BUS_MIXER0>,
276					 <&display_clocks CLK_MIXER0>;
277				clock-names = "bus",
278					      "mod";
279				resets = <&display_clocks RST_MIXER0>;
280
281				ports {
282					#address-cells = <1>;
283					#size-cells = <0>;
284
285					mixer0_out: port@1 {
286						#address-cells = <1>;
287						#size-cells = <0>;
288						reg = <1>;
289
290						mixer0_out_tcon0: endpoint@0 {
291							reg = <0>;
292							remote-endpoint = <&tcon0_in_mixer0>;
293						};
294
295						mixer0_out_tcon1: endpoint@1 {
296							reg = <1>;
297							remote-endpoint = <&tcon1_in_mixer0>;
298						};
299					};
300				};
301			};
302
303			mixer1: mixer@200000 {
304				compatible = "allwinner,sun50i-a64-de2-mixer-1";
305				reg = <0x200000 0x100000>;
306				clocks = <&display_clocks CLK_BUS_MIXER1>,
307					 <&display_clocks CLK_MIXER1>;
308				clock-names = "bus",
309					      "mod";
310				resets = <&display_clocks RST_MIXER1>;
311
312				ports {
313					#address-cells = <1>;
314					#size-cells = <0>;
315
316					mixer1_out: port@1 {
317						#address-cells = <1>;
318						#size-cells = <0>;
319						reg = <1>;
320
321						mixer1_out_tcon0: endpoint@0 {
322							reg = <0>;
323							remote-endpoint = <&tcon0_in_mixer1>;
324						};
325
326						mixer1_out_tcon1: endpoint@1 {
327							reg = <1>;
328							remote-endpoint = <&tcon1_in_mixer1>;
329						};
330					};
331				};
332			};
333		};
334
335		syscon: syscon@1c00000 {
336			compatible = "allwinner,sun50i-a64-system-control";
337			reg = <0x01c00000 0x1000>;
338			#address-cells = <1>;
339			#size-cells = <1>;
340			ranges;
341
342			sram_c: sram@18000 {
343				compatible = "mmio-sram";
344				reg = <0x00018000 0x28000>;
345				#address-cells = <1>;
346				#size-cells = <1>;
347				ranges = <0 0x00018000 0x28000>;
348
349				de2_sram: sram-section@0 {
350					compatible = "allwinner,sun50i-a64-sram-c";
351					reg = <0x0000 0x28000>;
352				};
353			};
354
355			sram_c1: sram@1d00000 {
356				compatible = "mmio-sram";
357				reg = <0x01d00000 0x40000>;
358				#address-cells = <1>;
359				#size-cells = <1>;
360				ranges = <0 0x01d00000 0x40000>;
361
362				ve_sram: sram-section@0 {
363					compatible = "allwinner,sun50i-a64-sram-c1",
364						     "allwinner,sun4i-a10-sram-c1";
365					reg = <0x000000 0x40000>;
366				};
367			};
368		};
369
370		dma: dma-controller@1c02000 {
371			compatible = "allwinner,sun50i-a64-dma";
372			reg = <0x01c02000 0x1000>;
373			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
374			clocks = <&ccu CLK_BUS_DMA>;
375			dma-channels = <8>;
376			dma-requests = <27>;
377			resets = <&ccu RST_BUS_DMA>;
378			#dma-cells = <1>;
379		};
380
381		tcon0: lcd-controller@1c0c000 {
382			compatible = "allwinner,sun50i-a64-tcon-lcd",
383				     "allwinner,sun8i-a83t-tcon-lcd";
384			reg = <0x01c0c000 0x1000>;
385			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
386			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
387			clock-names = "ahb", "tcon-ch0";
388			clock-output-names = "tcon-pixel-clock";
389			#clock-cells = <0>;
390			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
391			reset-names = "lcd", "lvds";
392
393			ports {
394				#address-cells = <1>;
395				#size-cells = <0>;
396
397				tcon0_in: port@0 {
398					#address-cells = <1>;
399					#size-cells = <0>;
400					reg = <0>;
401
402					tcon0_in_mixer0: endpoint@0 {
403						reg = <0>;
404						remote-endpoint = <&mixer0_out_tcon0>;
405					};
406
407					tcon0_in_mixer1: endpoint@1 {
408						reg = <1>;
409						remote-endpoint = <&mixer1_out_tcon0>;
410					};
411				};
412
413				tcon0_out: port@1 {
414					#address-cells = <1>;
415					#size-cells = <0>;
416					reg = <1>;
417
418					tcon0_out_dsi: endpoint@1 {
419						reg = <1>;
420						remote-endpoint = <&dsi_in_tcon0>;
421						allwinner,tcon-channel = <1>;
422					};
423				};
424			};
425		};
426
427		tcon1: lcd-controller@1c0d000 {
428			compatible = "allwinner,sun50i-a64-tcon-tv",
429				     "allwinner,sun8i-a83t-tcon-tv";
430			reg = <0x01c0d000 0x1000>;
431			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
432			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
433			clock-names = "ahb", "tcon-ch1";
434			resets = <&ccu RST_BUS_TCON1>;
435			reset-names = "lcd";
436
437			ports {
438				#address-cells = <1>;
439				#size-cells = <0>;
440
441				tcon1_in: port@0 {
442					#address-cells = <1>;
443					#size-cells = <0>;
444					reg = <0>;
445
446					tcon1_in_mixer0: endpoint@0 {
447						reg = <0>;
448						remote-endpoint = <&mixer0_out_tcon1>;
449					};
450
451					tcon1_in_mixer1: endpoint@1 {
452						reg = <1>;
453						remote-endpoint = <&mixer1_out_tcon1>;
454					};
455				};
456
457				tcon1_out: port@1 {
458					#address-cells = <1>;
459					#size-cells = <0>;
460					reg = <1>;
461
462					tcon1_out_hdmi: endpoint@1 {
463						reg = <1>;
464						remote-endpoint = <&hdmi_in_tcon1>;
465					};
466				};
467			};
468		};
469
470		video-codec@1c0e000 {
471			compatible = "allwinner,sun50i-a64-video-engine";
472			reg = <0x01c0e000 0x1000>;
473			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
474				 <&ccu CLK_DRAM_VE>;
475			clock-names = "ahb", "mod", "ram";
476			resets = <&ccu RST_BUS_VE>;
477			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
478			allwinner,sram = <&ve_sram 1>;
479		};
480
481		mmc0: mmc@1c0f000 {
482			compatible = "allwinner,sun50i-a64-mmc";
483			reg = <0x01c0f000 0x1000>;
484			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
485			clock-names = "ahb", "mmc";
486			resets = <&ccu RST_BUS_MMC0>;
487			reset-names = "ahb";
488			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
489			max-frequency = <150000000>;
490			status = "disabled";
491			#address-cells = <1>;
492			#size-cells = <0>;
493		};
494
495		mmc1: mmc@1c10000 {
496			compatible = "allwinner,sun50i-a64-mmc";
497			reg = <0x01c10000 0x1000>;
498			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
499			clock-names = "ahb", "mmc";
500			resets = <&ccu RST_BUS_MMC1>;
501			reset-names = "ahb";
502			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
503			max-frequency = <150000000>;
504			status = "disabled";
505			#address-cells = <1>;
506			#size-cells = <0>;
507		};
508
509		mmc2: mmc@1c11000 {
510			compatible = "allwinner,sun50i-a64-emmc";
511			reg = <0x01c11000 0x1000>;
512			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
513			clock-names = "ahb", "mmc";
514			resets = <&ccu RST_BUS_MMC2>;
515			reset-names = "ahb";
516			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
517			max-frequency = <150000000>;
518			status = "disabled";
519			#address-cells = <1>;
520			#size-cells = <0>;
521		};
522
523		sid: eeprom@1c14000 {
524			compatible = "allwinner,sun50i-a64-sid";
525			reg = <0x1c14000 0x400>;
526			#address-cells = <1>;
527			#size-cells = <1>;
528
529			ths_calibration: thermal-sensor-calibration@34 {
530				reg = <0x34 0x8>;
531			};
532		};
533
534		crypto: crypto@1c15000 {
535			compatible = "allwinner,sun50i-a64-crypto";
536			reg = <0x01c15000 0x1000>;
537			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
538			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
539			clock-names = "bus", "mod";
540			resets = <&ccu RST_BUS_CE>;
541		};
542
543		msgbox: mailbox@1c17000 {
544			compatible = "allwinner,sun50i-a64-msgbox",
545				     "allwinner,sun6i-a31-msgbox";
546			reg = <0x01c17000 0x1000>;
547			clocks = <&ccu CLK_BUS_MSGBOX>;
548			resets = <&ccu RST_BUS_MSGBOX>;
549			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
550			#mbox-cells = <1>;
551		};
552
553		usb_otg: usb@1c19000 {
554			compatible = "allwinner,sun8i-a33-musb";
555			reg = <0x01c19000 0x0400>;
556			clocks = <&ccu CLK_BUS_OTG>;
557			resets = <&ccu RST_BUS_OTG>;
558			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
559			interrupt-names = "mc";
560			phys = <&usbphy 0>;
561			phy-names = "usb";
562			extcon = <&usbphy 0>;
563			dr_mode = "otg";
564			status = "disabled";
565		};
566
567		usbphy: phy@1c19400 {
568			compatible = "allwinner,sun50i-a64-usb-phy";
569			reg = <0x01c19400 0x14>,
570			      <0x01c1a800 0x4>,
571			      <0x01c1b800 0x4>;
572			reg-names = "phy_ctrl",
573				    "pmu0",
574				    "pmu1";
575			clocks = <&ccu CLK_USB_PHY0>,
576				 <&ccu CLK_USB_PHY1>;
577			clock-names = "usb0_phy",
578				      "usb1_phy";
579			resets = <&ccu RST_USB_PHY0>,
580				 <&ccu RST_USB_PHY1>;
581			reset-names = "usb0_reset",
582				      "usb1_reset";
583			status = "disabled";
584			#phy-cells = <1>;
585		};
586
587		ehci0: usb@1c1a000 {
588			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
589			reg = <0x01c1a000 0x100>;
590			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
591			clocks = <&ccu CLK_BUS_OHCI0>,
592				 <&ccu CLK_BUS_EHCI0>,
593				 <&ccu CLK_USB_OHCI0>;
594			resets = <&ccu RST_BUS_OHCI0>,
595				 <&ccu RST_BUS_EHCI0>;
596			phys = <&usbphy 0>;
597			phy-names = "usb";
598			status = "disabled";
599		};
600
601		ohci0: usb@1c1a400 {
602			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
603			reg = <0x01c1a400 0x100>;
604			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
605			clocks = <&ccu CLK_BUS_OHCI0>,
606				 <&ccu CLK_USB_OHCI0>;
607			resets = <&ccu RST_BUS_OHCI0>;
608			phys = <&usbphy 0>;
609			phy-names = "usb";
610			status = "disabled";
611		};
612
613		ehci1: usb@1c1b000 {
614			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
615			reg = <0x01c1b000 0x100>;
616			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
617			clocks = <&ccu CLK_BUS_OHCI1>,
618				 <&ccu CLK_BUS_EHCI1>,
619				 <&ccu CLK_USB_OHCI1>;
620			resets = <&ccu RST_BUS_OHCI1>,
621				 <&ccu RST_BUS_EHCI1>;
622			phys = <&usbphy 1>;
623			phy-names = "usb";
624			status = "disabled";
625		};
626
627		ohci1: usb@1c1b400 {
628			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
629			reg = <0x01c1b400 0x100>;
630			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
631			clocks = <&ccu CLK_BUS_OHCI1>,
632				 <&ccu CLK_USB_OHCI1>;
633			resets = <&ccu RST_BUS_OHCI1>;
634			phys = <&usbphy 1>;
635			phy-names = "usb";
636			status = "disabled";
637		};
638
639		ccu: clock@1c20000 {
640			compatible = "allwinner,sun50i-a64-ccu";
641			reg = <0x01c20000 0x400>;
642			clocks = <&osc24M>, <&rtc 0>;
643			clock-names = "hosc", "losc";
644			#clock-cells = <1>;
645			#reset-cells = <1>;
646		};
647
648		pio: pinctrl@1c20800 {
649			compatible = "allwinner,sun50i-a64-pinctrl";
650			reg = <0x01c20800 0x400>;
651			interrupt-parent = <&r_intc>;
652			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
653				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
654				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
655			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
656			clock-names = "apb", "hosc", "losc";
657			gpio-controller;
658			#gpio-cells = <3>;
659			interrupt-controller;
660			#interrupt-cells = <3>;
661
662			/omit-if-no-ref/
663			aif2_pins: aif2-pins {
664				pins = "PB4", "PB5", "PB6", "PB7";
665				function = "aif2";
666			};
667
668			/omit-if-no-ref/
669			aif3_pins: aif3-pins {
670				pins = "PG10", "PG11", "PG12", "PG13";
671				function = "aif3";
672			};
673
674			csi_pins: csi-pins {
675				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
676				       "PE7", "PE8", "PE9", "PE10", "PE11";
677				function = "csi";
678			};
679
680			/omit-if-no-ref/
681			csi_mclk_pin: csi-mclk-pin {
682				pins = "PE1";
683				function = "csi";
684			};
685
686			i2c0_pins: i2c0-pins {
687				pins = "PH0", "PH1";
688				function = "i2c0";
689			};
690
691			i2c1_pins: i2c1-pins {
692				pins = "PH2", "PH3";
693				function = "i2c1";
694			};
695
696			i2c2_pins: i2c2-pins {
697				pins = "PE14", "PE15";
698				function = "i2c2";
699			};
700
701			/omit-if-no-ref/
702			lcd_rgb666_pins: lcd-rgb666-pins {
703				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
704				       "PD5", "PD6", "PD7", "PD8", "PD9",
705				       "PD10", "PD11", "PD12", "PD13",
706				       "PD14", "PD15", "PD16", "PD17",
707				       "PD18", "PD19", "PD20", "PD21";
708				function = "lcd0";
709			};
710
711			mmc0_pins: mmc0-pins {
712				pins = "PF0", "PF1", "PF2", "PF3",
713				       "PF4", "PF5";
714				function = "mmc0";
715				drive-strength = <30>;
716				bias-pull-up;
717			};
718
719			mmc1_pins: mmc1-pins {
720				pins = "PG0", "PG1", "PG2", "PG3",
721				       "PG4", "PG5";
722				function = "mmc1";
723				drive-strength = <30>;
724				bias-pull-up;
725			};
726
727			mmc2_pins: mmc2-pins {
728				pins = "PC5", "PC6", "PC8", "PC9",
729				       "PC10","PC11", "PC12", "PC13",
730				       "PC14", "PC15", "PC16";
731				function = "mmc2";
732				drive-strength = <30>;
733				bias-pull-up;
734			};
735
736			mmc2_ds_pin: mmc2-ds-pin {
737				pins = "PC1";
738				function = "mmc2";
739				drive-strength = <30>;
740				bias-pull-up;
741			};
742
743			pwm_pin: pwm-pin {
744				pins = "PD22";
745				function = "pwm";
746			};
747
748			rmii_pins: rmii-pins {
749				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
750				       "PD18", "PD19", "PD20", "PD22", "PD23";
751				function = "emac";
752				drive-strength = <40>;
753			};
754
755			rgmii_pins: rgmii-pins {
756				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
757				       "PD13", "PD15", "PD16", "PD17", "PD18",
758				       "PD19", "PD20", "PD21", "PD22", "PD23";
759				function = "emac";
760				drive-strength = <40>;
761			};
762
763			spdif_tx_pin: spdif-tx-pin {
764				pins = "PH8";
765				function = "spdif";
766			};
767
768			spi0_pins: spi0-pins {
769				pins = "PC0", "PC1", "PC2", "PC3";
770				function = "spi0";
771			};
772
773			spi1_pins: spi1-pins {
774				pins = "PD0", "PD1", "PD2", "PD3";
775				function = "spi1";
776			};
777
778			uart0_pb_pins: uart0-pb-pins {
779				pins = "PB8", "PB9";
780				function = "uart0";
781			};
782
783			uart1_pins: uart1-pins {
784				pins = "PG6", "PG7";
785				function = "uart1";
786			};
787
788			uart1_rts_cts_pins: uart1-rts-cts-pins {
789				pins = "PG8", "PG9";
790				function = "uart1";
791			};
792
793			uart2_pins: uart2-pins {
794				pins = "PB0", "PB1";
795				function = "uart2";
796			};
797
798			uart3_pins: uart3-pins {
799				pins = "PD0", "PD1";
800				function = "uart3";
801			};
802
803			uart4_pins: uart4-pins {
804				pins = "PD2", "PD3";
805				function = "uart4";
806			};
807
808			uart4_rts_cts_pins: uart4-rts-cts-pins {
809				pins = "PD4", "PD5";
810				function = "uart4";
811			};
812		};
813
814		timer@1c20c00 {
815			compatible = "allwinner,sun50i-a64-timer",
816				     "allwinner,sun8i-a23-timer";
817			reg = <0x01c20c00 0xa0>;
818			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
819				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
820			clocks = <&osc24M>;
821		};
822
823		wdt0: watchdog@1c20ca0 {
824			compatible = "allwinner,sun50i-a64-wdt",
825				     "allwinner,sun6i-a31-wdt";
826			reg = <0x01c20ca0 0x20>;
827			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
828			clocks = <&osc24M>;
829		};
830
831		spdif: spdif@1c21000 {
832			#sound-dai-cells = <0>;
833			compatible = "allwinner,sun50i-a64-spdif",
834				     "allwinner,sun8i-h3-spdif";
835			reg = <0x01c21000 0x400>;
836			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
837			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
838			resets = <&ccu RST_BUS_SPDIF>;
839			clock-names = "apb", "spdif";
840			dmas = <&dma 2>;
841			dma-names = "tx";
842			pinctrl-names = "default";
843			pinctrl-0 = <&spdif_tx_pin>;
844			status = "disabled";
845		};
846
847		lradc: lradc@1c21800 {
848			compatible = "allwinner,sun50i-a64-lradc",
849				     "allwinner,sun8i-a83t-r-lradc";
850			reg = <0x01c21800 0x400>;
851			interrupt-parent = <&r_intc>;
852			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
853			status = "disabled";
854		};
855
856		i2s0: i2s@1c22000 {
857			#sound-dai-cells = <0>;
858			compatible = "allwinner,sun50i-a64-i2s",
859				     "allwinner,sun8i-h3-i2s";
860			reg = <0x01c22000 0x400>;
861			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
862			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
863			clock-names = "apb", "mod";
864			resets = <&ccu RST_BUS_I2S0>;
865			dma-names = "rx", "tx";
866			dmas = <&dma 3>, <&dma 3>;
867			status = "disabled";
868		};
869
870		i2s1: i2s@1c22400 {
871			#sound-dai-cells = <0>;
872			compatible = "allwinner,sun50i-a64-i2s",
873				     "allwinner,sun8i-h3-i2s";
874			reg = <0x01c22400 0x400>;
875			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
876			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
877			clock-names = "apb", "mod";
878			resets = <&ccu RST_BUS_I2S1>;
879			dma-names = "rx", "tx";
880			dmas = <&dma 4>, <&dma 4>;
881			status = "disabled";
882		};
883
884		i2s2: i2s@1c22800 {
885			#sound-dai-cells = <0>;
886			compatible = "allwinner,sun50i-a64-i2s",
887				     "allwinner,sun8i-h3-i2s";
888			reg = <0x01c22800 0x400>;
889			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
890			clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
891			clock-names = "apb", "mod";
892			resets = <&ccu RST_BUS_I2S2>;
893			dma-names = "rx", "tx";
894			dmas = <&dma 27>, <&dma 27>;
895			status = "disabled";
896		};
897
898		dai: dai@1c22c00 {
899			#sound-dai-cells = <0>;
900			compatible = "allwinner,sun50i-a64-codec-i2s";
901			reg = <0x01c22c00 0x200>;
902			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
903			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
904			clock-names = "apb", "mod";
905			resets = <&ccu RST_BUS_CODEC>;
906			dmas = <&dma 15>, <&dma 15>;
907			dma-names = "rx", "tx";
908			status = "disabled";
909		};
910
911		codec: codec@1c22e00 {
912			#sound-dai-cells = <1>;
913			compatible = "allwinner,sun50i-a64-codec",
914				     "allwinner,sun8i-a33-codec";
915			reg = <0x01c22e00 0x600>;
916			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
917			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
918			clock-names = "bus", "mod";
919			status = "disabled";
920		};
921
922		ths: thermal-sensor@1c25000 {
923			compatible = "allwinner,sun50i-a64-ths";
924			reg = <0x01c25000 0x100>;
925			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
926			clock-names = "bus", "mod";
927			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
928			resets = <&ccu RST_BUS_THS>;
929			nvmem-cells = <&ths_calibration>;
930			nvmem-cell-names = "calibration";
931			#thermal-sensor-cells = <1>;
932		};
933
934		uart0: serial@1c28000 {
935			compatible = "snps,dw-apb-uart";
936			reg = <0x01c28000 0x400>;
937			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
938			reg-shift = <2>;
939			reg-io-width = <4>;
940			clocks = <&ccu CLK_BUS_UART0>;
941			resets = <&ccu RST_BUS_UART0>;
942			status = "disabled";
943		};
944
945		uart1: serial@1c28400 {
946			compatible = "snps,dw-apb-uart";
947			reg = <0x01c28400 0x400>;
948			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
949			reg-shift = <2>;
950			reg-io-width = <4>;
951			clocks = <&ccu CLK_BUS_UART1>;
952			resets = <&ccu RST_BUS_UART1>;
953			status = "disabled";
954		};
955
956		uart2: serial@1c28800 {
957			compatible = "snps,dw-apb-uart";
958			reg = <0x01c28800 0x400>;
959			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
960			reg-shift = <2>;
961			reg-io-width = <4>;
962			clocks = <&ccu CLK_BUS_UART2>;
963			resets = <&ccu RST_BUS_UART2>;
964			status = "disabled";
965		};
966
967		uart3: serial@1c28c00 {
968			compatible = "snps,dw-apb-uart";
969			reg = <0x01c28c00 0x400>;
970			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
971			reg-shift = <2>;
972			reg-io-width = <4>;
973			clocks = <&ccu CLK_BUS_UART3>;
974			resets = <&ccu RST_BUS_UART3>;
975			status = "disabled";
976		};
977
978		uart4: serial@1c29000 {
979			compatible = "snps,dw-apb-uart";
980			reg = <0x01c29000 0x400>;
981			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
982			reg-shift = <2>;
983			reg-io-width = <4>;
984			clocks = <&ccu CLK_BUS_UART4>;
985			resets = <&ccu RST_BUS_UART4>;
986			status = "disabled";
987		};
988
989		i2c0: i2c@1c2ac00 {
990			compatible = "allwinner,sun6i-a31-i2c";
991			reg = <0x01c2ac00 0x400>;
992			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
993			clocks = <&ccu CLK_BUS_I2C0>;
994			resets = <&ccu RST_BUS_I2C0>;
995			pinctrl-names = "default";
996			pinctrl-0 = <&i2c0_pins>;
997			status = "disabled";
998			#address-cells = <1>;
999			#size-cells = <0>;
1000		};
1001
1002		i2c1: i2c@1c2b000 {
1003			compatible = "allwinner,sun6i-a31-i2c";
1004			reg = <0x01c2b000 0x400>;
1005			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1006			clocks = <&ccu CLK_BUS_I2C1>;
1007			resets = <&ccu RST_BUS_I2C1>;
1008			pinctrl-names = "default";
1009			pinctrl-0 = <&i2c1_pins>;
1010			status = "disabled";
1011			#address-cells = <1>;
1012			#size-cells = <0>;
1013		};
1014
1015		i2c2: i2c@1c2b400 {
1016			compatible = "allwinner,sun6i-a31-i2c";
1017			reg = <0x01c2b400 0x400>;
1018			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1019			clocks = <&ccu CLK_BUS_I2C2>;
1020			resets = <&ccu RST_BUS_I2C2>;
1021			pinctrl-names = "default";
1022			pinctrl-0 = <&i2c2_pins>;
1023			status = "disabled";
1024			#address-cells = <1>;
1025			#size-cells = <0>;
1026		};
1027
1028		spi0: spi@1c68000 {
1029			compatible = "allwinner,sun8i-h3-spi";
1030			reg = <0x01c68000 0x1000>;
1031			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1032			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1033			clock-names = "ahb", "mod";
1034			dmas = <&dma 23>, <&dma 23>;
1035			dma-names = "rx", "tx";
1036			pinctrl-names = "default";
1037			pinctrl-0 = <&spi0_pins>;
1038			resets = <&ccu RST_BUS_SPI0>;
1039			status = "disabled";
1040			num-cs = <1>;
1041			#address-cells = <1>;
1042			#size-cells = <0>;
1043		};
1044
1045		spi1: spi@1c69000 {
1046			compatible = "allwinner,sun8i-h3-spi";
1047			reg = <0x01c69000 0x1000>;
1048			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1049			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1050			clock-names = "ahb", "mod";
1051			dmas = <&dma 24>, <&dma 24>;
1052			dma-names = "rx", "tx";
1053			pinctrl-names = "default";
1054			pinctrl-0 = <&spi1_pins>;
1055			resets = <&ccu RST_BUS_SPI1>;
1056			status = "disabled";
1057			num-cs = <1>;
1058			#address-cells = <1>;
1059			#size-cells = <0>;
1060		};
1061
1062		emac: ethernet@1c30000 {
1063			compatible = "allwinner,sun50i-a64-emac";
1064			syscon = <&syscon>;
1065			reg = <0x01c30000 0x10000>;
1066			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1067			interrupt-names = "macirq";
1068			resets = <&ccu RST_BUS_EMAC>;
1069			reset-names = "stmmaceth";
1070			clocks = <&ccu CLK_BUS_EMAC>;
1071			clock-names = "stmmaceth";
1072			status = "disabled";
1073
1074			mdio: mdio {
1075				compatible = "snps,dwmac-mdio";
1076				#address-cells = <1>;
1077				#size-cells = <0>;
1078			};
1079		};
1080
1081		mali: gpu@1c40000 {
1082			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1083			reg = <0x01c40000 0x10000>;
1084			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1085				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1086				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1087				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1088				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1089				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1090				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1091			interrupt-names = "gp",
1092					  "gpmmu",
1093					  "pp0",
1094					  "ppmmu0",
1095					  "pp1",
1096					  "ppmmu1",
1097					  "pmu";
1098			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1099			clock-names = "bus", "core";
1100			resets = <&ccu RST_BUS_GPU>;
1101		};
1102
1103		gic: interrupt-controller@1c81000 {
1104			compatible = "arm,gic-400";
1105			reg = <0x01c81000 0x1000>,
1106			      <0x01c82000 0x2000>,
1107			      <0x01c84000 0x2000>,
1108			      <0x01c86000 0x2000>;
1109			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1110			interrupt-controller;
1111			#interrupt-cells = <3>;
1112		};
1113
1114		pwm: pwm@1c21400 {
1115			compatible = "allwinner,sun50i-a64-pwm",
1116				     "allwinner,sun5i-a13-pwm";
1117			reg = <0x01c21400 0x400>;
1118			clocks = <&osc24M>;
1119			pinctrl-names = "default";
1120			pinctrl-0 = <&pwm_pin>;
1121			#pwm-cells = <3>;
1122			status = "disabled";
1123		};
1124
1125		mbus: dram-controller@1c62000 {
1126			compatible = "allwinner,sun50i-a64-mbus";
1127			reg = <0x01c62000 0x1000>;
1128			clocks = <&ccu 112>;
1129			#address-cells = <1>;
1130			#size-cells = <1>;
1131			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1132			#interconnect-cells = <1>;
1133		};
1134
1135		csi: csi@1cb0000 {
1136			compatible = "allwinner,sun50i-a64-csi";
1137			reg = <0x01cb0000 0x1000>;
1138			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1139			clocks = <&ccu CLK_BUS_CSI>,
1140				 <&ccu CLK_CSI_SCLK>,
1141				 <&ccu CLK_DRAM_CSI>;
1142			clock-names = "bus", "mod", "ram";
1143			resets = <&ccu RST_BUS_CSI>;
1144			pinctrl-names = "default";
1145			pinctrl-0 = <&csi_pins>;
1146			status = "disabled";
1147		};
1148
1149		dsi: dsi@1ca0000 {
1150			compatible = "allwinner,sun50i-a64-mipi-dsi";
1151			reg = <0x01ca0000 0x1000>;
1152			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1153			clocks = <&ccu CLK_BUS_MIPI_DSI>;
1154			resets = <&ccu RST_BUS_MIPI_DSI>;
1155			phys = <&dphy>;
1156			phy-names = "dphy";
1157			status = "disabled";
1158			#address-cells = <1>;
1159			#size-cells = <0>;
1160
1161			port {
1162				dsi_in_tcon0: endpoint {
1163					remote-endpoint = <&tcon0_out_dsi>;
1164				};
1165			};
1166		};
1167
1168		dphy: d-phy@1ca1000 {
1169			compatible = "allwinner,sun50i-a64-mipi-dphy",
1170				     "allwinner,sun6i-a31-mipi-dphy";
1171			reg = <0x01ca1000 0x1000>;
1172			clocks = <&ccu CLK_BUS_MIPI_DSI>,
1173				 <&ccu CLK_DSI_DPHY>;
1174			clock-names = "bus", "mod";
1175			resets = <&ccu RST_BUS_MIPI_DSI>;
1176			status = "disabled";
1177			#phy-cells = <0>;
1178		};
1179
1180		deinterlace: deinterlace@1e00000 {
1181			compatible = "allwinner,sun50i-a64-deinterlace",
1182				     "allwinner,sun8i-h3-deinterlace";
1183			reg = <0x01e00000 0x20000>;
1184			clocks = <&ccu CLK_BUS_DEINTERLACE>,
1185				 <&ccu CLK_DEINTERLACE>,
1186				 <&ccu CLK_DRAM_DEINTERLACE>;
1187			clock-names = "bus", "mod", "ram";
1188			resets = <&ccu RST_BUS_DEINTERLACE>;
1189			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1190			interconnects = <&mbus 9>;
1191			interconnect-names = "dma-mem";
1192		};
1193
1194		hdmi: hdmi@1ee0000 {
1195			compatible = "allwinner,sun50i-a64-dw-hdmi",
1196				     "allwinner,sun8i-a83t-dw-hdmi";
1197			reg = <0x01ee0000 0x10000>;
1198			reg-io-width = <1>;
1199			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1200			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1201				 <&ccu CLK_HDMI>;
1202			clock-names = "iahb", "isfr", "tmds";
1203			resets = <&ccu RST_BUS_HDMI1>;
1204			reset-names = "ctrl";
1205			phys = <&hdmi_phy>;
1206			phy-names = "phy";
1207			status = "disabled";
1208
1209			ports {
1210				#address-cells = <1>;
1211				#size-cells = <0>;
1212
1213				hdmi_in: port@0 {
1214					reg = <0>;
1215
1216					hdmi_in_tcon1: endpoint {
1217						remote-endpoint = <&tcon1_out_hdmi>;
1218					};
1219				};
1220
1221				hdmi_out: port@1 {
1222					reg = <1>;
1223				};
1224			};
1225		};
1226
1227		hdmi_phy: hdmi-phy@1ef0000 {
1228			compatible = "allwinner,sun50i-a64-hdmi-phy";
1229			reg = <0x01ef0000 0x10000>;
1230			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1231				 <&ccu CLK_PLL_VIDEO0>;
1232			clock-names = "bus", "mod", "pll-0";
1233			resets = <&ccu RST_BUS_HDMI0>;
1234			reset-names = "phy";
1235			#phy-cells = <0>;
1236		};
1237
1238		rtc: rtc@1f00000 {
1239			compatible = "allwinner,sun50i-a64-rtc",
1240				     "allwinner,sun8i-h3-rtc";
1241			reg = <0x01f00000 0x400>;
1242			interrupt-parent = <&r_intc>;
1243			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1244				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1245			clock-output-names = "osc32k", "osc32k-out", "iosc";
1246			clocks = <&osc32k>;
1247			#clock-cells = <1>;
1248		};
1249
1250		r_intc: interrupt-controller@1f00c00 {
1251			compatible = "allwinner,sun50i-a64-r-intc",
1252				     "allwinner,sun6i-a31-r-intc";
1253			interrupt-controller;
1254			#interrupt-cells = <3>;
1255			reg = <0x01f00c00 0x400>;
1256			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1257		};
1258
1259		r_ccu: clock@1f01400 {
1260			compatible = "allwinner,sun50i-a64-r-ccu";
1261			reg = <0x01f01400 0x100>;
1262			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1263				 <&ccu CLK_PLL_PERIPH0>;
1264			clock-names = "hosc", "losc", "iosc", "pll-periph";
1265			#clock-cells = <1>;
1266			#reset-cells = <1>;
1267		};
1268
1269		codec_analog: codec-analog@1f015c0 {
1270			compatible = "allwinner,sun50i-a64-codec-analog";
1271			reg = <0x01f015c0 0x4>;
1272			status = "disabled";
1273		};
1274
1275		r_i2c: i2c@1f02400 {
1276			compatible = "allwinner,sun50i-a64-i2c",
1277				     "allwinner,sun6i-a31-i2c";
1278			reg = <0x01f02400 0x400>;
1279			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1280			clocks = <&r_ccu CLK_APB0_I2C>;
1281			resets = <&r_ccu RST_APB0_I2C>;
1282			status = "disabled";
1283			#address-cells = <1>;
1284			#size-cells = <0>;
1285		};
1286
1287		r_ir: ir@1f02000 {
1288			compatible = "allwinner,sun50i-a64-ir",
1289				     "allwinner,sun6i-a31-ir";
1290			reg = <0x01f02000 0x400>;
1291			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1292			clock-names = "apb", "ir";
1293			resets = <&r_ccu RST_APB0_IR>;
1294			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1295			pinctrl-names = "default";
1296			pinctrl-0 = <&r_ir_rx_pin>;
1297			status = "disabled";
1298		};
1299
1300		r_pwm: pwm@1f03800 {
1301			compatible = "allwinner,sun50i-a64-pwm",
1302				     "allwinner,sun5i-a13-pwm";
1303			reg = <0x01f03800 0x400>;
1304			clocks = <&osc24M>;
1305			pinctrl-names = "default";
1306			pinctrl-0 = <&r_pwm_pin>;
1307			#pwm-cells = <3>;
1308			status = "disabled";
1309		};
1310
1311		r_pio: pinctrl@1f02c00 {
1312			compatible = "allwinner,sun50i-a64-r-pinctrl";
1313			reg = <0x01f02c00 0x400>;
1314			interrupt-parent = <&r_intc>;
1315			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1316			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1317			clock-names = "apb", "hosc", "losc";
1318			gpio-controller;
1319			#gpio-cells = <3>;
1320			interrupt-controller;
1321			#interrupt-cells = <3>;
1322
1323			r_i2c_pl89_pins: r-i2c-pl89-pins {
1324				pins = "PL8", "PL9";
1325				function = "s_i2c";
1326			};
1327
1328			r_ir_rx_pin: r-ir-rx-pin {
1329				pins = "PL11";
1330				function = "s_cir_rx";
1331			};
1332
1333			r_pwm_pin: r-pwm-pin {
1334				pins = "PL10";
1335				function = "s_pwm";
1336			};
1337
1338			r_rsb_pins: r-rsb-pins {
1339				pins = "PL0", "PL1";
1340				function = "s_rsb";
1341			};
1342		};
1343
1344		r_rsb: rsb@1f03400 {
1345			compatible = "allwinner,sun8i-a23-rsb";
1346			reg = <0x01f03400 0x400>;
1347			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1348			clocks = <&r_ccu 6>;
1349			clock-frequency = <3000000>;
1350			resets = <&r_ccu 2>;
1351			pinctrl-names = "default";
1352			pinctrl-0 = <&r_rsb_pins>;
1353			status = "disabled";
1354			#address-cells = <1>;
1355			#size-cells = <0>;
1356		};
1357	};
1358};
1359