1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd.
3cabbaed7SClément Péron// based on the Allwinner H3 dtsi:
4cabbaed7SClément Péron//    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
56bc37facSAndre Przywara
6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h>
72c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h>
8494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h>
96bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h>
10a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h>
112c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h>
12871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h>
1359f5e9b9SVasily Khoruzhick#include <dt-bindings/thermal/thermal.h>
146bc37facSAndre Przywara
156bc37facSAndre Przywara/ {
166bc37facSAndre Przywara	interrupt-parent = <&gic>;
176bc37facSAndre Przywara	#address-cells = <1>;
186bc37facSAndre Przywara	#size-cells = <1>;
196bc37facSAndre Przywara
20c1cff65fSHarald Geyer	chosen {
21c1cff65fSHarald Geyer		#address-cells = <1>;
22c1cff65fSHarald Geyer		#size-cells = <1>;
23c1cff65fSHarald Geyer		ranges;
24c1cff65fSHarald Geyer
25c1cff65fSHarald Geyer		simplefb_lcd: framebuffer-lcd {
26c1cff65fSHarald Geyer			compatible = "allwinner,simple-framebuffer",
27c1cff65fSHarald Geyer				     "simple-framebuffer";
28c1cff65fSHarald Geyer			allwinner,pipeline = "mixer0-lcd0";
29c1cff65fSHarald Geyer			clocks = <&ccu CLK_TCON0>,
302c796fc8SIcenowy Zheng				 <&display_clocks CLK_MIXER0>;
31c1cff65fSHarald Geyer			status = "disabled";
32c1cff65fSHarald Geyer		};
33fca63f58SIcenowy Zheng
34fca63f58SIcenowy Zheng		simplefb_hdmi: framebuffer-hdmi {
35fca63f58SIcenowy Zheng			compatible = "allwinner,simple-framebuffer",
36fca63f58SIcenowy Zheng				     "simple-framebuffer";
37fca63f58SIcenowy Zheng			allwinner,pipeline = "mixer1-lcd1-hdmi";
38fca63f58SIcenowy Zheng			clocks = <&display_clocks CLK_MIXER1>,
39fca63f58SIcenowy Zheng				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
40fca63f58SIcenowy Zheng			status = "disabled";
41fca63f58SIcenowy Zheng		};
42c1cff65fSHarald Geyer	};
43c1cff65fSHarald Geyer
446bc37facSAndre Przywara	cpus {
456bc37facSAndre Przywara		#address-cells = <1>;
466bc37facSAndre Przywara		#size-cells = <0>;
476bc37facSAndre Przywara
486bc37facSAndre Przywara		cpu0: cpu@0 {
4931af04cdSRob Herring			compatible = "arm,cortex-a53";
506bc37facSAndre Przywara			device_type = "cpu";
516bc37facSAndre Przywara			reg = <0>;
526bc37facSAndre Przywara			enable-method = "psci";
5339defc81SAndre Przywara			next-level-cache = <&L2>;
54f267eff7SVasily Khoruzhick			clocks = <&ccu 21>;
55f267eff7SVasily Khoruzhick			clock-names = "cpu";
566bc37facSAndre Przywara		};
576bc37facSAndre Przywara
586bc37facSAndre Przywara		cpu1: cpu@1 {
5931af04cdSRob Herring			compatible = "arm,cortex-a53";
606bc37facSAndre Przywara			device_type = "cpu";
616bc37facSAndre Przywara			reg = <1>;
626bc37facSAndre Przywara			enable-method = "psci";
6339defc81SAndre Przywara			next-level-cache = <&L2>;
64f267eff7SVasily Khoruzhick			clocks = <&ccu 21>;
65f267eff7SVasily Khoruzhick			clock-names = "cpu";
666bc37facSAndre Przywara		};
676bc37facSAndre Przywara
686bc37facSAndre Przywara		cpu2: cpu@2 {
6931af04cdSRob Herring			compatible = "arm,cortex-a53";
706bc37facSAndre Przywara			device_type = "cpu";
716bc37facSAndre Przywara			reg = <2>;
726bc37facSAndre Przywara			enable-method = "psci";
7339defc81SAndre Przywara			next-level-cache = <&L2>;
74f267eff7SVasily Khoruzhick			clocks = <&ccu 21>;
75f267eff7SVasily Khoruzhick			clock-names = "cpu";
766bc37facSAndre Przywara		};
776bc37facSAndre Przywara
786bc37facSAndre Przywara		cpu3: cpu@3 {
7931af04cdSRob Herring			compatible = "arm,cortex-a53";
806bc37facSAndre Przywara			device_type = "cpu";
816bc37facSAndre Przywara			reg = <3>;
826bc37facSAndre Przywara			enable-method = "psci";
8339defc81SAndre Przywara			next-level-cache = <&L2>;
84f267eff7SVasily Khoruzhick			clocks = <&ccu 21>;
85f267eff7SVasily Khoruzhick			clock-names = "cpu";
8639defc81SAndre Przywara		};
8739defc81SAndre Przywara
8839defc81SAndre Przywara		L2: l2-cache {
8939defc81SAndre Przywara			compatible = "cache";
9039defc81SAndre Przywara			cache-level = <2>;
916bc37facSAndre Przywara		};
926bc37facSAndre Przywara	};
936bc37facSAndre Przywara
94e85f28e0SJagan Teki	de: display-engine {
95e85f28e0SJagan Teki		compatible = "allwinner,sun50i-a64-display-engine";
96e85f28e0SJagan Teki		allwinner,pipelines = <&mixer0>,
97e85f28e0SJagan Teki				      <&mixer1>;
98e85f28e0SJagan Teki		status = "disabled";
99e85f28e0SJagan Teki	};
100e85f28e0SJagan Teki
1016bc37facSAndre Przywara	osc24M: osc24M_clk {
1026bc37facSAndre Przywara		#clock-cells = <0>;
1036bc37facSAndre Przywara		compatible = "fixed-clock";
1046bc37facSAndre Przywara		clock-frequency = <24000000>;
1056bc37facSAndre Przywara		clock-output-names = "osc24M";
1066bc37facSAndre Przywara	};
1076bc37facSAndre Przywara
1086bc37facSAndre Przywara	osc32k: osc32k_clk {
1096bc37facSAndre Przywara		#clock-cells = <0>;
1106bc37facSAndre Przywara		compatible = "fixed-clock";
1116bc37facSAndre Przywara		clock-frequency = <32768>;
11244ff3cafSChen-Yu Tsai		clock-output-names = "ext-osc32k";
113791a9e00SIcenowy Zheng	};
114791a9e00SIcenowy Zheng
11534a97fccSHarald Geyer	pmu {
11634a97fccSHarald Geyer		compatible = "arm,cortex-a53-pmu";
1176b832a14SAndre Przywara		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1186b832a14SAndre Przywara			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1196b832a14SAndre Przywara			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1206b832a14SAndre Przywara			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
12134a97fccSHarald Geyer		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
12234a97fccSHarald Geyer	};
12334a97fccSHarald Geyer
1246bc37facSAndre Przywara	psci {
1256bc37facSAndre Przywara		compatible = "arm,psci-0.2";
1266bc37facSAndre Przywara		method = "smc";
1276bc37facSAndre Przywara	};
1286bc37facSAndre Przywara
129ec4a9540SVasily Khoruzhick	sound: sound {
130ec4a9540SVasily Khoruzhick		compatible = "simple-audio-card";
131ec4a9540SVasily Khoruzhick		simple-audio-card,name = "sun50i-a64-audio";
132ec4a9540SVasily Khoruzhick		simple-audio-card,format = "i2s";
133ec4a9540SVasily Khoruzhick		simple-audio-card,frame-master = <&cpudai>;
134ec4a9540SVasily Khoruzhick		simple-audio-card,bitclock-master = <&cpudai>;
135ec4a9540SVasily Khoruzhick		simple-audio-card,mclk-fs = <128>;
136ec4a9540SVasily Khoruzhick		simple-audio-card,aux-devs = <&codec_analog>;
137ec4a9540SVasily Khoruzhick		simple-audio-card,routing =
138ec4a9540SVasily Khoruzhick				"Left DAC", "AIF1 Slot 0 Left",
139ec4a9540SVasily Khoruzhick				"Right DAC", "AIF1 Slot 0 Right",
140ec4a9540SVasily Khoruzhick				"AIF1 Slot 0 Left ADC", "Left ADC",
141ec4a9540SVasily Khoruzhick				"AIF1 Slot 0 Right ADC", "Right ADC";
142ec4a9540SVasily Khoruzhick		status = "disabled";
143ec4a9540SVasily Khoruzhick
144ec4a9540SVasily Khoruzhick		cpudai: simple-audio-card,cpu {
145ec4a9540SVasily Khoruzhick			sound-dai = <&dai>;
146ec4a9540SVasily Khoruzhick		};
147ec4a9540SVasily Khoruzhick
148ec4a9540SVasily Khoruzhick		link_codec: simple-audio-card,codec {
149ec4a9540SVasily Khoruzhick			sound-dai = <&codec>;
150ec4a9540SVasily Khoruzhick		};
151ec4a9540SVasily Khoruzhick	};
152ec4a9540SVasily Khoruzhick
15378e07137SMarcus Cooper	sound_spdif {
15478e07137SMarcus Cooper		compatible = "simple-audio-card";
15578e07137SMarcus Cooper		simple-audio-card,name = "On-board SPDIF";
15678e07137SMarcus Cooper
15778e07137SMarcus Cooper		simple-audio-card,cpu {
15878e07137SMarcus Cooper			sound-dai = <&spdif>;
15978e07137SMarcus Cooper		};
16078e07137SMarcus Cooper
16178e07137SMarcus Cooper		simple-audio-card,codec {
16278e07137SMarcus Cooper			sound-dai = <&spdif_out>;
16378e07137SMarcus Cooper		};
16478e07137SMarcus Cooper	};
16578e07137SMarcus Cooper
16678e07137SMarcus Cooper	spdif_out: spdif-out {
16778e07137SMarcus Cooper		#sound-dai-cells = <0>;
16878e07137SMarcus Cooper		compatible = "linux,spdif-dit";
16978e07137SMarcus Cooper	};
17078e07137SMarcus Cooper
1716bc37facSAndre Przywara	timer {
1726bc37facSAndre Przywara		compatible = "arm,armv8-timer";
17355ec26d6SSamuel Holland		allwinner,erratum-unknown1;
1746bc37facSAndre Przywara		interrupts = <GIC_PPI 13
1756bc37facSAndre Przywara			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
1766bc37facSAndre Przywara			     <GIC_PPI 14
1776bc37facSAndre Przywara			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
1786bc37facSAndre Przywara			     <GIC_PPI 11
1796bc37facSAndre Przywara			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
1806bc37facSAndre Przywara			     <GIC_PPI 10
1816bc37facSAndre Przywara			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1826bc37facSAndre Przywara	};
1836bc37facSAndre Przywara
18459f5e9b9SVasily Khoruzhick	thermal-zones {
18559f5e9b9SVasily Khoruzhick		cpu_thermal: cpu0-thermal {
18659f5e9b9SVasily Khoruzhick			/* milliseconds */
18759f5e9b9SVasily Khoruzhick			polling-delay-passive = <0>;
18859f5e9b9SVasily Khoruzhick			polling-delay = <0>;
18959f5e9b9SVasily Khoruzhick			thermal-sensors = <&ths 0>;
19059f5e9b9SVasily Khoruzhick		};
19159f5e9b9SVasily Khoruzhick
19259f5e9b9SVasily Khoruzhick		gpu0_thermal: gpu0-thermal {
19359f5e9b9SVasily Khoruzhick			/* milliseconds */
19459f5e9b9SVasily Khoruzhick			polling-delay-passive = <0>;
19559f5e9b9SVasily Khoruzhick			polling-delay = <0>;
19659f5e9b9SVasily Khoruzhick			thermal-sensors = <&ths 1>;
19759f5e9b9SVasily Khoruzhick		};
19859f5e9b9SVasily Khoruzhick
19959f5e9b9SVasily Khoruzhick		gpu1_thermal: gpu1-thermal {
20059f5e9b9SVasily Khoruzhick			/* milliseconds */
20159f5e9b9SVasily Khoruzhick			polling-delay-passive = <0>;
20259f5e9b9SVasily Khoruzhick			polling-delay = <0>;
20359f5e9b9SVasily Khoruzhick			thermal-sensors = <&ths 2>;
20459f5e9b9SVasily Khoruzhick		};
20559f5e9b9SVasily Khoruzhick	};
20659f5e9b9SVasily Khoruzhick
2076bc37facSAndre Przywara	soc {
2086bc37facSAndre Przywara		compatible = "simple-bus";
2096bc37facSAndre Przywara		#address-cells = <1>;
2106bc37facSAndre Przywara		#size-cells = <1>;
2116bc37facSAndre Przywara		ranges;
2126bc37facSAndre Przywara
213275b6317SMaxime Ripard		bus@1000000 {
2142c796fc8SIcenowy Zheng			compatible = "allwinner,sun50i-a64-de2";
2152c796fc8SIcenowy Zheng			reg = <0x1000000 0x400000>;
2162c796fc8SIcenowy Zheng			allwinner,sram = <&de2_sram 1>;
2172c796fc8SIcenowy Zheng			#address-cells = <1>;
2182c796fc8SIcenowy Zheng			#size-cells = <1>;
2192c796fc8SIcenowy Zheng			ranges = <0 0x1000000 0x400000>;
2202c796fc8SIcenowy Zheng
2212c796fc8SIcenowy Zheng			display_clocks: clock@0 {
2222c796fc8SIcenowy Zheng				compatible = "allwinner,sun50i-a64-de2-clk";
2232c796fc8SIcenowy Zheng				reg = <0x0 0x100000>;
2245ea40f71SMaxime Ripard				clocks = <&ccu CLK_BUS_DE>,
2255ea40f71SMaxime Ripard					 <&ccu CLK_DE>;
2265ea40f71SMaxime Ripard				clock-names = "bus",
2275ea40f71SMaxime Ripard					      "mod";
2282c796fc8SIcenowy Zheng				resets = <&ccu RST_BUS_DE>;
2292c796fc8SIcenowy Zheng				#clock-cells = <1>;
2302c796fc8SIcenowy Zheng				#reset-cells = <1>;
2312c796fc8SIcenowy Zheng			};
232e85f28e0SJagan Teki
233e85f28e0SJagan Teki			mixer0: mixer@100000 {
234e85f28e0SJagan Teki				compatible = "allwinner,sun50i-a64-de2-mixer-0";
235e85f28e0SJagan Teki				reg = <0x100000 0x100000>;
236e85f28e0SJagan Teki				clocks = <&display_clocks CLK_BUS_MIXER0>,
237e85f28e0SJagan Teki					 <&display_clocks CLK_MIXER0>;
238e85f28e0SJagan Teki				clock-names = "bus",
239e85f28e0SJagan Teki					      "mod";
240e85f28e0SJagan Teki				resets = <&display_clocks RST_MIXER0>;
241e85f28e0SJagan Teki
242e85f28e0SJagan Teki				ports {
243e85f28e0SJagan Teki					#address-cells = <1>;
244e85f28e0SJagan Teki					#size-cells = <0>;
245e85f28e0SJagan Teki
246e85f28e0SJagan Teki					mixer0_out: port@1 {
247a7f7047fSMaxime Ripard						#address-cells = <1>;
248a7f7047fSMaxime Ripard						#size-cells = <0>;
249e85f28e0SJagan Teki						reg = <1>;
250e85f28e0SJagan Teki
251a7f7047fSMaxime Ripard						mixer0_out_tcon0: endpoint@0 {
252a7f7047fSMaxime Ripard							reg = <0>;
253e85f28e0SJagan Teki							remote-endpoint = <&tcon0_in_mixer0>;
254e85f28e0SJagan Teki						};
255a7f7047fSMaxime Ripard
256a7f7047fSMaxime Ripard						mixer0_out_tcon1: endpoint@1 {
257a7f7047fSMaxime Ripard							reg = <1>;
258a7f7047fSMaxime Ripard							remote-endpoint = <&tcon1_in_mixer0>;
259a7f7047fSMaxime Ripard						};
260e85f28e0SJagan Teki					};
261e85f28e0SJagan Teki				};
262e85f28e0SJagan Teki			};
263e85f28e0SJagan Teki
264e85f28e0SJagan Teki			mixer1: mixer@200000 {
265e85f28e0SJagan Teki				compatible = "allwinner,sun50i-a64-de2-mixer-1";
266e85f28e0SJagan Teki				reg = <0x200000 0x100000>;
267e85f28e0SJagan Teki				clocks = <&display_clocks CLK_BUS_MIXER1>,
268e85f28e0SJagan Teki					 <&display_clocks CLK_MIXER1>;
269e85f28e0SJagan Teki				clock-names = "bus",
270e85f28e0SJagan Teki					      "mod";
271e85f28e0SJagan Teki				resets = <&display_clocks RST_MIXER1>;
272e85f28e0SJagan Teki
273e85f28e0SJagan Teki				ports {
274e85f28e0SJagan Teki					#address-cells = <1>;
275e85f28e0SJagan Teki					#size-cells = <0>;
276e85f28e0SJagan Teki
277e85f28e0SJagan Teki					mixer1_out: port@1 {
278d41a43a0SMaxime Ripard						#address-cells = <1>;
279d41a43a0SMaxime Ripard						#size-cells = <0>;
280e85f28e0SJagan Teki						reg = <1>;
281e85f28e0SJagan Teki
282a7f7047fSMaxime Ripard						mixer1_out_tcon0: endpoint@0 {
283a7f7047fSMaxime Ripard							reg = <0>;
284a7f7047fSMaxime Ripard							remote-endpoint = <&tcon0_in_mixer1>;
285a7f7047fSMaxime Ripard						};
286a7f7047fSMaxime Ripard
287a7f7047fSMaxime Ripard						mixer1_out_tcon1: endpoint@1 {
288a7f7047fSMaxime Ripard							reg = <1>;
289e85f28e0SJagan Teki							remote-endpoint = <&tcon1_in_mixer1>;
290e85f28e0SJagan Teki						};
291e85f28e0SJagan Teki					};
292e85f28e0SJagan Teki				};
293e85f28e0SJagan Teki			};
2942c796fc8SIcenowy Zheng		};
2952c796fc8SIcenowy Zheng
29679b95360SCorentin Labbe		syscon: syscon@1c00000 {
2971f1f5183SIcenowy Zheng			compatible = "allwinner,sun50i-a64-system-control";
29879b95360SCorentin Labbe			reg = <0x01c00000 0x1000>;
2991f1f5183SIcenowy Zheng			#address-cells = <1>;
3001f1f5183SIcenowy Zheng			#size-cells = <1>;
3011f1f5183SIcenowy Zheng			ranges;
3021f1f5183SIcenowy Zheng
3031f1f5183SIcenowy Zheng			sram_c: sram@18000 {
3041f1f5183SIcenowy Zheng				compatible = "mmio-sram";
3051f1f5183SIcenowy Zheng				reg = <0x00018000 0x28000>;
3061f1f5183SIcenowy Zheng				#address-cells = <1>;
3071f1f5183SIcenowy Zheng				#size-cells = <1>;
3081f1f5183SIcenowy Zheng				ranges = <0 0x00018000 0x28000>;
3091f1f5183SIcenowy Zheng
3101f1f5183SIcenowy Zheng				de2_sram: sram-section@0 {
3111f1f5183SIcenowy Zheng					compatible = "allwinner,sun50i-a64-sram-c";
3121f1f5183SIcenowy Zheng					reg = <0x0000 0x28000>;
3131f1f5183SIcenowy Zheng				};
3141f1f5183SIcenowy Zheng			};
315106deea8SPaul Kocialkowski
316106deea8SPaul Kocialkowski			sram_c1: sram@1d00000 {
317106deea8SPaul Kocialkowski				compatible = "mmio-sram";
318106deea8SPaul Kocialkowski				reg = <0x01d00000 0x40000>;
319106deea8SPaul Kocialkowski				#address-cells = <1>;
320106deea8SPaul Kocialkowski				#size-cells = <1>;
321106deea8SPaul Kocialkowski				ranges = <0 0x01d00000 0x40000>;
322106deea8SPaul Kocialkowski
323106deea8SPaul Kocialkowski				ve_sram: sram-section@0 {
324106deea8SPaul Kocialkowski					compatible = "allwinner,sun50i-a64-sram-c1",
325106deea8SPaul Kocialkowski						     "allwinner,sun4i-a10-sram-c1";
326106deea8SPaul Kocialkowski					reg = <0x000000 0x40000>;
327106deea8SPaul Kocialkowski				};
328106deea8SPaul Kocialkowski			};
32979b95360SCorentin Labbe		};
33079b95360SCorentin Labbe
331c32637e0SStefan Brüns		dma: dma-controller@1c02000 {
332c32637e0SStefan Brüns			compatible = "allwinner,sun50i-a64-dma";
333c32637e0SStefan Brüns			reg = <0x01c02000 0x1000>;
334c32637e0SStefan Brüns			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
335c32637e0SStefan Brüns			clocks = <&ccu CLK_BUS_DMA>;
336c32637e0SStefan Brüns			dma-channels = <8>;
337c32637e0SStefan Brüns			dma-requests = <27>;
338c32637e0SStefan Brüns			resets = <&ccu RST_BUS_DMA>;
339c32637e0SStefan Brüns			#dma-cells = <1>;
340c32637e0SStefan Brüns		};
341c32637e0SStefan Brüns
342e85f28e0SJagan Teki		tcon0: lcd-controller@1c0c000 {
343e85f28e0SJagan Teki			compatible = "allwinner,sun50i-a64-tcon-lcd",
344e85f28e0SJagan Teki				     "allwinner,sun8i-a83t-tcon-lcd";
345e85f28e0SJagan Teki			reg = <0x01c0c000 0x1000>;
346e85f28e0SJagan Teki			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
347e85f28e0SJagan Teki			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
348e85f28e0SJagan Teki			clock-names = "ahb", "tcon-ch0";
349e85f28e0SJagan Teki			clock-output-names = "tcon-pixel-clock";
35026c609d5SMaxime Ripard			#clock-cells = <0>;
351e85f28e0SJagan Teki			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
352e85f28e0SJagan Teki			reset-names = "lcd", "lvds";
353e85f28e0SJagan Teki
354e85f28e0SJagan Teki			ports {
355e85f28e0SJagan Teki				#address-cells = <1>;
356e85f28e0SJagan Teki				#size-cells = <0>;
357e85f28e0SJagan Teki
358e85f28e0SJagan Teki				tcon0_in: port@0 {
359e85f28e0SJagan Teki					#address-cells = <1>;
360e85f28e0SJagan Teki					#size-cells = <0>;
361e85f28e0SJagan Teki					reg = <0>;
362e85f28e0SJagan Teki
363e85f28e0SJagan Teki					tcon0_in_mixer0: endpoint@0 {
364e85f28e0SJagan Teki						reg = <0>;
365e85f28e0SJagan Teki						remote-endpoint = <&mixer0_out_tcon0>;
366e85f28e0SJagan Teki					};
367a7f7047fSMaxime Ripard
368a7f7047fSMaxime Ripard					tcon0_in_mixer1: endpoint@1 {
369a7f7047fSMaxime Ripard						reg = <1>;
370d41a43a0SMaxime Ripard						remote-endpoint = <&mixer1_out_tcon0>;
371a7f7047fSMaxime Ripard					};
372e85f28e0SJagan Teki				};
373e85f28e0SJagan Teki
374e85f28e0SJagan Teki				tcon0_out: port@1 {
375e85f28e0SJagan Teki					#address-cells = <1>;
376e85f28e0SJagan Teki					#size-cells = <0>;
377e85f28e0SJagan Teki					reg = <1>;
37816c8ff57SJagan Teki
37916c8ff57SJagan Teki					tcon0_out_dsi: endpoint@1 {
38016c8ff57SJagan Teki						reg = <1>;
38116c8ff57SJagan Teki						remote-endpoint = <&dsi_in_tcon0>;
38216c8ff57SJagan Teki						allwinner,tcon-channel = <1>;
38316c8ff57SJagan Teki					};
384e85f28e0SJagan Teki				};
385e85f28e0SJagan Teki			};
386e85f28e0SJagan Teki		};
387e85f28e0SJagan Teki
388e85f28e0SJagan Teki		tcon1: lcd-controller@1c0d000 {
389e85f28e0SJagan Teki			compatible = "allwinner,sun50i-a64-tcon-tv",
390e85f28e0SJagan Teki				     "allwinner,sun8i-a83t-tcon-tv";
391e85f28e0SJagan Teki			reg = <0x01c0d000 0x1000>;
392e85f28e0SJagan Teki			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
393e85f28e0SJagan Teki			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
394e85f28e0SJagan Teki			clock-names = "ahb", "tcon-ch1";
395e85f28e0SJagan Teki			resets = <&ccu RST_BUS_TCON1>;
396e85f28e0SJagan Teki			reset-names = "lcd";
397e85f28e0SJagan Teki
398e85f28e0SJagan Teki			ports {
399e85f28e0SJagan Teki				#address-cells = <1>;
400e85f28e0SJagan Teki				#size-cells = <0>;
401e85f28e0SJagan Teki
402e85f28e0SJagan Teki				tcon1_in: port@0 {
403a7f7047fSMaxime Ripard					#address-cells = <1>;
404a7f7047fSMaxime Ripard					#size-cells = <0>;
405e85f28e0SJagan Teki					reg = <0>;
406e85f28e0SJagan Teki
407a7f7047fSMaxime Ripard					tcon1_in_mixer0: endpoint@0 {
408a7f7047fSMaxime Ripard						reg = <0>;
409a7f7047fSMaxime Ripard						remote-endpoint = <&mixer0_out_tcon1>;
410a7f7047fSMaxime Ripard					};
411a7f7047fSMaxime Ripard
412a7f7047fSMaxime Ripard					tcon1_in_mixer1: endpoint@1 {
413a7f7047fSMaxime Ripard						reg = <1>;
414e85f28e0SJagan Teki						remote-endpoint = <&mixer1_out_tcon1>;
415e85f28e0SJagan Teki					};
416e85f28e0SJagan Teki				};
417e85f28e0SJagan Teki
418e85f28e0SJagan Teki				tcon1_out: port@1 {
419e85f28e0SJagan Teki					#address-cells = <1>;
420e85f28e0SJagan Teki					#size-cells = <0>;
421e85f28e0SJagan Teki					reg = <1>;
422e85f28e0SJagan Teki
423e85f28e0SJagan Teki					tcon1_out_hdmi: endpoint@1 {
424e85f28e0SJagan Teki						reg = <1>;
425e85f28e0SJagan Teki						remote-endpoint = <&hdmi_in_tcon1>;
426e85f28e0SJagan Teki					};
427e85f28e0SJagan Teki				};
428e85f28e0SJagan Teki			};
429e85f28e0SJagan Teki		};
430e85f28e0SJagan Teki
431d60ce247SPaul Kocialkowski		video-codec@1c0e000 {
4324ab88516SPaul Kocialkowski			compatible = "allwinner,sun50i-a64-video-engine";
433d60ce247SPaul Kocialkowski			reg = <0x01c0e000 0x1000>;
434d60ce247SPaul Kocialkowski			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
435d60ce247SPaul Kocialkowski				 <&ccu CLK_DRAM_VE>;
436d60ce247SPaul Kocialkowski			clock-names = "ahb", "mod", "ram";
437d60ce247SPaul Kocialkowski			resets = <&ccu RST_BUS_VE>;
438d60ce247SPaul Kocialkowski			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
439d60ce247SPaul Kocialkowski			allwinner,sram = <&ve_sram 1>;
440d60ce247SPaul Kocialkowski		};
441d60ce247SPaul Kocialkowski
442f3dff347SAndre Przywara		mmc0: mmc@1c0f000 {
443f3dff347SAndre Przywara			compatible = "allwinner,sun50i-a64-mmc";
444f3dff347SAndre Przywara			reg = <0x01c0f000 0x1000>;
445f3dff347SAndre Przywara			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
446f3dff347SAndre Przywara			clock-names = "ahb", "mmc";
447f3dff347SAndre Przywara			resets = <&ccu RST_BUS_MMC0>;
448f3dff347SAndre Przywara			reset-names = "ahb";
449f3dff347SAndre Przywara			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
45022be992fSMaxime Ripard			max-frequency = <150000000>;
451f3dff347SAndre Przywara			status = "disabled";
452f3dff347SAndre Przywara			#address-cells = <1>;
453f3dff347SAndre Przywara			#size-cells = <0>;
454f3dff347SAndre Przywara		};
455f3dff347SAndre Przywara
456f3dff347SAndre Przywara		mmc1: mmc@1c10000 {
457f3dff347SAndre Przywara			compatible = "allwinner,sun50i-a64-mmc";
458f3dff347SAndre Przywara			reg = <0x01c10000 0x1000>;
459f3dff347SAndre Przywara			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
460f3dff347SAndre Przywara			clock-names = "ahb", "mmc";
461f3dff347SAndre Przywara			resets = <&ccu RST_BUS_MMC1>;
462f3dff347SAndre Przywara			reset-names = "ahb";
463f3dff347SAndre Przywara			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
46422be992fSMaxime Ripard			max-frequency = <150000000>;
465f3dff347SAndre Przywara			status = "disabled";
466f3dff347SAndre Przywara			#address-cells = <1>;
467f3dff347SAndre Przywara			#size-cells = <0>;
468f3dff347SAndre Przywara		};
469f3dff347SAndre Przywara
470f3dff347SAndre Przywara		mmc2: mmc@1c11000 {
471f3dff347SAndre Przywara			compatible = "allwinner,sun50i-a64-emmc";
472f3dff347SAndre Przywara			reg = <0x01c11000 0x1000>;
473f3dff347SAndre Przywara			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
474f3dff347SAndre Przywara			clock-names = "ahb", "mmc";
475f3dff347SAndre Przywara			resets = <&ccu RST_BUS_MMC2>;
476f3dff347SAndre Przywara			reset-names = "ahb";
477f3dff347SAndre Przywara			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
47822be992fSMaxime Ripard			max-frequency = <200000000>;
479f3dff347SAndre Przywara			status = "disabled";
480f3dff347SAndre Przywara			#address-cells = <1>;
481f3dff347SAndre Przywara			#size-cells = <0>;
482f3dff347SAndre Przywara		};
483f3dff347SAndre Przywara
484ac947b17SEmmanuel Vadot		sid: eeprom@1c14000 {
485ac947b17SEmmanuel Vadot			compatible = "allwinner,sun50i-a64-sid";
486ac947b17SEmmanuel Vadot			reg = <0x1c14000 0x400>;
48759f5e9b9SVasily Khoruzhick			#address-cells = <1>;
48859f5e9b9SVasily Khoruzhick			#size-cells = <1>;
48959f5e9b9SVasily Khoruzhick
49059f5e9b9SVasily Khoruzhick			ths_calibration: thermal-sensor-calibration@34 {
49159f5e9b9SVasily Khoruzhick				reg = <0x34 0x8>;
49259f5e9b9SVasily Khoruzhick			};
493ac947b17SEmmanuel Vadot		};
494ac947b17SEmmanuel Vadot
4950f5fc158SCorentin Labbe		crypto: crypto@1c15000 {
4960f5fc158SCorentin Labbe			compatible = "allwinner,sun50i-a64-crypto";
4970f5fc158SCorentin Labbe			reg = <0x01c15000 0x1000>;
4980f5fc158SCorentin Labbe			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
4990f5fc158SCorentin Labbe			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
5000f5fc158SCorentin Labbe			clock-names = "bus", "mod";
5010f5fc158SCorentin Labbe			resets = <&ccu RST_BUS_CE>;
5020f5fc158SCorentin Labbe		};
5030f5fc158SCorentin Labbe
504d6c9da12SCorentin LABBE		usb_otg: usb@1c19000 {
505972a3ecdSIcenowy Zheng			compatible = "allwinner,sun8i-a33-musb";
506972a3ecdSIcenowy Zheng			reg = <0x01c19000 0x0400>;
507972a3ecdSIcenowy Zheng			clocks = <&ccu CLK_BUS_OTG>;
508972a3ecdSIcenowy Zheng			resets = <&ccu RST_BUS_OTG>;
509972a3ecdSIcenowy Zheng			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
510972a3ecdSIcenowy Zheng			interrupt-names = "mc";
511972a3ecdSIcenowy Zheng			phys = <&usbphy 0>;
512972a3ecdSIcenowy Zheng			phy-names = "usb";
513972a3ecdSIcenowy Zheng			extcon = <&usbphy 0>;
5140973c06bSMaxime Ripard			dr_mode = "otg";
515972a3ecdSIcenowy Zheng			status = "disabled";
516972a3ecdSIcenowy Zheng		};
517972a3ecdSIcenowy Zheng
518d6c9da12SCorentin LABBE		usbphy: phy@1c19400 {
519a004ee35SIcenowy Zheng			compatible = "allwinner,sun50i-a64-usb-phy";
520a004ee35SIcenowy Zheng			reg = <0x01c19400 0x14>,
5210d984797SIcenowy Zheng			      <0x01c1a800 0x4>,
522a004ee35SIcenowy Zheng			      <0x01c1b800 0x4>;
523a004ee35SIcenowy Zheng			reg-names = "phy_ctrl",
5240d984797SIcenowy Zheng				    "pmu0",
525a004ee35SIcenowy Zheng				    "pmu1";
526a004ee35SIcenowy Zheng			clocks = <&ccu CLK_USB_PHY0>,
527a004ee35SIcenowy Zheng				 <&ccu CLK_USB_PHY1>;
528a004ee35SIcenowy Zheng			clock-names = "usb0_phy",
529a004ee35SIcenowy Zheng				      "usb1_phy";
530a004ee35SIcenowy Zheng			resets = <&ccu RST_USB_PHY0>,
531a004ee35SIcenowy Zheng				 <&ccu RST_USB_PHY1>;
532a004ee35SIcenowy Zheng			reset-names = "usb0_reset",
533a004ee35SIcenowy Zheng				      "usb1_reset";
534a004ee35SIcenowy Zheng			status = "disabled";
535a004ee35SIcenowy Zheng			#phy-cells = <1>;
536a004ee35SIcenowy Zheng		};
537a004ee35SIcenowy Zheng
538d6c9da12SCorentin LABBE		ehci0: usb@1c1a000 {
539dc03a047SIcenowy Zheng			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
540dc03a047SIcenowy Zheng			reg = <0x01c1a000 0x100>;
541dc03a047SIcenowy Zheng			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
542dc03a047SIcenowy Zheng			clocks = <&ccu CLK_BUS_OHCI0>,
543dc03a047SIcenowy Zheng				 <&ccu CLK_BUS_EHCI0>,
544dc03a047SIcenowy Zheng				 <&ccu CLK_USB_OHCI0>;
545dc03a047SIcenowy Zheng			resets = <&ccu RST_BUS_OHCI0>,
546dc03a047SIcenowy Zheng				 <&ccu RST_BUS_EHCI0>;
547dc03a047SIcenowy Zheng			status = "disabled";
548dc03a047SIcenowy Zheng		};
549dc03a047SIcenowy Zheng
550d6c9da12SCorentin LABBE		ohci0: usb@1c1a400 {
551dc03a047SIcenowy Zheng			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
552dc03a047SIcenowy Zheng			reg = <0x01c1a400 0x100>;
553dc03a047SIcenowy Zheng			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
554dc03a047SIcenowy Zheng			clocks = <&ccu CLK_BUS_OHCI0>,
555dc03a047SIcenowy Zheng				 <&ccu CLK_USB_OHCI0>;
556dc03a047SIcenowy Zheng			resets = <&ccu RST_BUS_OHCI0>;
557dc03a047SIcenowy Zheng			status = "disabled";
558dc03a047SIcenowy Zheng		};
559dc03a047SIcenowy Zheng
560d6c9da12SCorentin LABBE		ehci1: usb@1c1b000 {
561a004ee35SIcenowy Zheng			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
562a004ee35SIcenowy Zheng			reg = <0x01c1b000 0x100>;
563a004ee35SIcenowy Zheng			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
564a004ee35SIcenowy Zheng			clocks = <&ccu CLK_BUS_OHCI1>,
565a004ee35SIcenowy Zheng				 <&ccu CLK_BUS_EHCI1>,
566a004ee35SIcenowy Zheng				 <&ccu CLK_USB_OHCI1>;
567a004ee35SIcenowy Zheng			resets = <&ccu RST_BUS_OHCI1>,
568a004ee35SIcenowy Zheng				 <&ccu RST_BUS_EHCI1>;
569a004ee35SIcenowy Zheng			phys = <&usbphy 1>;
570e6064cf4SMaxime Ripard			phy-names = "usb";
571a004ee35SIcenowy Zheng			status = "disabled";
572a004ee35SIcenowy Zheng		};
573a004ee35SIcenowy Zheng
574d6c9da12SCorentin LABBE		ohci1: usb@1c1b400 {
575a004ee35SIcenowy Zheng			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
576a004ee35SIcenowy Zheng			reg = <0x01c1b400 0x100>;
577a004ee35SIcenowy Zheng			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
578a004ee35SIcenowy Zheng			clocks = <&ccu CLK_BUS_OHCI1>,
579a004ee35SIcenowy Zheng				 <&ccu CLK_USB_OHCI1>;
580a004ee35SIcenowy Zheng			resets = <&ccu RST_BUS_OHCI1>;
581a004ee35SIcenowy Zheng			phys = <&usbphy 1>;
582e6064cf4SMaxime Ripard			phy-names = "usb";
583a004ee35SIcenowy Zheng			status = "disabled";
584a004ee35SIcenowy Zheng		};
585a004ee35SIcenowy Zheng
586d6c9da12SCorentin LABBE		ccu: clock@1c20000 {
5876bc37facSAndre Przywara			compatible = "allwinner,sun50i-a64-ccu";
5886bc37facSAndre Przywara			reg = <0x01c20000 0x400>;
58944ff3cafSChen-Yu Tsai			clocks = <&osc24M>, <&rtc 0>;
5906bc37facSAndre Przywara			clock-names = "hosc", "losc";
5916bc37facSAndre Przywara			#clock-cells = <1>;
5926bc37facSAndre Przywara			#reset-cells = <1>;
5936bc37facSAndre Przywara		};
5946bc37facSAndre Przywara
5956bc37facSAndre Przywara		pio: pinctrl@1c20800 {
5966bc37facSAndre Przywara			compatible = "allwinner,sun50i-a64-pinctrl";
5976bc37facSAndre Przywara			reg = <0x01c20800 0x400>;
5986bc37facSAndre Przywara			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
5996bc37facSAndre Przywara				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
6006bc37facSAndre Przywara				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
601b71818cbSChen-Yu Tsai			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
602562bf196SMaxime Ripard			clock-names = "apb", "hosc", "losc";
6036bc37facSAndre Przywara			gpio-controller;
6046bc37facSAndre Przywara			#gpio-cells = <3>;
6056bc37facSAndre Przywara			interrupt-controller;
6066bc37facSAndre Przywara			#interrupt-cells = <3>;
6076bc37facSAndre Przywara
608ff29f13eSJagan Teki			csi_pins: csi-pins {
609ff29f13eSJagan Teki				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
610ff29f13eSJagan Teki				       "PE7", "PE8", "PE9", "PE10", "PE11";
611ff29f13eSJagan Teki				function = "csi";
612ff29f13eSJagan Teki			};
613ff29f13eSJagan Teki
614f7056b28SJagan Teki			/omit-if-no-ref/
615f7056b28SJagan Teki			csi_mclk_pin: csi-mclk-pin {
616f7056b28SJagan Teki				pins = "PE1";
617f7056b28SJagan Teki				function = "csi";
618f7056b28SJagan Teki			};
619f7056b28SJagan Teki
62054eac67bSMaxime Ripard			i2c0_pins: i2c0-pins {
62111239fe6SHarald Geyer				pins = "PH0", "PH1";
62211239fe6SHarald Geyer				function = "i2c0";
62311239fe6SHarald Geyer			};
62411239fe6SHarald Geyer
62554eac67bSMaxime Ripard			i2c1_pins: i2c1-pins {
6266bc37facSAndre Przywara				pins = "PH2", "PH3";
6276bc37facSAndre Przywara				function = "i2c1";
6286bc37facSAndre Przywara			};
6296bc37facSAndre Przywara
630c478a12eSIcenowy Zheng			/omit-if-no-ref/
631c478a12eSIcenowy Zheng			lcd_rgb666_pins: lcd-rgb666-pins {
632c478a12eSIcenowy Zheng				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
633c478a12eSIcenowy Zheng				       "PD5", "PD6", "PD7", "PD8", "PD9",
634c478a12eSIcenowy Zheng				       "PD10", "PD11", "PD12", "PD13",
635c478a12eSIcenowy Zheng				       "PD14", "PD15", "PD16", "PD17",
636c478a12eSIcenowy Zheng				       "PD18", "PD19", "PD20", "PD21";
637c478a12eSIcenowy Zheng				function = "lcd0";
638c478a12eSIcenowy Zheng			};
639c478a12eSIcenowy Zheng
640a3e8f492SMaxime Ripard			mmc0_pins: mmc0-pins {
641a3e8f492SMaxime Ripard				pins = "PF0", "PF1", "PF2", "PF3",
642a3e8f492SMaxime Ripard				       "PF4", "PF5";
643a3e8f492SMaxime Ripard				function = "mmc0";
644a3e8f492SMaxime Ripard				drive-strength = <30>;
645a3e8f492SMaxime Ripard				bias-pull-up;
646a3e8f492SMaxime Ripard			};
647a3e8f492SMaxime Ripard
648a3e8f492SMaxime Ripard			mmc1_pins: mmc1-pins {
649a3e8f492SMaxime Ripard				pins = "PG0", "PG1", "PG2", "PG3",
650a3e8f492SMaxime Ripard				       "PG4", "PG5";
651a3e8f492SMaxime Ripard				function = "mmc1";
652a3e8f492SMaxime Ripard				drive-strength = <30>;
653a3e8f492SMaxime Ripard				bias-pull-up;
654a3e8f492SMaxime Ripard			};
655a3e8f492SMaxime Ripard
656a3e8f492SMaxime Ripard			mmc2_pins: mmc2-pins {
657fa59dd2eSChen-Yu Tsai				pins = "PC5", "PC6", "PC8", "PC9",
658a3e8f492SMaxime Ripard				       "PC10","PC11", "PC12", "PC13",
659a3e8f492SMaxime Ripard				       "PC14", "PC15", "PC16";
660a3e8f492SMaxime Ripard				function = "mmc2";
661a3e8f492SMaxime Ripard				drive-strength = <30>;
662a3e8f492SMaxime Ripard				bias-pull-up;
663a3e8f492SMaxime Ripard			};
664a3e8f492SMaxime Ripard
665fa59dd2eSChen-Yu Tsai			mmc2_ds_pin: mmc2-ds-pin {
666fa59dd2eSChen-Yu Tsai				pins = "PC1";
667fa59dd2eSChen-Yu Tsai				function = "mmc2";
668fa59dd2eSChen-Yu Tsai				drive-strength = <30>;
669fa59dd2eSChen-Yu Tsai				bias-pull-up;
670fa59dd2eSChen-Yu Tsai			};
671fa59dd2eSChen-Yu Tsai
67254eac67bSMaxime Ripard			pwm_pin: pwm-pin {
673b5df280bSAndre Przywara				pins = "PD22";
674b5df280bSAndre Przywara				function = "pwm";
675b5df280bSAndre Przywara			};
676b5df280bSAndre Przywara
67754eac67bSMaxime Ripard			rmii_pins: rmii-pins {
678e53f67e9SCorentin Labbe				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
679e53f67e9SCorentin Labbe				       "PD18", "PD19", "PD20", "PD22", "PD23";
680e53f67e9SCorentin Labbe				function = "emac";
681e53f67e9SCorentin Labbe				drive-strength = <40>;
682e53f67e9SCorentin Labbe			};
683e53f67e9SCorentin Labbe
68454eac67bSMaxime Ripard			rgmii_pins: rgmii-pins {
685e53f67e9SCorentin Labbe				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
686e53f67e9SCorentin Labbe				       "PD13", "PD15", "PD16", "PD17", "PD18",
687e53f67e9SCorentin Labbe				       "PD19", "PD20", "PD21", "PD22", "PD23";
688e53f67e9SCorentin Labbe				function = "emac";
689e53f67e9SCorentin Labbe				drive-strength = <40>;
690e53f67e9SCorentin Labbe			};
691e53f67e9SCorentin Labbe
69254eac67bSMaxime Ripard			spdif_tx_pin: spdif-tx-pin {
693b399d2acSMarcus Cooper				pins = "PH8";
694b399d2acSMarcus Cooper				function = "spdif";
695b399d2acSMarcus Cooper			};
696b399d2acSMarcus Cooper
69754eac67bSMaxime Ripard			spi0_pins: spi0-pins {
698b518bb15SStefan Brüns				pins = "PC0", "PC1", "PC2", "PC3";
699b518bb15SStefan Brüns				function = "spi0";
700b518bb15SStefan Brüns			};
701b518bb15SStefan Brüns
70254eac67bSMaxime Ripard			spi1_pins: spi1-pins {
703b518bb15SStefan Brüns				pins = "PD0", "PD1", "PD2", "PD3";
704b518bb15SStefan Brüns				function = "spi1";
705b518bb15SStefan Brüns			};
706b518bb15SStefan Brüns
707d91ebb95SChen-Yu Tsai			uart0_pb_pins: uart0-pb-pins {
7086bc37facSAndre Przywara				pins = "PB8", "PB9";
7096bc37facSAndre Przywara				function = "uart0";
7106bc37facSAndre Przywara			};
711e7ba733dSAndre Przywara
71254eac67bSMaxime Ripard			uart1_pins: uart1-pins {
713e7ba733dSAndre Przywara				pins = "PG6", "PG7";
714e7ba733dSAndre Przywara				function = "uart1";
715e7ba733dSAndre Przywara			};
716e7ba733dSAndre Przywara
71754eac67bSMaxime Ripard			uart1_rts_cts_pins: uart1-rts-cts-pins {
718e7ba733dSAndre Przywara				pins = "PG8", "PG9";
719e7ba733dSAndre Przywara				function = "uart1";
720e7ba733dSAndre Przywara			};
72179825719SAndreas Färber
72279825719SAndreas Färber			uart2_pins: uart2-pins {
72379825719SAndreas Färber				pins = "PB0", "PB1";
72479825719SAndreas Färber				function = "uart2";
72579825719SAndreas Färber			};
7262273aa16SAndreas Färber
7272273aa16SAndreas Färber			uart3_pins: uart3-pins {
7282273aa16SAndreas Färber				pins = "PD0", "PD1";
7292273aa16SAndreas Färber				function = "uart3";
7302273aa16SAndreas Färber			};
7312273aa16SAndreas Färber
7322273aa16SAndreas Färber			uart4_pins: uart4-pins {
7332273aa16SAndreas Färber				pins = "PD2", "PD3";
7342273aa16SAndreas Färber				function = "uart4";
7352273aa16SAndreas Färber			};
7362273aa16SAndreas Färber
7372273aa16SAndreas Färber			uart4_rts_cts_pins: uart4-rts-cts-pins {
7382273aa16SAndreas Färber				pins = "PD4", "PD5";
7392273aa16SAndreas Färber				function = "uart4";
7402273aa16SAndreas Färber			};
7416bc37facSAndre Przywara		};
7426bc37facSAndre Przywara
743b399d2acSMarcus Cooper		spdif: spdif@1c21000 {
744b399d2acSMarcus Cooper			#sound-dai-cells = <0>;
745b399d2acSMarcus Cooper			compatible = "allwinner,sun50i-a64-spdif",
746b399d2acSMarcus Cooper				     "allwinner,sun8i-h3-spdif";
747b399d2acSMarcus Cooper			reg = <0x01c21000 0x400>;
748b399d2acSMarcus Cooper			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
749b399d2acSMarcus Cooper			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
750b399d2acSMarcus Cooper			resets = <&ccu RST_BUS_SPDIF>;
751b399d2acSMarcus Cooper			clock-names = "apb", "spdif";
752b399d2acSMarcus Cooper			dmas = <&dma 2>;
753b399d2acSMarcus Cooper			dma-names = "tx";
754b399d2acSMarcus Cooper			pinctrl-names = "default";
755b399d2acSMarcus Cooper			pinctrl-0 = <&spdif_tx_pin>;
756b399d2acSMarcus Cooper			status = "disabled";
757b399d2acSMarcus Cooper		};
758b399d2acSMarcus Cooper
75984204fb6SLuca Weiss		lradc: lradc@1c21800 {
76084204fb6SLuca Weiss			compatible = "allwinner,sun50i-a64-lradc",
76184204fb6SLuca Weiss				     "allwinner,sun8i-a83t-r-lradc";
76284204fb6SLuca Weiss			reg = <0x01c21800 0x400>;
76384204fb6SLuca Weiss			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
76484204fb6SLuca Weiss			status = "disabled";
76584204fb6SLuca Weiss		};
76684204fb6SLuca Weiss
7671c92c009SMarcus Cooper		i2s0: i2s@1c22000 {
7681c92c009SMarcus Cooper			#sound-dai-cells = <0>;
7691c92c009SMarcus Cooper			compatible = "allwinner,sun50i-a64-i2s",
7701c92c009SMarcus Cooper				     "allwinner,sun8i-h3-i2s";
7711c92c009SMarcus Cooper			reg = <0x01c22000 0x400>;
7721c92c009SMarcus Cooper			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
7731c92c009SMarcus Cooper			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
7741c92c009SMarcus Cooper			clock-names = "apb", "mod";
7751c92c009SMarcus Cooper			resets = <&ccu RST_BUS_I2S0>;
7761c92c009SMarcus Cooper			dma-names = "rx", "tx";
7771c92c009SMarcus Cooper			dmas = <&dma 3>, <&dma 3>;
7781c92c009SMarcus Cooper			status = "disabled";
7791c92c009SMarcus Cooper		};
7801c92c009SMarcus Cooper
7811c92c009SMarcus Cooper		i2s1: i2s@1c22400 {
7821c92c009SMarcus Cooper			#sound-dai-cells = <0>;
7831c92c009SMarcus Cooper			compatible = "allwinner,sun50i-a64-i2s",
7841c92c009SMarcus Cooper				     "allwinner,sun8i-h3-i2s";
7851c92c009SMarcus Cooper			reg = <0x01c22400 0x400>;
7861c92c009SMarcus Cooper			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
7871c92c009SMarcus Cooper			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
7881c92c009SMarcus Cooper			clock-names = "apb", "mod";
7891c92c009SMarcus Cooper			resets = <&ccu RST_BUS_I2S1>;
7901c92c009SMarcus Cooper			dma-names = "rx", "tx";
7911c92c009SMarcus Cooper			dmas = <&dma 4>, <&dma 4>;
7921c92c009SMarcus Cooper			status = "disabled";
7931c92c009SMarcus Cooper		};
7941c92c009SMarcus Cooper
795ec4a9540SVasily Khoruzhick		dai: dai@1c22c00 {
796ec4a9540SVasily Khoruzhick			#sound-dai-cells = <0>;
797ec4a9540SVasily Khoruzhick			compatible = "allwinner,sun50i-a64-codec-i2s";
798ec4a9540SVasily Khoruzhick			reg = <0x01c22c00 0x200>;
799ec4a9540SVasily Khoruzhick			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
800ec4a9540SVasily Khoruzhick			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
801ec4a9540SVasily Khoruzhick			clock-names = "apb", "mod";
802ec4a9540SVasily Khoruzhick			resets = <&ccu RST_BUS_CODEC>;
803ec4a9540SVasily Khoruzhick			dmas = <&dma 15>, <&dma 15>;
804ec4a9540SVasily Khoruzhick			dma-names = "rx", "tx";
805ec4a9540SVasily Khoruzhick			status = "disabled";
806ec4a9540SVasily Khoruzhick		};
807ec4a9540SVasily Khoruzhick
808ec4a9540SVasily Khoruzhick		codec: codec@1c22e00 {
809ec4a9540SVasily Khoruzhick			#sound-dai-cells = <0>;
810ec4a9540SVasily Khoruzhick			compatible = "allwinner,sun8i-a33-codec";
811ec4a9540SVasily Khoruzhick			reg = <0x01c22e00 0x600>;
812ec4a9540SVasily Khoruzhick			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
813ec4a9540SVasily Khoruzhick			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
814ec4a9540SVasily Khoruzhick			clock-names = "bus", "mod";
815ec4a9540SVasily Khoruzhick			status = "disabled";
816ec4a9540SVasily Khoruzhick		};
817ec4a9540SVasily Khoruzhick
81859f5e9b9SVasily Khoruzhick		ths: thermal-sensor@1c25000 {
81959f5e9b9SVasily Khoruzhick			compatible = "allwinner,sun50i-a64-ths";
82059f5e9b9SVasily Khoruzhick			reg = <0x01c25000 0x100>;
82159f5e9b9SVasily Khoruzhick			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
82259f5e9b9SVasily Khoruzhick			clock-names = "bus", "mod";
82359f5e9b9SVasily Khoruzhick			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
82459f5e9b9SVasily Khoruzhick			resets = <&ccu RST_BUS_THS>;
82559f5e9b9SVasily Khoruzhick			nvmem-cells = <&ths_calibration>;
82659f5e9b9SVasily Khoruzhick			nvmem-cell-names = "calibration";
82759f5e9b9SVasily Khoruzhick			#thermal-sensor-cells = <1>;
82859f5e9b9SVasily Khoruzhick		};
82959f5e9b9SVasily Khoruzhick
8306bc37facSAndre Przywara		uart0: serial@1c28000 {
8316bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
8326bc37facSAndre Przywara			reg = <0x01c28000 0x400>;
8336bc37facSAndre Przywara			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
8346bc37facSAndre Przywara			reg-shift = <2>;
8356bc37facSAndre Przywara			reg-io-width = <4>;
836494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART0>;
837494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART0>;
8386bc37facSAndre Przywara			status = "disabled";
8396bc37facSAndre Przywara		};
8406bc37facSAndre Przywara
8416bc37facSAndre Przywara		uart1: serial@1c28400 {
8426bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
8436bc37facSAndre Przywara			reg = <0x01c28400 0x400>;
8446bc37facSAndre Przywara			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
8456bc37facSAndre Przywara			reg-shift = <2>;
8466bc37facSAndre Przywara			reg-io-width = <4>;
847494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART1>;
848494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART1>;
8496bc37facSAndre Przywara			status = "disabled";
8506bc37facSAndre Przywara		};
8516bc37facSAndre Przywara
8526bc37facSAndre Przywara		uart2: serial@1c28800 {
8536bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
8546bc37facSAndre Przywara			reg = <0x01c28800 0x400>;
8556bc37facSAndre Przywara			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
8566bc37facSAndre Przywara			reg-shift = <2>;
8576bc37facSAndre Przywara			reg-io-width = <4>;
858494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART2>;
859494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART2>;
8606bc37facSAndre Przywara			status = "disabled";
8616bc37facSAndre Przywara		};
8626bc37facSAndre Przywara
8636bc37facSAndre Przywara		uart3: serial@1c28c00 {
8646bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
8656bc37facSAndre Przywara			reg = <0x01c28c00 0x400>;
8666bc37facSAndre Przywara			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
8676bc37facSAndre Przywara			reg-shift = <2>;
8686bc37facSAndre Przywara			reg-io-width = <4>;
869494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART3>;
870494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART3>;
8716bc37facSAndre Przywara			status = "disabled";
8726bc37facSAndre Przywara		};
8736bc37facSAndre Przywara
8746bc37facSAndre Przywara		uart4: serial@1c29000 {
8756bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
8766bc37facSAndre Przywara			reg = <0x01c29000 0x400>;
8776bc37facSAndre Przywara			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
8786bc37facSAndre Przywara			reg-shift = <2>;
8796bc37facSAndre Przywara			reg-io-width = <4>;
880494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART4>;
881494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART4>;
8826bc37facSAndre Przywara			status = "disabled";
8836bc37facSAndre Przywara		};
8846bc37facSAndre Przywara
8856bc37facSAndre Przywara		i2c0: i2c@1c2ac00 {
8866bc37facSAndre Przywara			compatible = "allwinner,sun6i-a31-i2c";
8876bc37facSAndre Przywara			reg = <0x01c2ac00 0x400>;
8886bc37facSAndre Przywara			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
889494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_I2C0>;
890494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_I2C0>;
89170f76289SJagan Teki			pinctrl-names = "default";
89270f76289SJagan Teki			pinctrl-0 = <&i2c0_pins>;
8936bc37facSAndre Przywara			status = "disabled";
8946bc37facSAndre Przywara			#address-cells = <1>;
8956bc37facSAndre Przywara			#size-cells = <0>;
8966bc37facSAndre Przywara		};
8976bc37facSAndre Przywara
8986bc37facSAndre Przywara		i2c1: i2c@1c2b000 {
8996bc37facSAndre Przywara			compatible = "allwinner,sun6i-a31-i2c";
9006bc37facSAndre Przywara			reg = <0x01c2b000 0x400>;
9016bc37facSAndre Przywara			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
902494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_I2C1>;
903494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_I2C1>;
90470f76289SJagan Teki			pinctrl-names = "default";
90570f76289SJagan Teki			pinctrl-0 = <&i2c1_pins>;
9066bc37facSAndre Przywara			status = "disabled";
9076bc37facSAndre Przywara			#address-cells = <1>;
9086bc37facSAndre Przywara			#size-cells = <0>;
9096bc37facSAndre Przywara		};
9106bc37facSAndre Przywara
9116bc37facSAndre Przywara		i2c2: i2c@1c2b400 {
9126bc37facSAndre Przywara			compatible = "allwinner,sun6i-a31-i2c";
9136bc37facSAndre Przywara			reg = <0x01c2b400 0x400>;
9146bc37facSAndre Przywara			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
915494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_I2C2>;
916494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_I2C2>;
9176bc37facSAndre Przywara			status = "disabled";
9186bc37facSAndre Przywara			#address-cells = <1>;
9196bc37facSAndre Przywara			#size-cells = <0>;
9206bc37facSAndre Przywara		};
9216bc37facSAndre Przywara
922b518bb15SStefan Brüns
923d6c9da12SCorentin LABBE		spi0: spi@1c68000 {
924b518bb15SStefan Brüns			compatible = "allwinner,sun8i-h3-spi";
925b518bb15SStefan Brüns			reg = <0x01c68000 0x1000>;
926b518bb15SStefan Brüns			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
927b518bb15SStefan Brüns			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
928b518bb15SStefan Brüns			clock-names = "ahb", "mod";
92906c1258aSStefan Brüns			dmas = <&dma 23>, <&dma 23>;
93006c1258aSStefan Brüns			dma-names = "rx", "tx";
931b518bb15SStefan Brüns			pinctrl-names = "default";
932b518bb15SStefan Brüns			pinctrl-0 = <&spi0_pins>;
933b518bb15SStefan Brüns			resets = <&ccu RST_BUS_SPI0>;
934b518bb15SStefan Brüns			status = "disabled";
935b518bb15SStefan Brüns			num-cs = <1>;
936b518bb15SStefan Brüns			#address-cells = <1>;
937b518bb15SStefan Brüns			#size-cells = <0>;
938b518bb15SStefan Brüns		};
939b518bb15SStefan Brüns
940d6c9da12SCorentin LABBE		spi1: spi@1c69000 {
941b518bb15SStefan Brüns			compatible = "allwinner,sun8i-h3-spi";
942b518bb15SStefan Brüns			reg = <0x01c69000 0x1000>;
943b518bb15SStefan Brüns			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
944b518bb15SStefan Brüns			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
945b518bb15SStefan Brüns			clock-names = "ahb", "mod";
94606c1258aSStefan Brüns			dmas = <&dma 24>, <&dma 24>;
94706c1258aSStefan Brüns			dma-names = "rx", "tx";
948b518bb15SStefan Brüns			pinctrl-names = "default";
949b518bb15SStefan Brüns			pinctrl-0 = <&spi1_pins>;
950b518bb15SStefan Brüns			resets = <&ccu RST_BUS_SPI1>;
951b518bb15SStefan Brüns			status = "disabled";
952b518bb15SStefan Brüns			num-cs = <1>;
953b518bb15SStefan Brüns			#address-cells = <1>;
954b518bb15SStefan Brüns			#size-cells = <0>;
955b518bb15SStefan Brüns		};
956b518bb15SStefan Brüns
95794f44288SCorentin Labbe		emac: ethernet@1c30000 {
95894f44288SCorentin Labbe			compatible = "allwinner,sun50i-a64-emac";
95994f44288SCorentin Labbe			syscon = <&syscon>;
96094f44288SCorentin Labbe			reg = <0x01c30000 0x10000>;
96194f44288SCorentin Labbe			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
96294f44288SCorentin Labbe			interrupt-names = "macirq";
96394f44288SCorentin Labbe			resets = <&ccu RST_BUS_EMAC>;
96494f44288SCorentin Labbe			reset-names = "stmmaceth";
96594f44288SCorentin Labbe			clocks = <&ccu CLK_BUS_EMAC>;
96694f44288SCorentin Labbe			clock-names = "stmmaceth";
96794f44288SCorentin Labbe			status = "disabled";
96894f44288SCorentin Labbe
96994f44288SCorentin Labbe			mdio: mdio {
97016416084SCorentin Labbe				compatible = "snps,dwmac-mdio";
97194f44288SCorentin Labbe				#address-cells = <1>;
97294f44288SCorentin Labbe				#size-cells = <0>;
97394f44288SCorentin Labbe			};
97494f44288SCorentin Labbe		};
97594f44288SCorentin Labbe
9766b683d76SJagan Teki		mali: gpu@1c40000 {
9776b683d76SJagan Teki			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
9786b683d76SJagan Teki			reg = <0x01c40000 0x10000>;
9796b683d76SJagan Teki			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
9806b683d76SJagan Teki				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
9816b683d76SJagan Teki				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
9826b683d76SJagan Teki				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
9836b683d76SJagan Teki				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
9846b683d76SJagan Teki				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
9856b683d76SJagan Teki				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
9866b683d76SJagan Teki			interrupt-names = "gp",
9876b683d76SJagan Teki					  "gpmmu",
9886b683d76SJagan Teki					  "pp0",
9896b683d76SJagan Teki					  "ppmmu0",
9906b683d76SJagan Teki					  "pp1",
9916b683d76SJagan Teki					  "ppmmu1",
9926b683d76SJagan Teki					  "pmu";
9936b683d76SJagan Teki			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
9946b683d76SJagan Teki			clock-names = "bus", "core";
9956b683d76SJagan Teki			resets = <&ccu RST_BUS_GPU>;
9966b683d76SJagan Teki		};
9976b683d76SJagan Teki
9986bc37facSAndre Przywara		gic: interrupt-controller@1c81000 {
9996bc37facSAndre Przywara			compatible = "arm,gic-400";
10006bc37facSAndre Przywara			reg = <0x01c81000 0x1000>,
10016bc37facSAndre Przywara			      <0x01c82000 0x2000>,
10026bc37facSAndre Przywara			      <0x01c84000 0x2000>,
10036bc37facSAndre Przywara			      <0x01c86000 0x2000>;
10046bc37facSAndre Przywara			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
10056bc37facSAndre Przywara			interrupt-controller;
10066bc37facSAndre Przywara			#interrupt-cells = <3>;
10076bc37facSAndre Przywara		};
10086bc37facSAndre Przywara
1009b5df280bSAndre Przywara		pwm: pwm@1c21400 {
1010b5df280bSAndre Przywara			compatible = "allwinner,sun50i-a64-pwm",
1011b5df280bSAndre Przywara				     "allwinner,sun5i-a13-pwm";
1012b5df280bSAndre Przywara			reg = <0x01c21400 0x400>;
1013b5df280bSAndre Przywara			clocks = <&osc24M>;
1014b5df280bSAndre Przywara			pinctrl-names = "default";
1015b5df280bSAndre Przywara			pinctrl-0 = <&pwm_pin>;
1016b5df280bSAndre Przywara			#pwm-cells = <3>;
1017b5df280bSAndre Przywara			status = "disabled";
1018b5df280bSAndre Przywara		};
1019b5df280bSAndre Przywara
1020ff29f13eSJagan Teki		csi: csi@1cb0000 {
1021ff29f13eSJagan Teki			compatible = "allwinner,sun50i-a64-csi";
1022ff29f13eSJagan Teki			reg = <0x01cb0000 0x1000>;
1023ff29f13eSJagan Teki			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1024ff29f13eSJagan Teki			clocks = <&ccu CLK_BUS_CSI>,
1025ff29f13eSJagan Teki				 <&ccu CLK_CSI_SCLK>,
1026ff29f13eSJagan Teki				 <&ccu CLK_DRAM_CSI>;
1027ff29f13eSJagan Teki			clock-names = "bus", "mod", "ram";
1028ff29f13eSJagan Teki			resets = <&ccu RST_BUS_CSI>;
1029ff29f13eSJagan Teki			pinctrl-names = "default";
1030ff29f13eSJagan Teki			pinctrl-0 = <&csi_pins>;
1031ff29f13eSJagan Teki			status = "disabled";
1032ff29f13eSJagan Teki		};
1033ff29f13eSJagan Teki
103416c8ff57SJagan Teki		dsi: dsi@1ca0000 {
103516c8ff57SJagan Teki			compatible = "allwinner,sun50i-a64-mipi-dsi";
103616c8ff57SJagan Teki			reg = <0x01ca0000 0x1000>;
103716c8ff57SJagan Teki			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
103816c8ff57SJagan Teki			clocks = <&ccu CLK_BUS_MIPI_DSI>;
103916c8ff57SJagan Teki			resets = <&ccu RST_BUS_MIPI_DSI>;
104016c8ff57SJagan Teki			phys = <&dphy>;
104116c8ff57SJagan Teki			phy-names = "dphy";
104216c8ff57SJagan Teki			status = "disabled";
104316c8ff57SJagan Teki			#address-cells = <1>;
104416c8ff57SJagan Teki			#size-cells = <0>;
104516c8ff57SJagan Teki
104616c8ff57SJagan Teki			port {
104716c8ff57SJagan Teki				dsi_in_tcon0: endpoint {
104816c8ff57SJagan Teki					remote-endpoint = <&tcon0_out_dsi>;
104916c8ff57SJagan Teki				};
105016c8ff57SJagan Teki			};
105116c8ff57SJagan Teki		};
105216c8ff57SJagan Teki
105316c8ff57SJagan Teki		dphy: d-phy@1ca1000 {
105416c8ff57SJagan Teki			compatible = "allwinner,sun50i-a64-mipi-dphy",
105516c8ff57SJagan Teki				     "allwinner,sun6i-a31-mipi-dphy";
105616c8ff57SJagan Teki			reg = <0x01ca1000 0x1000>;
105716c8ff57SJagan Teki			clocks = <&ccu CLK_BUS_MIPI_DSI>,
105816c8ff57SJagan Teki				 <&ccu CLK_DSI_DPHY>;
105916c8ff57SJagan Teki			clock-names = "bus", "mod";
106016c8ff57SJagan Teki			resets = <&ccu RST_BUS_MIPI_DSI>;
106116c8ff57SJagan Teki			status = "disabled";
106216c8ff57SJagan Teki			#phy-cells = <0>;
106316c8ff57SJagan Teki		};
106416c8ff57SJagan Teki
1065e85f28e0SJagan Teki		hdmi: hdmi@1ee0000 {
1066e85f28e0SJagan Teki			compatible = "allwinner,sun50i-a64-dw-hdmi",
1067e85f28e0SJagan Teki				     "allwinner,sun8i-a83t-dw-hdmi";
1068e85f28e0SJagan Teki			reg = <0x01ee0000 0x10000>;
1069e85f28e0SJagan Teki			reg-io-width = <1>;
1070e85f28e0SJagan Teki			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1071e85f28e0SJagan Teki			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1072e85f28e0SJagan Teki				 <&ccu CLK_HDMI>;
1073e85f28e0SJagan Teki			clock-names = "iahb", "isfr", "tmds";
1074e85f28e0SJagan Teki			resets = <&ccu RST_BUS_HDMI1>;
1075e85f28e0SJagan Teki			reset-names = "ctrl";
1076e85f28e0SJagan Teki			phys = <&hdmi_phy>;
1077d40113fbSMaxime Ripard			phy-names = "phy";
1078e85f28e0SJagan Teki			status = "disabled";
1079e85f28e0SJagan Teki
1080e85f28e0SJagan Teki			ports {
1081e85f28e0SJagan Teki				#address-cells = <1>;
1082e85f28e0SJagan Teki				#size-cells = <0>;
1083e85f28e0SJagan Teki
1084e85f28e0SJagan Teki				hdmi_in: port@0 {
1085e85f28e0SJagan Teki					reg = <0>;
1086e85f28e0SJagan Teki
1087e85f28e0SJagan Teki					hdmi_in_tcon1: endpoint {
1088e85f28e0SJagan Teki						remote-endpoint = <&tcon1_out_hdmi>;
1089e85f28e0SJagan Teki					};
1090e85f28e0SJagan Teki				};
1091e85f28e0SJagan Teki
1092e85f28e0SJagan Teki				hdmi_out: port@1 {
1093e85f28e0SJagan Teki					reg = <1>;
1094e85f28e0SJagan Teki				};
1095e85f28e0SJagan Teki			};
1096e85f28e0SJagan Teki		};
1097e85f28e0SJagan Teki
1098e85f28e0SJagan Teki		hdmi_phy: hdmi-phy@1ef0000 {
1099e85f28e0SJagan Teki			compatible = "allwinner,sun50i-a64-hdmi-phy";
1100e85f28e0SJagan Teki			reg = <0x01ef0000 0x10000>;
1101e85f28e0SJagan Teki			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1102b71818cbSChen-Yu Tsai				 <&ccu CLK_PLL_VIDEO0>;
1103e85f28e0SJagan Teki			clock-names = "bus", "mod", "pll-0";
1104e85f28e0SJagan Teki			resets = <&ccu RST_BUS_HDMI0>;
1105e85f28e0SJagan Teki			reset-names = "phy";
1106e85f28e0SJagan Teki			#phy-cells = <0>;
1107e85f28e0SJagan Teki		};
1108e85f28e0SJagan Teki
11096bc37facSAndre Przywara		rtc: rtc@1f00000 {
111044ff3cafSChen-Yu Tsai			compatible = "allwinner,sun50i-a64-rtc",
111144ff3cafSChen-Yu Tsai				     "allwinner,sun8i-h3-rtc";
111244ff3cafSChen-Yu Tsai			reg = <0x01f00000 0x400>;
11136bc37facSAndre Przywara			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
11146bc37facSAndre Przywara				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
111544ff3cafSChen-Yu Tsai			clock-output-names = "osc32k", "osc32k-out", "iosc";
1116e1a9a474SJagan Teki			clocks = <&osc32k>;
1117e1a9a474SJagan Teki			#clock-cells = <1>;
11186bc37facSAndre Przywara		};
1119791a9e00SIcenowy Zheng
1120535ca508SIcenowy Zheng		r_intc: interrupt-controller@1f00c00 {
1121535ca508SIcenowy Zheng			compatible = "allwinner,sun50i-a64-r-intc",
1122535ca508SIcenowy Zheng				     "allwinner,sun6i-a31-r-intc";
1123535ca508SIcenowy Zheng			interrupt-controller;
1124535ca508SIcenowy Zheng			#interrupt-cells = <2>;
1125535ca508SIcenowy Zheng			reg = <0x01f00c00 0x400>;
1126535ca508SIcenowy Zheng			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1127535ca508SIcenowy Zheng		};
1128535ca508SIcenowy Zheng
1129791a9e00SIcenowy Zheng		r_ccu: clock@1f01400 {
1130791a9e00SIcenowy Zheng			compatible = "allwinner,sun50i-a64-r-ccu";
1131791a9e00SIcenowy Zheng			reg = <0x01f01400 0x100>;
1132b71818cbSChen-Yu Tsai			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1133b71818cbSChen-Yu Tsai				 <&ccu CLK_PLL_PERIPH0>;
1134f74994a9SChen-Yu Tsai			clock-names = "hosc", "losc", "iosc", "pll-periph";
1135791a9e00SIcenowy Zheng			#clock-cells = <1>;
1136791a9e00SIcenowy Zheng			#reset-cells = <1>;
1137791a9e00SIcenowy Zheng		};
1138ec427905SIcenowy Zheng
1139ec4a9540SVasily Khoruzhick		codec_analog: codec-analog@1f015c0 {
1140ec4a9540SVasily Khoruzhick			compatible = "allwinner,sun50i-a64-codec-analog";
1141ec4a9540SVasily Khoruzhick			reg = <0x01f015c0 0x4>;
1142ec4a9540SVasily Khoruzhick			status = "disabled";
1143ec4a9540SVasily Khoruzhick		};
1144ec4a9540SVasily Khoruzhick
1145871b5352SIcenowy Zheng		r_i2c: i2c@1f02400 {
1146871b5352SIcenowy Zheng			compatible = "allwinner,sun50i-a64-i2c",
1147871b5352SIcenowy Zheng				     "allwinner,sun6i-a31-i2c";
1148871b5352SIcenowy Zheng			reg = <0x01f02400 0x400>;
1149871b5352SIcenowy Zheng			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1150871b5352SIcenowy Zheng			clocks = <&r_ccu CLK_APB0_I2C>;
1151871b5352SIcenowy Zheng			resets = <&r_ccu RST_APB0_I2C>;
1152871b5352SIcenowy Zheng			status = "disabled";
1153871b5352SIcenowy Zheng			#address-cells = <1>;
1154871b5352SIcenowy Zheng			#size-cells = <0>;
1155871b5352SIcenowy Zheng		};
1156871b5352SIcenowy Zheng
115744a4f416SIgors Makejevs		r_ir: ir@1f02000 {
115844a4f416SIgors Makejevs			compatible = "allwinner,sun50i-a64-ir",
115944a4f416SIgors Makejevs				     "allwinner,sun6i-a31-ir";
116044a4f416SIgors Makejevs			reg = <0x01f02000 0x400>;
116144a4f416SIgors Makejevs			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
116244a4f416SIgors Makejevs			clock-names = "apb", "ir";
116344a4f416SIgors Makejevs			resets = <&r_ccu RST_APB0_IR>;
116444a4f416SIgors Makejevs			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116544a4f416SIgors Makejevs			pinctrl-names = "default";
116644a4f416SIgors Makejevs			pinctrl-0 = <&r_ir_rx_pin>;
116744a4f416SIgors Makejevs			status = "disabled";
116844a4f416SIgors Makejevs		};
116944a4f416SIgors Makejevs
1170b5df280bSAndre Przywara		r_pwm: pwm@1f03800 {
1171b5df280bSAndre Przywara			compatible = "allwinner,sun50i-a64-pwm",
1172b5df280bSAndre Przywara				     "allwinner,sun5i-a13-pwm";
1173b5df280bSAndre Przywara			reg = <0x01f03800 0x400>;
1174b5df280bSAndre Przywara			clocks = <&osc24M>;
1175b5df280bSAndre Przywara			pinctrl-names = "default";
1176b5df280bSAndre Przywara			pinctrl-0 = <&r_pwm_pin>;
1177b5df280bSAndre Przywara			#pwm-cells = <3>;
1178b5df280bSAndre Przywara			status = "disabled";
1179b5df280bSAndre Przywara		};
1180b5df280bSAndre Przywara
1181d6c9da12SCorentin LABBE		r_pio: pinctrl@1f02c00 {
1182ec427905SIcenowy Zheng			compatible = "allwinner,sun50i-a64-r-pinctrl";
1183ec427905SIcenowy Zheng			reg = <0x01f02c00 0x400>;
1184ec427905SIcenowy Zheng			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1185494d8a2cSChen-Yu Tsai			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1186ec427905SIcenowy Zheng			clock-names = "apb", "hosc", "losc";
1187ec427905SIcenowy Zheng			gpio-controller;
1188ec427905SIcenowy Zheng			#gpio-cells = <3>;
1189ec427905SIcenowy Zheng			interrupt-controller;
1190ec427905SIcenowy Zheng			#interrupt-cells = <3>;
11913b38fdedSIcenowy Zheng
11921b6ff1cbSChen-Yu Tsai			r_i2c_pl89_pins: r-i2c-pl89-pins {
1193871b5352SIcenowy Zheng				pins = "PL8", "PL9";
1194871b5352SIcenowy Zheng				function = "s_i2c";
1195871b5352SIcenowy Zheng			};
1196871b5352SIcenowy Zheng
119744a4f416SIgors Makejevs			r_ir_rx_pin: r-ir-rx-pin {
119844a4f416SIgors Makejevs				pins = "PL11";
119944a4f416SIgors Makejevs				function = "s_cir_rx";
120044a4f416SIgors Makejevs			};
120144a4f416SIgors Makejevs
120254eac67bSMaxime Ripard			r_pwm_pin: r-pwm-pin {
1203b5df280bSAndre Przywara				pins = "PL10";
1204b5df280bSAndre Przywara				function = "s_pwm";
1205b5df280bSAndre Przywara			};
1206b5df280bSAndre Przywara
120754eac67bSMaxime Ripard			r_rsb_pins: r-rsb-pins {
12083b38fdedSIcenowy Zheng				pins = "PL0", "PL1";
12093b38fdedSIcenowy Zheng				function = "s_rsb";
12103b38fdedSIcenowy Zheng			};
12113b38fdedSIcenowy Zheng		};
12123b38fdedSIcenowy Zheng
12133b38fdedSIcenowy Zheng		r_rsb: rsb@1f03400 {
12143b38fdedSIcenowy Zheng			compatible = "allwinner,sun8i-a23-rsb";
12153b38fdedSIcenowy Zheng			reg = <0x01f03400 0x400>;
12163b38fdedSIcenowy Zheng			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
12173b38fdedSIcenowy Zheng			clocks = <&r_ccu 6>;
12183b38fdedSIcenowy Zheng			clock-frequency = <3000000>;
12193b38fdedSIcenowy Zheng			resets = <&r_ccu 2>;
12203b38fdedSIcenowy Zheng			pinctrl-names = "default";
12213b38fdedSIcenowy Zheng			pinctrl-0 = <&r_rsb_pins>;
12223b38fdedSIcenowy Zheng			status = "disabled";
12233b38fdedSIcenowy Zheng			#address-cells = <1>;
12243b38fdedSIcenowy Zheng			#size-cells = <0>;
1225ec427905SIcenowy Zheng		};
1226d4185043SHarald Geyer
1227d4185043SHarald Geyer		wdt0: watchdog@1c20ca0 {
1228d4185043SHarald Geyer			compatible = "allwinner,sun50i-a64-wdt",
1229d4185043SHarald Geyer				     "allwinner,sun6i-a31-wdt";
1230d4185043SHarald Geyer			reg = <0x01c20ca0 0x20>;
1231d4185043SHarald Geyer			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
12329e1975f0SMaxime Ripard			clocks = <&osc24M>;
1233d4185043SHarald Geyer		};
12346bc37facSAndre Przywara	};
12356bc37facSAndre Przywara};
1236