1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd. 3cabbaed7SClément Péron// based on the Allwinner H3 dtsi: 4cabbaed7SClément Péron// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara 6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 72c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 8494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 96bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 10a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 112c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 12871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 1359f5e9b9SVasily Khoruzhick#include <dt-bindings/thermal/thermal.h> 146bc37facSAndre Przywara 156bc37facSAndre Przywara/ { 166bc37facSAndre Przywara interrupt-parent = <&gic>; 176bc37facSAndre Przywara #address-cells = <1>; 186bc37facSAndre Przywara #size-cells = <1>; 196bc37facSAndre Przywara 20c1cff65fSHarald Geyer chosen { 21c1cff65fSHarald Geyer #address-cells = <1>; 22c1cff65fSHarald Geyer #size-cells = <1>; 23c1cff65fSHarald Geyer ranges; 24c1cff65fSHarald Geyer 25c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 26c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 27c1cff65fSHarald Geyer "simple-framebuffer"; 28c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 29c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 302c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 31c1cff65fSHarald Geyer status = "disabled"; 32c1cff65fSHarald Geyer }; 33fca63f58SIcenowy Zheng 34fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 35fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 36fca63f58SIcenowy Zheng "simple-framebuffer"; 37fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 38fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 39fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40fca63f58SIcenowy Zheng status = "disabled"; 41fca63f58SIcenowy Zheng }; 42c1cff65fSHarald Geyer }; 43c1cff65fSHarald Geyer 446bc37facSAndre Przywara cpus { 456bc37facSAndre Przywara #address-cells = <1>; 466bc37facSAndre Przywara #size-cells = <0>; 476bc37facSAndre Przywara 486bc37facSAndre Przywara cpu0: cpu@0 { 4931af04cdSRob Herring compatible = "arm,cortex-a53"; 506bc37facSAndre Przywara device_type = "cpu"; 516bc37facSAndre Przywara reg = <0>; 526bc37facSAndre Przywara enable-method = "psci"; 5339defc81SAndre Przywara next-level-cache = <&L2>; 547db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 55f267eff7SVasily Khoruzhick clock-names = "cpu"; 56e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 576bc37facSAndre Przywara }; 586bc37facSAndre Przywara 596bc37facSAndre Przywara cpu1: cpu@1 { 6031af04cdSRob Herring compatible = "arm,cortex-a53"; 616bc37facSAndre Przywara device_type = "cpu"; 626bc37facSAndre Przywara reg = <1>; 636bc37facSAndre Przywara enable-method = "psci"; 6439defc81SAndre Przywara next-level-cache = <&L2>; 657db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 66f267eff7SVasily Khoruzhick clock-names = "cpu"; 67e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 686bc37facSAndre Przywara }; 696bc37facSAndre Przywara 706bc37facSAndre Przywara cpu2: cpu@2 { 7131af04cdSRob Herring compatible = "arm,cortex-a53"; 726bc37facSAndre Przywara device_type = "cpu"; 736bc37facSAndre Przywara reg = <2>; 746bc37facSAndre Przywara enable-method = "psci"; 7539defc81SAndre Przywara next-level-cache = <&L2>; 767db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 77f267eff7SVasily Khoruzhick clock-names = "cpu"; 78e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 796bc37facSAndre Przywara }; 806bc37facSAndre Przywara 816bc37facSAndre Przywara cpu3: cpu@3 { 8231af04cdSRob Herring compatible = "arm,cortex-a53"; 836bc37facSAndre Przywara device_type = "cpu"; 846bc37facSAndre Przywara reg = <3>; 856bc37facSAndre Przywara enable-method = "psci"; 8639defc81SAndre Przywara next-level-cache = <&L2>; 877db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 88f267eff7SVasily Khoruzhick clock-names = "cpu"; 89e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 9039defc81SAndre Przywara }; 9139defc81SAndre Przywara 9239defc81SAndre Przywara L2: l2-cache { 9339defc81SAndre Przywara compatible = "cache"; 9439defc81SAndre Przywara cache-level = <2>; 956bc37facSAndre Przywara }; 966bc37facSAndre Przywara }; 976bc37facSAndre Przywara 98e85f28e0SJagan Teki de: display-engine { 99e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 100e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 101e85f28e0SJagan Teki <&mixer1>; 102e85f28e0SJagan Teki status = "disabled"; 103e85f28e0SJagan Teki }; 104e85f28e0SJagan Teki 105*e954a7afSJernej Skrabec gpu_opp_table: opp-table-gpu { 106*e954a7afSJernej Skrabec compatible = "operating-points-v2"; 107*e954a7afSJernej Skrabec 108*e954a7afSJernej Skrabec opp-120000000 { 109*e954a7afSJernej Skrabec opp-hz = /bits/ 64 <120000000>; 110*e954a7afSJernej Skrabec }; 111*e954a7afSJernej Skrabec 112*e954a7afSJernej Skrabec opp-312000000 { 113*e954a7afSJernej Skrabec opp-hz = /bits/ 64 <312000000>; 114*e954a7afSJernej Skrabec }; 115*e954a7afSJernej Skrabec 116*e954a7afSJernej Skrabec opp-432000000 { 117*e954a7afSJernej Skrabec opp-hz = /bits/ 64 <432000000>; 118*e954a7afSJernej Skrabec }; 119*e954a7afSJernej Skrabec }; 120*e954a7afSJernej Skrabec 1216bc37facSAndre Przywara osc24M: osc24M_clk { 1226bc37facSAndre Przywara #clock-cells = <0>; 1236bc37facSAndre Przywara compatible = "fixed-clock"; 1246bc37facSAndre Przywara clock-frequency = <24000000>; 1256bc37facSAndre Przywara clock-output-names = "osc24M"; 1266bc37facSAndre Przywara }; 1276bc37facSAndre Przywara 1286bc37facSAndre Przywara osc32k: osc32k_clk { 1296bc37facSAndre Przywara #clock-cells = <0>; 1306bc37facSAndre Przywara compatible = "fixed-clock"; 1316bc37facSAndre Przywara clock-frequency = <32768>; 13244ff3cafSChen-Yu Tsai clock-output-names = "ext-osc32k"; 133791a9e00SIcenowy Zheng }; 134791a9e00SIcenowy Zheng 13534a97fccSHarald Geyer pmu { 13634a97fccSHarald Geyer compatible = "arm,cortex-a53-pmu"; 1376b832a14SAndre Przywara interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1386b832a14SAndre Przywara <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1396b832a14SAndre Przywara <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1406b832a14SAndre Przywara <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 14134a97fccSHarald Geyer interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 14234a97fccSHarald Geyer }; 14334a97fccSHarald Geyer 1446bc37facSAndre Przywara psci { 1456bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1466bc37facSAndre Przywara method = "smc"; 1476bc37facSAndre Przywara }; 1486bc37facSAndre Przywara 149ec4a9540SVasily Khoruzhick sound: sound { 150984a51c5SSamuel Holland #address-cells = <1>; 151984a51c5SSamuel Holland #size-cells = <0>; 152ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 153ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 154ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 155ec4a9540SVasily Khoruzhick simple-audio-card,routing = 156631e6a35SSamuel Holland "Left DAC", "DACL", 157631e6a35SSamuel Holland "Right DAC", "DACR", 158631e6a35SSamuel Holland "ADCL", "Left ADC", 159631e6a35SSamuel Holland "ADCR", "Right ADC"; 160ec4a9540SVasily Khoruzhick status = "disabled"; 161ec4a9540SVasily Khoruzhick 162984a51c5SSamuel Holland simple-audio-card,dai-link@0 { 163984a51c5SSamuel Holland format = "i2s"; 164984a51c5SSamuel Holland frame-master = <&link0_cpu>; 165984a51c5SSamuel Holland bitclock-master = <&link0_cpu>; 166984a51c5SSamuel Holland mclk-fs = <128>; 167984a51c5SSamuel Holland 168984a51c5SSamuel Holland link0_cpu: cpu { 169ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 170ec4a9540SVasily Khoruzhick }; 171ec4a9540SVasily Khoruzhick 172984a51c5SSamuel Holland link0_codec: codec { 173e0cd8e01SSamuel Holland sound-dai = <&codec 0>; 174ec4a9540SVasily Khoruzhick }; 175ec4a9540SVasily Khoruzhick }; 176984a51c5SSamuel Holland }; 177ec4a9540SVasily Khoruzhick 1786bc37facSAndre Przywara timer { 1796bc37facSAndre Przywara compatible = "arm,armv8-timer"; 18055ec26d6SSamuel Holland allwinner,erratum-unknown1; 181a371b1bdSSamuel Holland arm,no-tick-in-suspend; 1826bc37facSAndre Przywara interrupts = <GIC_PPI 13 1836bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1846bc37facSAndre Przywara <GIC_PPI 14 1856bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1866bc37facSAndre Przywara <GIC_PPI 11 1876bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1886bc37facSAndre Przywara <GIC_PPI 10 1896bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1906bc37facSAndre Przywara }; 1916bc37facSAndre Przywara 19259f5e9b9SVasily Khoruzhick thermal-zones { 19359f5e9b9SVasily Khoruzhick cpu_thermal: cpu0-thermal { 19459f5e9b9SVasily Khoruzhick /* milliseconds */ 19559f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 19659f5e9b9SVasily Khoruzhick polling-delay = <0>; 19759f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 0>; 198e1c3804aSVasily Khoruzhick 199e1c3804aSVasily Khoruzhick cooling-maps { 200e1c3804aSVasily Khoruzhick map0 { 201e1c3804aSVasily Khoruzhick trip = <&cpu_alert0>; 202e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 203e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 204e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 205e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 206e1c3804aSVasily Khoruzhick }; 207e1c3804aSVasily Khoruzhick map1 { 208e1c3804aSVasily Khoruzhick trip = <&cpu_alert1>; 209e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 212e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 213e1c3804aSVasily Khoruzhick }; 214e1c3804aSVasily Khoruzhick }; 215e1c3804aSVasily Khoruzhick 216e1c3804aSVasily Khoruzhick trips { 217e1c3804aSVasily Khoruzhick cpu_alert0: cpu_alert0 { 218e1c3804aSVasily Khoruzhick /* milliCelsius */ 219e1c3804aSVasily Khoruzhick temperature = <75000>; 220e1c3804aSVasily Khoruzhick hysteresis = <2000>; 221e1c3804aSVasily Khoruzhick type = "passive"; 222e1c3804aSVasily Khoruzhick }; 223e1c3804aSVasily Khoruzhick 224e1c3804aSVasily Khoruzhick cpu_alert1: cpu_alert1 { 225e1c3804aSVasily Khoruzhick /* milliCelsius */ 226e1c3804aSVasily Khoruzhick temperature = <90000>; 227e1c3804aSVasily Khoruzhick hysteresis = <2000>; 228e1c3804aSVasily Khoruzhick type = "hot"; 229e1c3804aSVasily Khoruzhick }; 230e1c3804aSVasily Khoruzhick 231e1c3804aSVasily Khoruzhick cpu_crit: cpu_crit { 232e1c3804aSVasily Khoruzhick /* milliCelsius */ 233e1c3804aSVasily Khoruzhick temperature = <110000>; 234e1c3804aSVasily Khoruzhick hysteresis = <2000>; 235e1c3804aSVasily Khoruzhick type = "critical"; 236e1c3804aSVasily Khoruzhick }; 237e1c3804aSVasily Khoruzhick }; 23859f5e9b9SVasily Khoruzhick }; 23959f5e9b9SVasily Khoruzhick 24059f5e9b9SVasily Khoruzhick gpu0_thermal: gpu0-thermal { 24159f5e9b9SVasily Khoruzhick /* milliseconds */ 24259f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 24359f5e9b9SVasily Khoruzhick polling-delay = <0>; 24459f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 1>; 24559f5e9b9SVasily Khoruzhick }; 24659f5e9b9SVasily Khoruzhick 24759f5e9b9SVasily Khoruzhick gpu1_thermal: gpu1-thermal { 24859f5e9b9SVasily Khoruzhick /* milliseconds */ 24959f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 25059f5e9b9SVasily Khoruzhick polling-delay = <0>; 25159f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 2>; 25259f5e9b9SVasily Khoruzhick }; 25359f5e9b9SVasily Khoruzhick }; 25459f5e9b9SVasily Khoruzhick 2556bc37facSAndre Przywara soc { 2566bc37facSAndre Przywara compatible = "simple-bus"; 2576bc37facSAndre Przywara #address-cells = <1>; 2586bc37facSAndre Przywara #size-cells = <1>; 2596bc37facSAndre Przywara ranges; 2606bc37facSAndre Przywara 261275b6317SMaxime Ripard bus@1000000 { 2622c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 2632c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 2642c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 2652c796fc8SIcenowy Zheng #address-cells = <1>; 2662c796fc8SIcenowy Zheng #size-cells = <1>; 2672c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 2682c796fc8SIcenowy Zheng 2692c796fc8SIcenowy Zheng display_clocks: clock@0 { 2702c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 2713e9a1a8bSJernej Skrabec reg = <0x0 0x10000>; 2725ea40f71SMaxime Ripard clocks = <&ccu CLK_BUS_DE>, 2735ea40f71SMaxime Ripard <&ccu CLK_DE>; 2745ea40f71SMaxime Ripard clock-names = "bus", 2755ea40f71SMaxime Ripard "mod"; 2762c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 2772c796fc8SIcenowy Zheng #clock-cells = <1>; 2782c796fc8SIcenowy Zheng #reset-cells = <1>; 2792c796fc8SIcenowy Zheng }; 280e85f28e0SJagan Teki 281048cdfceSJernej Skrabec rotate: rotate@20000 { 282048cdfceSJernej Skrabec compatible = "allwinner,sun50i-a64-de2-rotate", 283048cdfceSJernej Skrabec "allwinner,sun8i-a83t-de2-rotate"; 284048cdfceSJernej Skrabec reg = <0x20000 0x10000>; 285048cdfceSJernej Skrabec interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 286048cdfceSJernej Skrabec clocks = <&display_clocks CLK_BUS_ROT>, 287048cdfceSJernej Skrabec <&display_clocks CLK_ROT>; 288048cdfceSJernej Skrabec clock-names = "bus", 289048cdfceSJernej Skrabec "mod"; 290048cdfceSJernej Skrabec resets = <&display_clocks RST_ROT>; 291048cdfceSJernej Skrabec }; 292048cdfceSJernej Skrabec 293e85f28e0SJagan Teki mixer0: mixer@100000 { 294e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 295e85f28e0SJagan Teki reg = <0x100000 0x100000>; 296e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 297e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 298e85f28e0SJagan Teki clock-names = "bus", 299e85f28e0SJagan Teki "mod"; 300e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 301e85f28e0SJagan Teki 302e85f28e0SJagan Teki ports { 303e85f28e0SJagan Teki #address-cells = <1>; 304e85f28e0SJagan Teki #size-cells = <0>; 305e85f28e0SJagan Teki 306e85f28e0SJagan Teki mixer0_out: port@1 { 307a7f7047fSMaxime Ripard #address-cells = <1>; 308a7f7047fSMaxime Ripard #size-cells = <0>; 309e85f28e0SJagan Teki reg = <1>; 310e85f28e0SJagan Teki 311a7f7047fSMaxime Ripard mixer0_out_tcon0: endpoint@0 { 312a7f7047fSMaxime Ripard reg = <0>; 313e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 314e85f28e0SJagan Teki }; 315a7f7047fSMaxime Ripard 316a7f7047fSMaxime Ripard mixer0_out_tcon1: endpoint@1 { 317a7f7047fSMaxime Ripard reg = <1>; 318a7f7047fSMaxime Ripard remote-endpoint = <&tcon1_in_mixer0>; 319a7f7047fSMaxime Ripard }; 320e85f28e0SJagan Teki }; 321e85f28e0SJagan Teki }; 322e85f28e0SJagan Teki }; 323e85f28e0SJagan Teki 324e85f28e0SJagan Teki mixer1: mixer@200000 { 325e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 326e85f28e0SJagan Teki reg = <0x200000 0x100000>; 327e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 328e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 329e85f28e0SJagan Teki clock-names = "bus", 330e85f28e0SJagan Teki "mod"; 331e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 332e85f28e0SJagan Teki 333e85f28e0SJagan Teki ports { 334e85f28e0SJagan Teki #address-cells = <1>; 335e85f28e0SJagan Teki #size-cells = <0>; 336e85f28e0SJagan Teki 337e85f28e0SJagan Teki mixer1_out: port@1 { 338d41a43a0SMaxime Ripard #address-cells = <1>; 339d41a43a0SMaxime Ripard #size-cells = <0>; 340e85f28e0SJagan Teki reg = <1>; 341e85f28e0SJagan Teki 342a7f7047fSMaxime Ripard mixer1_out_tcon0: endpoint@0 { 343a7f7047fSMaxime Ripard reg = <0>; 344a7f7047fSMaxime Ripard remote-endpoint = <&tcon0_in_mixer1>; 345a7f7047fSMaxime Ripard }; 346a7f7047fSMaxime Ripard 347a7f7047fSMaxime Ripard mixer1_out_tcon1: endpoint@1 { 348a7f7047fSMaxime Ripard reg = <1>; 349e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 350e85f28e0SJagan Teki }; 351e85f28e0SJagan Teki }; 352e85f28e0SJagan Teki }; 353e85f28e0SJagan Teki }; 3542c796fc8SIcenowy Zheng }; 3552c796fc8SIcenowy Zheng 35679b95360SCorentin Labbe syscon: syscon@1c00000 { 3571f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 35879b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 3591f1f5183SIcenowy Zheng #address-cells = <1>; 3601f1f5183SIcenowy Zheng #size-cells = <1>; 3611f1f5183SIcenowy Zheng ranges; 3621f1f5183SIcenowy Zheng 3631f1f5183SIcenowy Zheng sram_c: sram@18000 { 3641f1f5183SIcenowy Zheng compatible = "mmio-sram"; 3651f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 3661f1f5183SIcenowy Zheng #address-cells = <1>; 3671f1f5183SIcenowy Zheng #size-cells = <1>; 3681f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 3691f1f5183SIcenowy Zheng 3701f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 3711f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 3721f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 3731f1f5183SIcenowy Zheng }; 3741f1f5183SIcenowy Zheng }; 375106deea8SPaul Kocialkowski 376106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 377106deea8SPaul Kocialkowski compatible = "mmio-sram"; 378106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 379106deea8SPaul Kocialkowski #address-cells = <1>; 380106deea8SPaul Kocialkowski #size-cells = <1>; 381106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 382106deea8SPaul Kocialkowski 383106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 384106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 385106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 386106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 387106deea8SPaul Kocialkowski }; 388106deea8SPaul Kocialkowski }; 38979b95360SCorentin Labbe }; 39079b95360SCorentin Labbe 391c32637e0SStefan Brüns dma: dma-controller@1c02000 { 392c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 393c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 394c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 395c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 396c32637e0SStefan Brüns dma-channels = <8>; 397c32637e0SStefan Brüns dma-requests = <27>; 398c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 399c32637e0SStefan Brüns #dma-cells = <1>; 400c32637e0SStefan Brüns }; 401c32637e0SStefan Brüns 402e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 403e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 404e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 405e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 406e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 407e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 408e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 409e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 41026c609d5SMaxime Ripard #clock-cells = <0>; 411e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 412e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 413e85f28e0SJagan Teki 414e85f28e0SJagan Teki ports { 415e85f28e0SJagan Teki #address-cells = <1>; 416e85f28e0SJagan Teki #size-cells = <0>; 417e85f28e0SJagan Teki 418e85f28e0SJagan Teki tcon0_in: port@0 { 419e85f28e0SJagan Teki #address-cells = <1>; 420e85f28e0SJagan Teki #size-cells = <0>; 421e85f28e0SJagan Teki reg = <0>; 422e85f28e0SJagan Teki 423e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 424e85f28e0SJagan Teki reg = <0>; 425e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 426e85f28e0SJagan Teki }; 427a7f7047fSMaxime Ripard 428a7f7047fSMaxime Ripard tcon0_in_mixer1: endpoint@1 { 429a7f7047fSMaxime Ripard reg = <1>; 430d41a43a0SMaxime Ripard remote-endpoint = <&mixer1_out_tcon0>; 431a7f7047fSMaxime Ripard }; 432e85f28e0SJagan Teki }; 433e85f28e0SJagan Teki 434e85f28e0SJagan Teki tcon0_out: port@1 { 435e85f28e0SJagan Teki #address-cells = <1>; 436e85f28e0SJagan Teki #size-cells = <0>; 437e85f28e0SJagan Teki reg = <1>; 43816c8ff57SJagan Teki 43916c8ff57SJagan Teki tcon0_out_dsi: endpoint@1 { 44016c8ff57SJagan Teki reg = <1>; 44116c8ff57SJagan Teki remote-endpoint = <&dsi_in_tcon0>; 44216c8ff57SJagan Teki allwinner,tcon-channel = <1>; 44316c8ff57SJagan Teki }; 444e85f28e0SJagan Teki }; 445e85f28e0SJagan Teki }; 446e85f28e0SJagan Teki }; 447e85f28e0SJagan Teki 448e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 449e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 450e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 451e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 452e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 453e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 454e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 455e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 456e85f28e0SJagan Teki reset-names = "lcd"; 457e85f28e0SJagan Teki 458e85f28e0SJagan Teki ports { 459e85f28e0SJagan Teki #address-cells = <1>; 460e85f28e0SJagan Teki #size-cells = <0>; 461e85f28e0SJagan Teki 462e85f28e0SJagan Teki tcon1_in: port@0 { 463a7f7047fSMaxime Ripard #address-cells = <1>; 464a7f7047fSMaxime Ripard #size-cells = <0>; 465e85f28e0SJagan Teki reg = <0>; 466e85f28e0SJagan Teki 467a7f7047fSMaxime Ripard tcon1_in_mixer0: endpoint@0 { 468a7f7047fSMaxime Ripard reg = <0>; 469a7f7047fSMaxime Ripard remote-endpoint = <&mixer0_out_tcon1>; 470a7f7047fSMaxime Ripard }; 471a7f7047fSMaxime Ripard 472a7f7047fSMaxime Ripard tcon1_in_mixer1: endpoint@1 { 473a7f7047fSMaxime Ripard reg = <1>; 474e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 475e85f28e0SJagan Teki }; 476e85f28e0SJagan Teki }; 477e85f28e0SJagan Teki 478e85f28e0SJagan Teki tcon1_out: port@1 { 479e85f28e0SJagan Teki #address-cells = <1>; 480e85f28e0SJagan Teki #size-cells = <0>; 481e85f28e0SJagan Teki reg = <1>; 482e85f28e0SJagan Teki 483e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 484e85f28e0SJagan Teki reg = <1>; 485e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 486e85f28e0SJagan Teki }; 487e85f28e0SJagan Teki }; 488e85f28e0SJagan Teki }; 489e85f28e0SJagan Teki }; 490e85f28e0SJagan Teki 491d60ce247SPaul Kocialkowski video-codec@1c0e000 { 4924ab88516SPaul Kocialkowski compatible = "allwinner,sun50i-a64-video-engine"; 493d60ce247SPaul Kocialkowski reg = <0x01c0e000 0x1000>; 494d60ce247SPaul Kocialkowski clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 495d60ce247SPaul Kocialkowski <&ccu CLK_DRAM_VE>; 496d60ce247SPaul Kocialkowski clock-names = "ahb", "mod", "ram"; 497d60ce247SPaul Kocialkowski resets = <&ccu RST_BUS_VE>; 498d60ce247SPaul Kocialkowski interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 499d60ce247SPaul Kocialkowski allwinner,sram = <&ve_sram 1>; 500d60ce247SPaul Kocialkowski }; 501d60ce247SPaul Kocialkowski 502f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 503f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 504f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 505f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 506f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 507f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 508f3dff347SAndre Przywara reset-names = "ahb"; 509f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 51022be992fSMaxime Ripard max-frequency = <150000000>; 511f3dff347SAndre Przywara status = "disabled"; 512f3dff347SAndre Przywara #address-cells = <1>; 513f3dff347SAndre Przywara #size-cells = <0>; 514f3dff347SAndre Przywara }; 515f3dff347SAndre Przywara 516f3dff347SAndre Przywara mmc1: mmc@1c10000 { 517f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 518f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 519f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 520f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 521f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 522f3dff347SAndre Przywara reset-names = "ahb"; 523f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 52422be992fSMaxime Ripard max-frequency = <150000000>; 525f3dff347SAndre Przywara status = "disabled"; 526f3dff347SAndre Przywara #address-cells = <1>; 527f3dff347SAndre Przywara #size-cells = <0>; 528f3dff347SAndre Przywara }; 529f3dff347SAndre Przywara 530f3dff347SAndre Przywara mmc2: mmc@1c11000 { 531f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 532f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 533f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 534f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 535f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 536f3dff347SAndre Przywara reset-names = "ahb"; 537f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 538948c657cSAndre Przywara max-frequency = <150000000>; 539f3dff347SAndre Przywara status = "disabled"; 540f3dff347SAndre Przywara #address-cells = <1>; 541f3dff347SAndre Przywara #size-cells = <0>; 542f3dff347SAndre Przywara }; 543f3dff347SAndre Przywara 544ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 545ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 546ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 54759f5e9b9SVasily Khoruzhick #address-cells = <1>; 54859f5e9b9SVasily Khoruzhick #size-cells = <1>; 54959f5e9b9SVasily Khoruzhick 55059f5e9b9SVasily Khoruzhick ths_calibration: thermal-sensor-calibration@34 { 55159f5e9b9SVasily Khoruzhick reg = <0x34 0x8>; 55259f5e9b9SVasily Khoruzhick }; 553ac947b17SEmmanuel Vadot }; 554ac947b17SEmmanuel Vadot 5550f5fc158SCorentin Labbe crypto: crypto@1c15000 { 5560f5fc158SCorentin Labbe compatible = "allwinner,sun50i-a64-crypto"; 5570f5fc158SCorentin Labbe reg = <0x01c15000 0x1000>; 5580f5fc158SCorentin Labbe interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 5590f5fc158SCorentin Labbe clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 5600f5fc158SCorentin Labbe clock-names = "bus", "mod"; 5610f5fc158SCorentin Labbe resets = <&ccu RST_BUS_CE>; 5620f5fc158SCorentin Labbe }; 5630f5fc158SCorentin Labbe 5643e3f39a7SSamuel Holland msgbox: mailbox@1c17000 { 5653e3f39a7SSamuel Holland compatible = "allwinner,sun50i-a64-msgbox", 5663e3f39a7SSamuel Holland "allwinner,sun6i-a31-msgbox"; 5673e3f39a7SSamuel Holland reg = <0x01c17000 0x1000>; 5683e3f39a7SSamuel Holland clocks = <&ccu CLK_BUS_MSGBOX>; 5693e3f39a7SSamuel Holland resets = <&ccu RST_BUS_MSGBOX>; 5703e3f39a7SSamuel Holland interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 5713e3f39a7SSamuel Holland #mbox-cells = <1>; 5723e3f39a7SSamuel Holland }; 5733e3f39a7SSamuel Holland 574d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 575972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 576972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 577972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 578972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 579972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 580972a3ecdSIcenowy Zheng interrupt-names = "mc"; 581972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 582972a3ecdSIcenowy Zheng phy-names = "usb"; 583972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 5840973c06bSMaxime Ripard dr_mode = "otg"; 585972a3ecdSIcenowy Zheng status = "disabled"; 586972a3ecdSIcenowy Zheng }; 587972a3ecdSIcenowy Zheng 588d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 589a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 590a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 5910d984797SIcenowy Zheng <0x01c1a800 0x4>, 592a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 593a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 5940d984797SIcenowy Zheng "pmu0", 595a004ee35SIcenowy Zheng "pmu1"; 596a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 597a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 598a004ee35SIcenowy Zheng clock-names = "usb0_phy", 599a004ee35SIcenowy Zheng "usb1_phy"; 600a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 601a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 602a004ee35SIcenowy Zheng reset-names = "usb0_reset", 603a004ee35SIcenowy Zheng "usb1_reset"; 604a004ee35SIcenowy Zheng status = "disabled"; 605a004ee35SIcenowy Zheng #phy-cells = <1>; 606a004ee35SIcenowy Zheng }; 607a004ee35SIcenowy Zheng 608d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 609dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 610dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 611dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 612dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 613dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 614dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 615dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 616dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 617cc725707SAndre Przywara phys = <&usbphy 0>; 618cc725707SAndre Przywara phy-names = "usb"; 619dc03a047SIcenowy Zheng status = "disabled"; 620dc03a047SIcenowy Zheng }; 621dc03a047SIcenowy Zheng 622d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 623dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 624dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 625dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 626dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 627dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 628dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 629cc725707SAndre Przywara phys = <&usbphy 0>; 630cc725707SAndre Przywara phy-names = "usb"; 631dc03a047SIcenowy Zheng status = "disabled"; 632dc03a047SIcenowy Zheng }; 633dc03a047SIcenowy Zheng 634d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 635a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 636a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 637a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 638a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 639a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 640a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 641a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 642a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 643a004ee35SIcenowy Zheng phys = <&usbphy 1>; 644e6064cf4SMaxime Ripard phy-names = "usb"; 645a004ee35SIcenowy Zheng status = "disabled"; 646a004ee35SIcenowy Zheng }; 647a004ee35SIcenowy Zheng 648d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 649a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 650a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 651a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 652a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 653a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 654a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 655a004ee35SIcenowy Zheng phys = <&usbphy 1>; 656e6064cf4SMaxime Ripard phy-names = "usb"; 657a004ee35SIcenowy Zheng status = "disabled"; 658a004ee35SIcenowy Zheng }; 659a004ee35SIcenowy Zheng 660d6c9da12SCorentin LABBE ccu: clock@1c20000 { 6616bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 6626bc37facSAndre Przywara reg = <0x01c20000 0x400>; 66344ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>; 6646bc37facSAndre Przywara clock-names = "hosc", "losc"; 6656bc37facSAndre Przywara #clock-cells = <1>; 6666bc37facSAndre Przywara #reset-cells = <1>; 6676bc37facSAndre Przywara }; 6686bc37facSAndre Przywara 6696bc37facSAndre Przywara pio: pinctrl@1c20800 { 6706bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 6716bc37facSAndre Przywara reg = <0x01c20800 0x400>; 672189bef23SSamuel Holland interrupt-parent = <&r_intc>; 6736bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 6746bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 6756bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 676b71818cbSChen-Yu Tsai clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 677562bf196SMaxime Ripard clock-names = "apb", "hosc", "losc"; 6786bc37facSAndre Przywara gpio-controller; 6796bc37facSAndre Przywara #gpio-cells = <3>; 6806bc37facSAndre Przywara interrupt-controller; 6816bc37facSAndre Przywara #interrupt-cells = <3>; 6826bc37facSAndre Przywara 68309e0a7eaSSamuel Holland /omit-if-no-ref/ 68409e0a7eaSSamuel Holland aif2_pins: aif2-pins { 68509e0a7eaSSamuel Holland pins = "PB4", "PB5", "PB6", "PB7"; 68609e0a7eaSSamuel Holland function = "aif2"; 68709e0a7eaSSamuel Holland }; 68809e0a7eaSSamuel Holland 68909e0a7eaSSamuel Holland /omit-if-no-ref/ 69009e0a7eaSSamuel Holland aif3_pins: aif3-pins { 69109e0a7eaSSamuel Holland pins = "PG10", "PG11", "PG12", "PG13"; 69209e0a7eaSSamuel Holland function = "aif3"; 69309e0a7eaSSamuel Holland }; 69409e0a7eaSSamuel Holland 695ff29f13eSJagan Teki csi_pins: csi-pins { 696ff29f13eSJagan Teki pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 697ff29f13eSJagan Teki "PE7", "PE8", "PE9", "PE10", "PE11"; 698ff29f13eSJagan Teki function = "csi"; 699ff29f13eSJagan Teki }; 700ff29f13eSJagan Teki 701f7056b28SJagan Teki /omit-if-no-ref/ 702f7056b28SJagan Teki csi_mclk_pin: csi-mclk-pin { 703f7056b28SJagan Teki pins = "PE1"; 704f7056b28SJagan Teki function = "csi"; 705f7056b28SJagan Teki }; 706f7056b28SJagan Teki 70754eac67bSMaxime Ripard i2c0_pins: i2c0-pins { 70811239fe6SHarald Geyer pins = "PH0", "PH1"; 70911239fe6SHarald Geyer function = "i2c0"; 71011239fe6SHarald Geyer }; 71111239fe6SHarald Geyer 71254eac67bSMaxime Ripard i2c1_pins: i2c1-pins { 7136bc37facSAndre Przywara pins = "PH2", "PH3"; 7146bc37facSAndre Przywara function = "i2c1"; 7156bc37facSAndre Przywara }; 7166bc37facSAndre Przywara 71729b2c68bSOndrej Jirman i2c2_pins: i2c2-pins { 71829b2c68bSOndrej Jirman pins = "PE14", "PE15"; 71929b2c68bSOndrej Jirman function = "i2c2"; 72029b2c68bSOndrej Jirman }; 72129b2c68bSOndrej Jirman 722c478a12eSIcenowy Zheng /omit-if-no-ref/ 723c478a12eSIcenowy Zheng lcd_rgb666_pins: lcd-rgb666-pins { 724c478a12eSIcenowy Zheng pins = "PD0", "PD1", "PD2", "PD3", "PD4", 725c478a12eSIcenowy Zheng "PD5", "PD6", "PD7", "PD8", "PD9", 726c478a12eSIcenowy Zheng "PD10", "PD11", "PD12", "PD13", 727c478a12eSIcenowy Zheng "PD14", "PD15", "PD16", "PD17", 728c478a12eSIcenowy Zheng "PD18", "PD19", "PD20", "PD21"; 729c478a12eSIcenowy Zheng function = "lcd0"; 730c478a12eSIcenowy Zheng }; 731c478a12eSIcenowy Zheng 732a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 733a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 734a3e8f492SMaxime Ripard "PF4", "PF5"; 735a3e8f492SMaxime Ripard function = "mmc0"; 736a3e8f492SMaxime Ripard drive-strength = <30>; 737a3e8f492SMaxime Ripard bias-pull-up; 738a3e8f492SMaxime Ripard }; 739a3e8f492SMaxime Ripard 740a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 741a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 742a3e8f492SMaxime Ripard "PG4", "PG5"; 743a3e8f492SMaxime Ripard function = "mmc1"; 744a3e8f492SMaxime Ripard drive-strength = <30>; 745a3e8f492SMaxime Ripard bias-pull-up; 746a3e8f492SMaxime Ripard }; 747a3e8f492SMaxime Ripard 748a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 749fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 750a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 751a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 752a3e8f492SMaxime Ripard function = "mmc2"; 753a3e8f492SMaxime Ripard drive-strength = <30>; 754a3e8f492SMaxime Ripard bias-pull-up; 755a3e8f492SMaxime Ripard }; 756a3e8f492SMaxime Ripard 757fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 758fa59dd2eSChen-Yu Tsai pins = "PC1"; 759fa59dd2eSChen-Yu Tsai function = "mmc2"; 760fa59dd2eSChen-Yu Tsai drive-strength = <30>; 761fa59dd2eSChen-Yu Tsai bias-pull-up; 762fa59dd2eSChen-Yu Tsai }; 763fa59dd2eSChen-Yu Tsai 76454eac67bSMaxime Ripard pwm_pin: pwm-pin { 765b5df280bSAndre Przywara pins = "PD22"; 766b5df280bSAndre Przywara function = "pwm"; 767b5df280bSAndre Przywara }; 768b5df280bSAndre Przywara 76954eac67bSMaxime Ripard rmii_pins: rmii-pins { 770e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 771e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 772e53f67e9SCorentin Labbe function = "emac"; 773e53f67e9SCorentin Labbe drive-strength = <40>; 774e53f67e9SCorentin Labbe }; 775e53f67e9SCorentin Labbe 77654eac67bSMaxime Ripard rgmii_pins: rgmii-pins { 777e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 778e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 779e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 780e53f67e9SCorentin Labbe function = "emac"; 781e53f67e9SCorentin Labbe drive-strength = <40>; 782e53f67e9SCorentin Labbe }; 783e53f67e9SCorentin Labbe 78454eac67bSMaxime Ripard spdif_tx_pin: spdif-tx-pin { 785b399d2acSMarcus Cooper pins = "PH8"; 786b399d2acSMarcus Cooper function = "spdif"; 787b399d2acSMarcus Cooper }; 788b399d2acSMarcus Cooper 78954eac67bSMaxime Ripard spi0_pins: spi0-pins { 790b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 791b518bb15SStefan Brüns function = "spi0"; 792b518bb15SStefan Brüns }; 793b518bb15SStefan Brüns 79454eac67bSMaxime Ripard spi1_pins: spi1-pins { 795b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 796b518bb15SStefan Brüns function = "spi1"; 797b518bb15SStefan Brüns }; 798b518bb15SStefan Brüns 799d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 8006bc37facSAndre Przywara pins = "PB8", "PB9"; 8016bc37facSAndre Przywara function = "uart0"; 8026bc37facSAndre Przywara }; 803e7ba733dSAndre Przywara 80454eac67bSMaxime Ripard uart1_pins: uart1-pins { 805e7ba733dSAndre Przywara pins = "PG6", "PG7"; 806e7ba733dSAndre Przywara function = "uart1"; 807e7ba733dSAndre Przywara }; 808e7ba733dSAndre Przywara 80954eac67bSMaxime Ripard uart1_rts_cts_pins: uart1-rts-cts-pins { 810e7ba733dSAndre Przywara pins = "PG8", "PG9"; 811e7ba733dSAndre Przywara function = "uart1"; 812e7ba733dSAndre Przywara }; 81379825719SAndreas Färber 81479825719SAndreas Färber uart2_pins: uart2-pins { 81579825719SAndreas Färber pins = "PB0", "PB1"; 81679825719SAndreas Färber function = "uart2"; 81779825719SAndreas Färber }; 8182273aa16SAndreas Färber 8192273aa16SAndreas Färber uart3_pins: uart3-pins { 8202273aa16SAndreas Färber pins = "PD0", "PD1"; 8212273aa16SAndreas Färber function = "uart3"; 8222273aa16SAndreas Färber }; 8232273aa16SAndreas Färber 8242273aa16SAndreas Färber uart4_pins: uart4-pins { 8252273aa16SAndreas Färber pins = "PD2", "PD3"; 8262273aa16SAndreas Färber function = "uart4"; 8272273aa16SAndreas Färber }; 8282273aa16SAndreas Färber 8292273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 8302273aa16SAndreas Färber pins = "PD4", "PD5"; 8312273aa16SAndreas Färber function = "uart4"; 8322273aa16SAndreas Färber }; 8336bc37facSAndre Przywara }; 8346bc37facSAndre Przywara 83512bcaacaSSamuel Holland timer@1c20c00 { 83612bcaacaSSamuel Holland compatible = "allwinner,sun50i-a64-timer", 83712bcaacaSSamuel Holland "allwinner,sun8i-a23-timer"; 83812bcaacaSSamuel Holland reg = <0x01c20c00 0xa0>; 83912bcaacaSSamuel Holland interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 84012bcaacaSSamuel Holland <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 84112bcaacaSSamuel Holland clocks = <&osc24M>; 84212bcaacaSSamuel Holland }; 84312bcaacaSSamuel Holland 844af97dd55SSamuel Holland wdt0: watchdog@1c20ca0 { 845af97dd55SSamuel Holland compatible = "allwinner,sun50i-a64-wdt", 846af97dd55SSamuel Holland "allwinner,sun6i-a31-wdt"; 847af97dd55SSamuel Holland reg = <0x01c20ca0 0x20>; 848af97dd55SSamuel Holland interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 849af97dd55SSamuel Holland clocks = <&osc24M>; 850af97dd55SSamuel Holland }; 851af97dd55SSamuel Holland 852b399d2acSMarcus Cooper spdif: spdif@1c21000 { 853b399d2acSMarcus Cooper #sound-dai-cells = <0>; 854b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 855b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 856b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 857b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 858b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 859b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 860b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 861b399d2acSMarcus Cooper dmas = <&dma 2>; 862b399d2acSMarcus Cooper dma-names = "tx"; 863b399d2acSMarcus Cooper pinctrl-names = "default"; 864b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 865b399d2acSMarcus Cooper status = "disabled"; 866b399d2acSMarcus Cooper }; 867b399d2acSMarcus Cooper 86884204fb6SLuca Weiss lradc: lradc@1c21800 { 86984204fb6SLuca Weiss compatible = "allwinner,sun50i-a64-lradc", 87084204fb6SLuca Weiss "allwinner,sun8i-a83t-r-lradc"; 87184204fb6SLuca Weiss reg = <0x01c21800 0x400>; 872189bef23SSamuel Holland interrupt-parent = <&r_intc>; 87384204fb6SLuca Weiss interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 87484204fb6SLuca Weiss status = "disabled"; 87584204fb6SLuca Weiss }; 87684204fb6SLuca Weiss 8771c92c009SMarcus Cooper i2s0: i2s@1c22000 { 8781c92c009SMarcus Cooper #sound-dai-cells = <0>; 8791c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8801c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8811c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 8821c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8831c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 8841c92c009SMarcus Cooper clock-names = "apb", "mod"; 8851c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 8861c92c009SMarcus Cooper dma-names = "rx", "tx"; 8871c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 8881c92c009SMarcus Cooper status = "disabled"; 8891c92c009SMarcus Cooper }; 8901c92c009SMarcus Cooper 8911c92c009SMarcus Cooper i2s1: i2s@1c22400 { 8921c92c009SMarcus Cooper #sound-dai-cells = <0>; 8931c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8941c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8951c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 8961c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8971c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 8981c92c009SMarcus Cooper clock-names = "apb", "mod"; 8991c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 9001c92c009SMarcus Cooper dma-names = "rx", "tx"; 9011c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 9021c92c009SMarcus Cooper status = "disabled"; 9031c92c009SMarcus Cooper }; 9041c92c009SMarcus Cooper 905796c994eSMarcus Cooper i2s2: i2s@1c22800 { 906796c994eSMarcus Cooper #sound-dai-cells = <0>; 907796c994eSMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 908796c994eSMarcus Cooper "allwinner,sun8i-h3-i2s"; 909796c994eSMarcus Cooper reg = <0x01c22800 0x400>; 910796c994eSMarcus Cooper interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 911796c994eSMarcus Cooper clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 912796c994eSMarcus Cooper clock-names = "apb", "mod"; 913796c994eSMarcus Cooper resets = <&ccu RST_BUS_I2S2>; 914796c994eSMarcus Cooper dma-names = "rx", "tx"; 915796c994eSMarcus Cooper dmas = <&dma 27>, <&dma 27>; 916796c994eSMarcus Cooper status = "disabled"; 917796c994eSMarcus Cooper }; 918796c994eSMarcus Cooper 919ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 920ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 921ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 922ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 923ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 924ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 925ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 926ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 927ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 928ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 929ec4a9540SVasily Khoruzhick status = "disabled"; 930ec4a9540SVasily Khoruzhick }; 931ec4a9540SVasily Khoruzhick 932ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 933e0cd8e01SSamuel Holland #sound-dai-cells = <1>; 934db9c6ad2SSamuel Holland compatible = "allwinner,sun50i-a64-codec", 935db9c6ad2SSamuel Holland "allwinner,sun8i-a33-codec"; 936ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 937ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 938ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 939ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 940ec4a9540SVasily Khoruzhick status = "disabled"; 941ec4a9540SVasily Khoruzhick }; 942ec4a9540SVasily Khoruzhick 94359f5e9b9SVasily Khoruzhick ths: thermal-sensor@1c25000 { 94459f5e9b9SVasily Khoruzhick compatible = "allwinner,sun50i-a64-ths"; 94559f5e9b9SVasily Khoruzhick reg = <0x01c25000 0x100>; 94659f5e9b9SVasily Khoruzhick clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 94759f5e9b9SVasily Khoruzhick clock-names = "bus", "mod"; 94859f5e9b9SVasily Khoruzhick interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 94959f5e9b9SVasily Khoruzhick resets = <&ccu RST_BUS_THS>; 95059f5e9b9SVasily Khoruzhick nvmem-cells = <&ths_calibration>; 95159f5e9b9SVasily Khoruzhick nvmem-cell-names = "calibration"; 95259f5e9b9SVasily Khoruzhick #thermal-sensor-cells = <1>; 95359f5e9b9SVasily Khoruzhick }; 95459f5e9b9SVasily Khoruzhick 9556bc37facSAndre Przywara uart0: serial@1c28000 { 9566bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9576bc37facSAndre Przywara reg = <0x01c28000 0x400>; 9586bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 9596bc37facSAndre Przywara reg-shift = <2>; 9606bc37facSAndre Przywara reg-io-width = <4>; 961494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 962494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 9636bc37facSAndre Przywara status = "disabled"; 9646bc37facSAndre Przywara }; 9656bc37facSAndre Przywara 9666bc37facSAndre Przywara uart1: serial@1c28400 { 9676bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9686bc37facSAndre Przywara reg = <0x01c28400 0x400>; 9696bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 9706bc37facSAndre Przywara reg-shift = <2>; 9716bc37facSAndre Przywara reg-io-width = <4>; 972494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 973494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 9746bc37facSAndre Przywara status = "disabled"; 9756bc37facSAndre Przywara }; 9766bc37facSAndre Przywara 9776bc37facSAndre Przywara uart2: serial@1c28800 { 9786bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9796bc37facSAndre Przywara reg = <0x01c28800 0x400>; 9806bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 9816bc37facSAndre Przywara reg-shift = <2>; 9826bc37facSAndre Przywara reg-io-width = <4>; 983494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 984494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 9856bc37facSAndre Przywara status = "disabled"; 9866bc37facSAndre Przywara }; 9876bc37facSAndre Przywara 9886bc37facSAndre Przywara uart3: serial@1c28c00 { 9896bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9906bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 9916bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 9926bc37facSAndre Przywara reg-shift = <2>; 9936bc37facSAndre Przywara reg-io-width = <4>; 994494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 995494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 9966bc37facSAndre Przywara status = "disabled"; 9976bc37facSAndre Przywara }; 9986bc37facSAndre Przywara 9996bc37facSAndre Przywara uart4: serial@1c29000 { 10006bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 10016bc37facSAndre Przywara reg = <0x01c29000 0x400>; 10026bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 10036bc37facSAndre Przywara reg-shift = <2>; 10046bc37facSAndre Przywara reg-io-width = <4>; 1005494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 1006494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 10076bc37facSAndre Przywara status = "disabled"; 10086bc37facSAndre Przywara }; 10096bc37facSAndre Przywara 10106bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 10116bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 10126bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 10136bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1014494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 1015494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 101670f76289SJagan Teki pinctrl-names = "default"; 101770f76289SJagan Teki pinctrl-0 = <&i2c0_pins>; 10186bc37facSAndre Przywara status = "disabled"; 10196bc37facSAndre Przywara #address-cells = <1>; 10206bc37facSAndre Przywara #size-cells = <0>; 10216bc37facSAndre Przywara }; 10226bc37facSAndre Przywara 10236bc37facSAndre Przywara i2c1: i2c@1c2b000 { 10246bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 10256bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 10266bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1027494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 1028494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 102970f76289SJagan Teki pinctrl-names = "default"; 103070f76289SJagan Teki pinctrl-0 = <&i2c1_pins>; 10316bc37facSAndre Przywara status = "disabled"; 10326bc37facSAndre Przywara #address-cells = <1>; 10336bc37facSAndre Przywara #size-cells = <0>; 10346bc37facSAndre Przywara }; 10356bc37facSAndre Przywara 10366bc37facSAndre Przywara i2c2: i2c@1c2b400 { 10376bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 10386bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 10396bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1040494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 1041494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 104229b2c68bSOndrej Jirman pinctrl-names = "default"; 104329b2c68bSOndrej Jirman pinctrl-0 = <&i2c2_pins>; 10446bc37facSAndre Przywara status = "disabled"; 10456bc37facSAndre Przywara #address-cells = <1>; 10466bc37facSAndre Przywara #size-cells = <0>; 10476bc37facSAndre Przywara }; 10486bc37facSAndre Przywara 1049d6c9da12SCorentin LABBE spi0: spi@1c68000 { 1050b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 1051b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 1052b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1053b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1054b518bb15SStefan Brüns clock-names = "ahb", "mod"; 105506c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 105606c1258aSStefan Brüns dma-names = "rx", "tx"; 1057b518bb15SStefan Brüns pinctrl-names = "default"; 1058b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 1059b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 1060b518bb15SStefan Brüns status = "disabled"; 1061b518bb15SStefan Brüns num-cs = <1>; 1062b518bb15SStefan Brüns #address-cells = <1>; 1063b518bb15SStefan Brüns #size-cells = <0>; 1064b518bb15SStefan Brüns }; 1065b518bb15SStefan Brüns 1066d6c9da12SCorentin LABBE spi1: spi@1c69000 { 1067b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 1068b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 1069b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1070b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1071b518bb15SStefan Brüns clock-names = "ahb", "mod"; 107206c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 107306c1258aSStefan Brüns dma-names = "rx", "tx"; 1074b518bb15SStefan Brüns pinctrl-names = "default"; 1075b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 1076b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 1077b518bb15SStefan Brüns status = "disabled"; 1078b518bb15SStefan Brüns num-cs = <1>; 1079b518bb15SStefan Brüns #address-cells = <1>; 1080b518bb15SStefan Brüns #size-cells = <0>; 1081b518bb15SStefan Brüns }; 1082b518bb15SStefan Brüns 108394f44288SCorentin Labbe emac: ethernet@1c30000 { 108494f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 108594f44288SCorentin Labbe syscon = <&syscon>; 108694f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 108794f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 108894f44288SCorentin Labbe interrupt-names = "macirq"; 108994f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 109094f44288SCorentin Labbe reset-names = "stmmaceth"; 109194f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 109294f44288SCorentin Labbe clock-names = "stmmaceth"; 109394f44288SCorentin Labbe status = "disabled"; 109494f44288SCorentin Labbe 109594f44288SCorentin Labbe mdio: mdio { 109616416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 109794f44288SCorentin Labbe #address-cells = <1>; 109894f44288SCorentin Labbe #size-cells = <0>; 109994f44288SCorentin Labbe }; 110094f44288SCorentin Labbe }; 110194f44288SCorentin Labbe 11026b683d76SJagan Teki mali: gpu@1c40000 { 11036b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 11046b683d76SJagan Teki reg = <0x01c40000 0x10000>; 11056b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 11066b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 11076b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 11086b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 11096b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 11106b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 11116b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 11126b683d76SJagan Teki interrupt-names = "gp", 11136b683d76SJagan Teki "gpmmu", 11146b683d76SJagan Teki "pp0", 11156b683d76SJagan Teki "ppmmu0", 11166b683d76SJagan Teki "pp1", 11176b683d76SJagan Teki "ppmmu1", 11186b683d76SJagan Teki "pmu"; 11196b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 11206b683d76SJagan Teki clock-names = "bus", "core"; 11216b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 1122*e954a7afSJernej Skrabec operating-points-v2 = <&gpu_opp_table>; 11236b683d76SJagan Teki }; 11246b683d76SJagan Teki 11256bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 11266bc37facSAndre Przywara compatible = "arm,gic-400"; 11276bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 11286bc37facSAndre Przywara <0x01c82000 0x2000>, 11296bc37facSAndre Przywara <0x01c84000 0x2000>, 11306bc37facSAndre Przywara <0x01c86000 0x2000>; 11316bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 11326bc37facSAndre Przywara interrupt-controller; 11336bc37facSAndre Przywara #interrupt-cells = <3>; 11346bc37facSAndre Przywara }; 11356bc37facSAndre Przywara 1136b5df280bSAndre Przywara pwm: pwm@1c21400 { 1137b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1138b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1139b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 1140b5df280bSAndre Przywara clocks = <&osc24M>; 1141b5df280bSAndre Przywara pinctrl-names = "default"; 1142b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 1143b5df280bSAndre Przywara #pwm-cells = <3>; 1144b5df280bSAndre Przywara status = "disabled"; 1145b5df280bSAndre Przywara }; 1146b5df280bSAndre Przywara 1147fc7c2bfbSJernej Skrabec mbus: dram-controller@1c62000 { 1148fc7c2bfbSJernej Skrabec compatible = "allwinner,sun50i-a64-mbus"; 1149fc7c2bfbSJernej Skrabec reg = <0x01c62000 0x1000>; 1150fc7c2bfbSJernej Skrabec clocks = <&ccu 112>; 1151cff11101SOndrej Jirman #address-cells = <1>; 1152cff11101SOndrej Jirman #size-cells = <1>; 1153fc7c2bfbSJernej Skrabec dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1154fc7c2bfbSJernej Skrabec #interconnect-cells = <1>; 1155fc7c2bfbSJernej Skrabec }; 1156fc7c2bfbSJernej Skrabec 1157ff29f13eSJagan Teki csi: csi@1cb0000 { 1158ff29f13eSJagan Teki compatible = "allwinner,sun50i-a64-csi"; 1159ff29f13eSJagan Teki reg = <0x01cb0000 0x1000>; 1160ff29f13eSJagan Teki interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1161ff29f13eSJagan Teki clocks = <&ccu CLK_BUS_CSI>, 1162ff29f13eSJagan Teki <&ccu CLK_CSI_SCLK>, 1163ff29f13eSJagan Teki <&ccu CLK_DRAM_CSI>; 1164ff29f13eSJagan Teki clock-names = "bus", "mod", "ram"; 1165ff29f13eSJagan Teki resets = <&ccu RST_BUS_CSI>; 1166ff29f13eSJagan Teki pinctrl-names = "default"; 1167ff29f13eSJagan Teki pinctrl-0 = <&csi_pins>; 1168ff29f13eSJagan Teki status = "disabled"; 1169ff29f13eSJagan Teki }; 1170ff29f13eSJagan Teki 117116c8ff57SJagan Teki dsi: dsi@1ca0000 { 117216c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dsi"; 117316c8ff57SJagan Teki reg = <0x01ca0000 0x1000>; 117416c8ff57SJagan Teki interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 117516c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>; 117616c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 117716c8ff57SJagan Teki phys = <&dphy>; 117816c8ff57SJagan Teki phy-names = "dphy"; 117916c8ff57SJagan Teki status = "disabled"; 118016c8ff57SJagan Teki #address-cells = <1>; 118116c8ff57SJagan Teki #size-cells = <0>; 118216c8ff57SJagan Teki 118316c8ff57SJagan Teki port { 118416c8ff57SJagan Teki dsi_in_tcon0: endpoint { 118516c8ff57SJagan Teki remote-endpoint = <&tcon0_out_dsi>; 118616c8ff57SJagan Teki }; 118716c8ff57SJagan Teki }; 118816c8ff57SJagan Teki }; 118916c8ff57SJagan Teki 119016c8ff57SJagan Teki dphy: d-phy@1ca1000 { 119116c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dphy", 119216c8ff57SJagan Teki "allwinner,sun6i-a31-mipi-dphy"; 119316c8ff57SJagan Teki reg = <0x01ca1000 0x1000>; 119416c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>, 119516c8ff57SJagan Teki <&ccu CLK_DSI_DPHY>; 119616c8ff57SJagan Teki clock-names = "bus", "mod"; 119716c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 119816c8ff57SJagan Teki status = "disabled"; 119916c8ff57SJagan Teki #phy-cells = <0>; 120016c8ff57SJagan Teki }; 120116c8ff57SJagan Teki 1202dd00d78dSJernej Skrabec deinterlace: deinterlace@1e00000 { 1203dd00d78dSJernej Skrabec compatible = "allwinner,sun50i-a64-deinterlace", 1204dd00d78dSJernej Skrabec "allwinner,sun8i-h3-deinterlace"; 1205dd00d78dSJernej Skrabec reg = <0x01e00000 0x20000>; 1206dd00d78dSJernej Skrabec clocks = <&ccu CLK_BUS_DEINTERLACE>, 1207dd00d78dSJernej Skrabec <&ccu CLK_DEINTERLACE>, 1208dd00d78dSJernej Skrabec <&ccu CLK_DRAM_DEINTERLACE>; 1209dd00d78dSJernej Skrabec clock-names = "bus", "mod", "ram"; 1210dd00d78dSJernej Skrabec resets = <&ccu RST_BUS_DEINTERLACE>; 1211dd00d78dSJernej Skrabec interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1212dd00d78dSJernej Skrabec interconnects = <&mbus 9>; 1213dd00d78dSJernej Skrabec interconnect-names = "dma-mem"; 1214dd00d78dSJernej Skrabec }; 1215dd00d78dSJernej Skrabec 1216e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 1217e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 1218e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 1219e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 1220e85f28e0SJagan Teki reg-io-width = <1>; 1221e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1222e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1223e85f28e0SJagan Teki <&ccu CLK_HDMI>; 1224e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 1225e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 1226e85f28e0SJagan Teki reset-names = "ctrl"; 1227e85f28e0SJagan Teki phys = <&hdmi_phy>; 1228d40113fbSMaxime Ripard phy-names = "phy"; 1229e85f28e0SJagan Teki status = "disabled"; 1230e85f28e0SJagan Teki 1231e85f28e0SJagan Teki ports { 1232e85f28e0SJagan Teki #address-cells = <1>; 1233e85f28e0SJagan Teki #size-cells = <0>; 1234e85f28e0SJagan Teki 1235e85f28e0SJagan Teki hdmi_in: port@0 { 1236e85f28e0SJagan Teki reg = <0>; 1237e85f28e0SJagan Teki 1238e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 1239e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 1240e85f28e0SJagan Teki }; 1241e85f28e0SJagan Teki }; 1242e85f28e0SJagan Teki 1243e85f28e0SJagan Teki hdmi_out: port@1 { 1244e85f28e0SJagan Teki reg = <1>; 1245e85f28e0SJagan Teki }; 1246e85f28e0SJagan Teki }; 1247e85f28e0SJagan Teki }; 1248e85f28e0SJagan Teki 1249e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 1250e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 1251e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 1252e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1253b71818cbSChen-Yu Tsai <&ccu CLK_PLL_VIDEO0>; 1254e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 1255e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 1256e85f28e0SJagan Teki reset-names = "phy"; 1257e85f28e0SJagan Teki #phy-cells = <0>; 1258e85f28e0SJagan Teki }; 1259e85f28e0SJagan Teki 12606bc37facSAndre Przywara rtc: rtc@1f00000 { 126144ff3cafSChen-Yu Tsai compatible = "allwinner,sun50i-a64-rtc", 126244ff3cafSChen-Yu Tsai "allwinner,sun8i-h3-rtc"; 126344ff3cafSChen-Yu Tsai reg = <0x01f00000 0x400>; 1264189bef23SSamuel Holland interrupt-parent = <&r_intc>; 12656bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 12666bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 126744ff3cafSChen-Yu Tsai clock-output-names = "osc32k", "osc32k-out", "iosc"; 1268e1a9a474SJagan Teki clocks = <&osc32k>; 1269e1a9a474SJagan Teki #clock-cells = <1>; 12706bc37facSAndre Przywara }; 1271791a9e00SIcenowy Zheng 1272535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 1273535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 1274535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 1275535ca508SIcenowy Zheng interrupt-controller; 127673088dfeSSamuel Holland #interrupt-cells = <3>; 1277535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 1278535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1279535ca508SIcenowy Zheng }; 1280535ca508SIcenowy Zheng 1281791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 1282791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 1283791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 1284b71818cbSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 1285b71818cbSChen-Yu Tsai <&ccu CLK_PLL_PERIPH0>; 1286f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 1287791a9e00SIcenowy Zheng #clock-cells = <1>; 1288791a9e00SIcenowy Zheng #reset-cells = <1>; 1289791a9e00SIcenowy Zheng }; 1290ec427905SIcenowy Zheng 1291ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 1292ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 1293ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 1294ec4a9540SVasily Khoruzhick status = "disabled"; 1295ec4a9540SVasily Khoruzhick }; 1296ec4a9540SVasily Khoruzhick 1297871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 1298871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 1299871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 1300871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 1301871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1302871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1303871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1304871b5352SIcenowy Zheng status = "disabled"; 1305871b5352SIcenowy Zheng #address-cells = <1>; 1306871b5352SIcenowy Zheng #size-cells = <0>; 1307871b5352SIcenowy Zheng }; 1308871b5352SIcenowy Zheng 130944a4f416SIgors Makejevs r_ir: ir@1f02000 { 131044a4f416SIgors Makejevs compatible = "allwinner,sun50i-a64-ir", 131144a4f416SIgors Makejevs "allwinner,sun6i-a31-ir"; 131244a4f416SIgors Makejevs reg = <0x01f02000 0x400>; 131344a4f416SIgors Makejevs clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 131444a4f416SIgors Makejevs clock-names = "apb", "ir"; 131544a4f416SIgors Makejevs resets = <&r_ccu RST_APB0_IR>; 131644a4f416SIgors Makejevs interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 131744a4f416SIgors Makejevs pinctrl-names = "default"; 131844a4f416SIgors Makejevs pinctrl-0 = <&r_ir_rx_pin>; 131944a4f416SIgors Makejevs status = "disabled"; 132044a4f416SIgors Makejevs }; 132144a4f416SIgors Makejevs 1322b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1323b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1324b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1325b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1326b5df280bSAndre Przywara clocks = <&osc24M>; 1327b5df280bSAndre Przywara pinctrl-names = "default"; 1328b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1329b5df280bSAndre Przywara #pwm-cells = <3>; 1330b5df280bSAndre Przywara status = "disabled"; 1331b5df280bSAndre Przywara }; 1332b5df280bSAndre Przywara 1333d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1334ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1335ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1336189bef23SSamuel Holland interrupt-parent = <&r_intc>; 1337ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1338494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1339ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1340ec427905SIcenowy Zheng gpio-controller; 1341ec427905SIcenowy Zheng #gpio-cells = <3>; 1342ec427905SIcenowy Zheng interrupt-controller; 1343ec427905SIcenowy Zheng #interrupt-cells = <3>; 13443b38fdedSIcenowy Zheng 13451b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1346871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1347871b5352SIcenowy Zheng function = "s_i2c"; 1348871b5352SIcenowy Zheng }; 1349871b5352SIcenowy Zheng 135044a4f416SIgors Makejevs r_ir_rx_pin: r-ir-rx-pin { 135144a4f416SIgors Makejevs pins = "PL11"; 135244a4f416SIgors Makejevs function = "s_cir_rx"; 135344a4f416SIgors Makejevs }; 135444a4f416SIgors Makejevs 135554eac67bSMaxime Ripard r_pwm_pin: r-pwm-pin { 1356b5df280bSAndre Przywara pins = "PL10"; 1357b5df280bSAndre Przywara function = "s_pwm"; 1358b5df280bSAndre Przywara }; 1359b5df280bSAndre Przywara 136054eac67bSMaxime Ripard r_rsb_pins: r-rsb-pins { 13613b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 13623b38fdedSIcenowy Zheng function = "s_rsb"; 13633b38fdedSIcenowy Zheng }; 13643b38fdedSIcenowy Zheng }; 13653b38fdedSIcenowy Zheng 13663b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 13673b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 13683b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 13693b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 13703b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 13713b38fdedSIcenowy Zheng clock-frequency = <3000000>; 13723b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 13733b38fdedSIcenowy Zheng pinctrl-names = "default"; 13743b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 13753b38fdedSIcenowy Zheng status = "disabled"; 13763b38fdedSIcenowy Zheng #address-cells = <1>; 13773b38fdedSIcenowy Zheng #size-cells = <0>; 1378ec427905SIcenowy Zheng }; 13796bc37facSAndre Przywara }; 13806bc37facSAndre Przywara}; 1381