16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 46494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 476bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 48a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 496bc37facSAndre Przywara 506bc37facSAndre Przywara/ { 516bc37facSAndre Przywara interrupt-parent = <&gic>; 526bc37facSAndre Przywara #address-cells = <1>; 536bc37facSAndre Przywara #size-cells = <1>; 546bc37facSAndre Przywara 556bc37facSAndre Przywara cpus { 566bc37facSAndre Przywara #address-cells = <1>; 576bc37facSAndre Przywara #size-cells = <0>; 586bc37facSAndre Przywara 596bc37facSAndre Przywara cpu0: cpu@0 { 606bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 616bc37facSAndre Przywara device_type = "cpu"; 626bc37facSAndre Przywara reg = <0>; 636bc37facSAndre Przywara enable-method = "psci"; 646bc37facSAndre Przywara }; 656bc37facSAndre Przywara 666bc37facSAndre Przywara cpu1: cpu@1 { 676bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 686bc37facSAndre Przywara device_type = "cpu"; 696bc37facSAndre Przywara reg = <1>; 706bc37facSAndre Przywara enable-method = "psci"; 716bc37facSAndre Przywara }; 726bc37facSAndre Przywara 736bc37facSAndre Przywara cpu2: cpu@2 { 746bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 756bc37facSAndre Przywara device_type = "cpu"; 766bc37facSAndre Przywara reg = <2>; 776bc37facSAndre Przywara enable-method = "psci"; 786bc37facSAndre Przywara }; 796bc37facSAndre Przywara 806bc37facSAndre Przywara cpu3: cpu@3 { 816bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 826bc37facSAndre Przywara device_type = "cpu"; 836bc37facSAndre Przywara reg = <3>; 846bc37facSAndre Przywara enable-method = "psci"; 856bc37facSAndre Przywara }; 866bc37facSAndre Przywara }; 876bc37facSAndre Przywara 886bc37facSAndre Przywara osc24M: osc24M_clk { 896bc37facSAndre Przywara #clock-cells = <0>; 906bc37facSAndre Przywara compatible = "fixed-clock"; 916bc37facSAndre Przywara clock-frequency = <24000000>; 926bc37facSAndre Przywara clock-output-names = "osc24M"; 936bc37facSAndre Przywara }; 946bc37facSAndre Przywara 956bc37facSAndre Przywara osc32k: osc32k_clk { 966bc37facSAndre Przywara #clock-cells = <0>; 976bc37facSAndre Przywara compatible = "fixed-clock"; 986bc37facSAndre Przywara clock-frequency = <32768>; 996bc37facSAndre Przywara clock-output-names = "osc32k"; 1006bc37facSAndre Przywara }; 1016bc37facSAndre Przywara 102791a9e00SIcenowy Zheng iosc: internal-osc-clk { 103791a9e00SIcenowy Zheng #clock-cells = <0>; 104791a9e00SIcenowy Zheng compatible = "fixed-clock"; 105791a9e00SIcenowy Zheng clock-frequency = <16000000>; 106791a9e00SIcenowy Zheng clock-accuracy = <300000000>; 107791a9e00SIcenowy Zheng clock-output-names = "iosc"; 108791a9e00SIcenowy Zheng }; 109791a9e00SIcenowy Zheng 1106bc37facSAndre Przywara psci { 1116bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1126bc37facSAndre Przywara method = "smc"; 1136bc37facSAndre Przywara }; 1146bc37facSAndre Przywara 11578e07137SMarcus Cooper sound_spdif { 11678e07137SMarcus Cooper compatible = "simple-audio-card"; 11778e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 11878e07137SMarcus Cooper 11978e07137SMarcus Cooper simple-audio-card,cpu { 12078e07137SMarcus Cooper sound-dai = <&spdif>; 12178e07137SMarcus Cooper }; 12278e07137SMarcus Cooper 12378e07137SMarcus Cooper simple-audio-card,codec { 12478e07137SMarcus Cooper sound-dai = <&spdif_out>; 12578e07137SMarcus Cooper }; 12678e07137SMarcus Cooper }; 12778e07137SMarcus Cooper 12878e07137SMarcus Cooper spdif_out: spdif-out { 12978e07137SMarcus Cooper #sound-dai-cells = <0>; 13078e07137SMarcus Cooper compatible = "linux,spdif-dit"; 13178e07137SMarcus Cooper }; 13278e07137SMarcus Cooper 1336bc37facSAndre Przywara timer { 1346bc37facSAndre Przywara compatible = "arm,armv8-timer"; 1356bc37facSAndre Przywara interrupts = <GIC_PPI 13 1366bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1376bc37facSAndre Przywara <GIC_PPI 14 1386bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1396bc37facSAndre Przywara <GIC_PPI 11 1406bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1416bc37facSAndre Przywara <GIC_PPI 10 1426bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1436bc37facSAndre Przywara }; 1446bc37facSAndre Przywara 1456bc37facSAndre Przywara soc { 1466bc37facSAndre Przywara compatible = "simple-bus"; 1476bc37facSAndre Przywara #address-cells = <1>; 1486bc37facSAndre Przywara #size-cells = <1>; 1496bc37facSAndre Przywara ranges; 1506bc37facSAndre Przywara 15179b95360SCorentin Labbe syscon: syscon@1c00000 { 15279b95360SCorentin Labbe compatible = "allwinner,sun50i-a64-system-controller", 15379b95360SCorentin Labbe "syscon"; 15479b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 15579b95360SCorentin Labbe }; 15679b95360SCorentin Labbe 157c32637e0SStefan Brüns dma: dma-controller@1c02000 { 158c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 159c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 160c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 161c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 162c32637e0SStefan Brüns dma-channels = <8>; 163c32637e0SStefan Brüns dma-requests = <27>; 164c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 165c32637e0SStefan Brüns #dma-cells = <1>; 166c32637e0SStefan Brüns }; 167c32637e0SStefan Brüns 168f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 169f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 170f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 171f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 172f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 173f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 174f3dff347SAndre Przywara reset-names = "ahb"; 175f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 17622be992fSMaxime Ripard max-frequency = <150000000>; 177f3dff347SAndre Przywara status = "disabled"; 178f3dff347SAndre Przywara #address-cells = <1>; 179f3dff347SAndre Przywara #size-cells = <0>; 180f3dff347SAndre Przywara }; 181f3dff347SAndre Przywara 182f3dff347SAndre Przywara mmc1: mmc@1c10000 { 183f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 184f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 185f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 186f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 187f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 188f3dff347SAndre Przywara reset-names = "ahb"; 189f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 19022be992fSMaxime Ripard max-frequency = <150000000>; 191f3dff347SAndre Przywara status = "disabled"; 192f3dff347SAndre Przywara #address-cells = <1>; 193f3dff347SAndre Przywara #size-cells = <0>; 194f3dff347SAndre Przywara }; 195f3dff347SAndre Przywara 196f3dff347SAndre Przywara mmc2: mmc@1c11000 { 197f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 198f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 199f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 200f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 201f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 202f3dff347SAndre Przywara reset-names = "ahb"; 203f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 20422be992fSMaxime Ripard max-frequency = <200000000>; 205f3dff347SAndre Przywara status = "disabled"; 206f3dff347SAndre Przywara #address-cells = <1>; 207f3dff347SAndre Przywara #size-cells = <0>; 208f3dff347SAndre Przywara }; 209f3dff347SAndre Przywara 210d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 211972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 212972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 213972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 214972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 215972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 216972a3ecdSIcenowy Zheng interrupt-names = "mc"; 217972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 218972a3ecdSIcenowy Zheng phy-names = "usb"; 219972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 220972a3ecdSIcenowy Zheng status = "disabled"; 221972a3ecdSIcenowy Zheng }; 222972a3ecdSIcenowy Zheng 223d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 224a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 225a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 2260d984797SIcenowy Zheng <0x01c1a800 0x4>, 227a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 228a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 2290d984797SIcenowy Zheng "pmu0", 230a004ee35SIcenowy Zheng "pmu1"; 231a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 232a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 233a004ee35SIcenowy Zheng clock-names = "usb0_phy", 234a004ee35SIcenowy Zheng "usb1_phy"; 235a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 236a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 237a004ee35SIcenowy Zheng reset-names = "usb0_reset", 238a004ee35SIcenowy Zheng "usb1_reset"; 239a004ee35SIcenowy Zheng status = "disabled"; 240a004ee35SIcenowy Zheng #phy-cells = <1>; 241a004ee35SIcenowy Zheng }; 242a004ee35SIcenowy Zheng 243d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 244dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 245dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 246dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 247dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 248dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 249dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 250dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 251dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 252dc03a047SIcenowy Zheng status = "disabled"; 253dc03a047SIcenowy Zheng }; 254dc03a047SIcenowy Zheng 255d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 256dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 257dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 258dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 259dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 260dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 261dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 262dc03a047SIcenowy Zheng status = "disabled"; 263dc03a047SIcenowy Zheng }; 264dc03a047SIcenowy Zheng 265d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 266a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 267a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 268a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 269a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 270a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 271a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 272a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 273a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 274a004ee35SIcenowy Zheng phys = <&usbphy 1>; 275a004ee35SIcenowy Zheng phy-names = "usb"; 276a004ee35SIcenowy Zheng status = "disabled"; 277a004ee35SIcenowy Zheng }; 278a004ee35SIcenowy Zheng 279d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 280a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 281a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 282a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 283a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 284a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 285a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 286a004ee35SIcenowy Zheng phys = <&usbphy 1>; 287a004ee35SIcenowy Zheng phy-names = "usb"; 288a004ee35SIcenowy Zheng status = "disabled"; 289a004ee35SIcenowy Zheng }; 290a004ee35SIcenowy Zheng 291d6c9da12SCorentin LABBE ccu: clock@1c20000 { 2926bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 2936bc37facSAndre Przywara reg = <0x01c20000 0x400>; 2946bc37facSAndre Przywara clocks = <&osc24M>, <&osc32k>; 2956bc37facSAndre Przywara clock-names = "hosc", "losc"; 2966bc37facSAndre Przywara #clock-cells = <1>; 2976bc37facSAndre Przywara #reset-cells = <1>; 2986bc37facSAndre Przywara }; 2996bc37facSAndre Przywara 3006bc37facSAndre Przywara pio: pinctrl@1c20800 { 3016bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 3026bc37facSAndre Przywara reg = <0x01c20800 0x400>; 3036bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 3046bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 3056bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 306f98121f3SArnd Bergmann clocks = <&ccu 58>; 3076bc37facSAndre Przywara gpio-controller; 3086bc37facSAndre Przywara #gpio-cells = <3>; 3096bc37facSAndre Przywara interrupt-controller; 3106bc37facSAndre Przywara #interrupt-cells = <3>; 3116bc37facSAndre Przywara 31211239fe6SHarald Geyer i2c0_pins: i2c0_pins { 31311239fe6SHarald Geyer pins = "PH0", "PH1"; 31411239fe6SHarald Geyer function = "i2c0"; 31511239fe6SHarald Geyer }; 31611239fe6SHarald Geyer 3176bc37facSAndre Przywara i2c1_pins: i2c1_pins { 3186bc37facSAndre Przywara pins = "PH2", "PH3"; 3196bc37facSAndre Przywara function = "i2c1"; 3206bc37facSAndre Przywara }; 3216bc37facSAndre Przywara 322a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 323a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 324a3e8f492SMaxime Ripard "PF4", "PF5"; 325a3e8f492SMaxime Ripard function = "mmc0"; 326a3e8f492SMaxime Ripard drive-strength = <30>; 327a3e8f492SMaxime Ripard bias-pull-up; 328a3e8f492SMaxime Ripard }; 329a3e8f492SMaxime Ripard 330a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 331a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 332a3e8f492SMaxime Ripard "PG4", "PG5"; 333a3e8f492SMaxime Ripard function = "mmc1"; 334a3e8f492SMaxime Ripard drive-strength = <30>; 335a3e8f492SMaxime Ripard bias-pull-up; 336a3e8f492SMaxime Ripard }; 337a3e8f492SMaxime Ripard 338a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 339a3e8f492SMaxime Ripard pins = "PC1", "PC5", "PC6", "PC8", "PC9", 340a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 341a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 342a3e8f492SMaxime Ripard function = "mmc2"; 343a3e8f492SMaxime Ripard drive-strength = <30>; 344a3e8f492SMaxime Ripard bias-pull-up; 345a3e8f492SMaxime Ripard }; 346a3e8f492SMaxime Ripard 347e53f67e9SCorentin Labbe rmii_pins: rmii_pins { 348e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 349e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 350e53f67e9SCorentin Labbe function = "emac"; 351e53f67e9SCorentin Labbe drive-strength = <40>; 352e53f67e9SCorentin Labbe }; 353e53f67e9SCorentin Labbe 354e53f67e9SCorentin Labbe rgmii_pins: rgmii_pins { 355e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 356e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 357e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 358e53f67e9SCorentin Labbe function = "emac"; 359e53f67e9SCorentin Labbe drive-strength = <40>; 360e53f67e9SCorentin Labbe }; 361e53f67e9SCorentin Labbe 362b399d2acSMarcus Cooper spdif_tx_pin: spdif { 363b399d2acSMarcus Cooper pins = "PH8"; 364b399d2acSMarcus Cooper function = "spdif"; 365b399d2acSMarcus Cooper }; 366b399d2acSMarcus Cooper 367b518bb15SStefan Brüns spi0_pins: spi0 { 368b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 369b518bb15SStefan Brüns function = "spi0"; 370b518bb15SStefan Brüns }; 371b518bb15SStefan Brüns 372b518bb15SStefan Brüns spi1_pins: spi1 { 373b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 374b518bb15SStefan Brüns function = "spi1"; 375b518bb15SStefan Brüns }; 376b518bb15SStefan Brüns 37792d378fbSCorentin LABBE uart0_pins_a: uart0 { 3786bc37facSAndre Przywara pins = "PB8", "PB9"; 3796bc37facSAndre Przywara function = "uart0"; 3806bc37facSAndre Przywara }; 381e7ba733dSAndre Przywara 382e7ba733dSAndre Przywara uart1_pins: uart1_pins { 383e7ba733dSAndre Przywara pins = "PG6", "PG7"; 384e7ba733dSAndre Przywara function = "uart1"; 385e7ba733dSAndre Przywara }; 386e7ba733dSAndre Przywara 387e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 388e7ba733dSAndre Przywara pins = "PG8", "PG9"; 389e7ba733dSAndre Przywara function = "uart1"; 390e7ba733dSAndre Przywara }; 39179825719SAndreas Färber 39279825719SAndreas Färber uart2_pins: uart2-pins { 39379825719SAndreas Färber pins = "PB0", "PB1"; 39479825719SAndreas Färber function = "uart2"; 39579825719SAndreas Färber }; 3962273aa16SAndreas Färber 3972273aa16SAndreas Färber uart3_pins: uart3-pins { 3982273aa16SAndreas Färber pins = "PD0", "PD1"; 3992273aa16SAndreas Färber function = "uart3"; 4002273aa16SAndreas Färber }; 4012273aa16SAndreas Färber 4022273aa16SAndreas Färber uart4_pins: uart4-pins { 4032273aa16SAndreas Färber pins = "PD2", "PD3"; 4042273aa16SAndreas Färber function = "uart4"; 4052273aa16SAndreas Färber }; 4062273aa16SAndreas Färber 4072273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 4082273aa16SAndreas Färber pins = "PD4", "PD5"; 4092273aa16SAndreas Färber function = "uart4"; 4102273aa16SAndreas Färber }; 4116bc37facSAndre Przywara }; 4126bc37facSAndre Przywara 413b399d2acSMarcus Cooper spdif: spdif@1c21000 { 414b399d2acSMarcus Cooper #sound-dai-cells = <0>; 415b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 416b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 417b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 418b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 419b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 420b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 421b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 422b399d2acSMarcus Cooper dmas = <&dma 2>; 423b399d2acSMarcus Cooper dma-names = "tx"; 424b399d2acSMarcus Cooper pinctrl-names = "default"; 425b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 426b399d2acSMarcus Cooper status = "disabled"; 427b399d2acSMarcus Cooper }; 428b399d2acSMarcus Cooper 4291c92c009SMarcus Cooper i2s0: i2s@1c22000 { 4301c92c009SMarcus Cooper #sound-dai-cells = <0>; 4311c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 4321c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 4331c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 4341c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4351c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 4361c92c009SMarcus Cooper clock-names = "apb", "mod"; 4371c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 4381c92c009SMarcus Cooper dma-names = "rx", "tx"; 4391c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 4401c92c009SMarcus Cooper status = "disabled"; 4411c92c009SMarcus Cooper }; 4421c92c009SMarcus Cooper 4431c92c009SMarcus Cooper i2s1: i2s@1c22400 { 4441c92c009SMarcus Cooper #sound-dai-cells = <0>; 4451c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 4461c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 4471c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 4481c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4491c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 4501c92c009SMarcus Cooper clock-names = "apb", "mod"; 4511c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 4521c92c009SMarcus Cooper dma-names = "rx", "tx"; 4531c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 4541c92c009SMarcus Cooper status = "disabled"; 4551c92c009SMarcus Cooper }; 4561c92c009SMarcus Cooper 4576bc37facSAndre Przywara uart0: serial@1c28000 { 4586bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 4596bc37facSAndre Przywara reg = <0x01c28000 0x400>; 4606bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4616bc37facSAndre Przywara reg-shift = <2>; 4626bc37facSAndre Przywara reg-io-width = <4>; 463494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 464494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 4656bc37facSAndre Przywara status = "disabled"; 4666bc37facSAndre Przywara }; 4676bc37facSAndre Przywara 4686bc37facSAndre Przywara uart1: serial@1c28400 { 4696bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 4706bc37facSAndre Przywara reg = <0x01c28400 0x400>; 4716bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 4726bc37facSAndre Przywara reg-shift = <2>; 4736bc37facSAndre Przywara reg-io-width = <4>; 474494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 475494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 4766bc37facSAndre Przywara status = "disabled"; 4776bc37facSAndre Przywara }; 4786bc37facSAndre Przywara 4796bc37facSAndre Przywara uart2: serial@1c28800 { 4806bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 4816bc37facSAndre Przywara reg = <0x01c28800 0x400>; 4826bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 4836bc37facSAndre Przywara reg-shift = <2>; 4846bc37facSAndre Przywara reg-io-width = <4>; 485494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 486494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 4876bc37facSAndre Przywara status = "disabled"; 4886bc37facSAndre Przywara }; 4896bc37facSAndre Przywara 4906bc37facSAndre Przywara uart3: serial@1c28c00 { 4916bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 4926bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 4936bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 4946bc37facSAndre Przywara reg-shift = <2>; 4956bc37facSAndre Przywara reg-io-width = <4>; 496494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 497494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 4986bc37facSAndre Przywara status = "disabled"; 4996bc37facSAndre Przywara }; 5006bc37facSAndre Przywara 5016bc37facSAndre Przywara uart4: serial@1c29000 { 5026bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5036bc37facSAndre Przywara reg = <0x01c29000 0x400>; 5046bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 5056bc37facSAndre Przywara reg-shift = <2>; 5066bc37facSAndre Przywara reg-io-width = <4>; 507494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 508494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 5096bc37facSAndre Przywara status = "disabled"; 5106bc37facSAndre Przywara }; 5116bc37facSAndre Przywara 5126bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 5136bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5146bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 5156bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 516494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 517494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 5186bc37facSAndre Przywara status = "disabled"; 5196bc37facSAndre Przywara #address-cells = <1>; 5206bc37facSAndre Przywara #size-cells = <0>; 5216bc37facSAndre Przywara }; 5226bc37facSAndre Przywara 5236bc37facSAndre Przywara i2c1: i2c@1c2b000 { 5246bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5256bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 5266bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 527494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 528494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 5296bc37facSAndre Przywara status = "disabled"; 5306bc37facSAndre Przywara #address-cells = <1>; 5316bc37facSAndre Przywara #size-cells = <0>; 5326bc37facSAndre Przywara }; 5336bc37facSAndre Przywara 5346bc37facSAndre Przywara i2c2: i2c@1c2b400 { 5356bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5366bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 5376bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 538494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 539494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 5406bc37facSAndre Przywara status = "disabled"; 5416bc37facSAndre Przywara #address-cells = <1>; 5426bc37facSAndre Przywara #size-cells = <0>; 5436bc37facSAndre Przywara }; 5446bc37facSAndre Przywara 545b518bb15SStefan Brüns 546d6c9da12SCorentin LABBE spi0: spi@1c68000 { 547b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 548b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 549b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 550b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 551b518bb15SStefan Brüns clock-names = "ahb", "mod"; 55206c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 55306c1258aSStefan Brüns dma-names = "rx", "tx"; 554b518bb15SStefan Brüns pinctrl-names = "default"; 555b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 556b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 557b518bb15SStefan Brüns status = "disabled"; 558b518bb15SStefan Brüns num-cs = <1>; 559b518bb15SStefan Brüns #address-cells = <1>; 560b518bb15SStefan Brüns #size-cells = <0>; 561b518bb15SStefan Brüns }; 562b518bb15SStefan Brüns 563d6c9da12SCorentin LABBE spi1: spi@1c69000 { 564b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 565b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 566b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 567b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 568b518bb15SStefan Brüns clock-names = "ahb", "mod"; 56906c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 57006c1258aSStefan Brüns dma-names = "rx", "tx"; 571b518bb15SStefan Brüns pinctrl-names = "default"; 572b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 573b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 574b518bb15SStefan Brüns status = "disabled"; 575b518bb15SStefan Brüns num-cs = <1>; 576b518bb15SStefan Brüns #address-cells = <1>; 577b518bb15SStefan Brüns #size-cells = <0>; 578b518bb15SStefan Brüns }; 579b518bb15SStefan Brüns 58094f44288SCorentin Labbe emac: ethernet@1c30000 { 58194f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 58294f44288SCorentin Labbe syscon = <&syscon>; 58394f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 58494f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 58594f44288SCorentin Labbe interrupt-names = "macirq"; 58694f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 58794f44288SCorentin Labbe reset-names = "stmmaceth"; 58894f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 58994f44288SCorentin Labbe clock-names = "stmmaceth"; 59094f44288SCorentin Labbe status = "disabled"; 59194f44288SCorentin Labbe #address-cells = <1>; 59294f44288SCorentin Labbe #size-cells = <0>; 59394f44288SCorentin Labbe 59494f44288SCorentin Labbe mdio: mdio { 59516416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 59694f44288SCorentin Labbe #address-cells = <1>; 59794f44288SCorentin Labbe #size-cells = <0>; 59894f44288SCorentin Labbe }; 59994f44288SCorentin Labbe }; 60094f44288SCorentin Labbe 6016bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 6026bc37facSAndre Przywara compatible = "arm,gic-400"; 6036bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 6046bc37facSAndre Przywara <0x01c82000 0x2000>, 6056bc37facSAndre Przywara <0x01c84000 0x2000>, 6066bc37facSAndre Przywara <0x01c86000 0x2000>; 6076bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 6086bc37facSAndre Przywara interrupt-controller; 6096bc37facSAndre Przywara #interrupt-cells = <3>; 6106bc37facSAndre Przywara }; 6116bc37facSAndre Przywara 6126bc37facSAndre Przywara rtc: rtc@1f00000 { 6136bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-rtc"; 6146bc37facSAndre Przywara reg = <0x01f00000 0x54>; 6156bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 6166bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 6176bc37facSAndre Przywara }; 618791a9e00SIcenowy Zheng 619535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 620535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 621535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 622535ca508SIcenowy Zheng interrupt-controller; 623535ca508SIcenowy Zheng #interrupt-cells = <2>; 624535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 625535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 626535ca508SIcenowy Zheng }; 627535ca508SIcenowy Zheng 628791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 629791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 630791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 631f74994a9SChen-Yu Tsai clocks = <&osc24M>, <&osc32k>, <&iosc>, 632f74994a9SChen-Yu Tsai <&ccu 11>; 633f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 634791a9e00SIcenowy Zheng #clock-cells = <1>; 635791a9e00SIcenowy Zheng #reset-cells = <1>; 636791a9e00SIcenowy Zheng }; 637ec427905SIcenowy Zheng 638d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 639ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 640ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 641ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 642494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 643ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 644ec427905SIcenowy Zheng gpio-controller; 645ec427905SIcenowy Zheng #gpio-cells = <3>; 646ec427905SIcenowy Zheng interrupt-controller; 647ec427905SIcenowy Zheng #interrupt-cells = <3>; 6483b38fdedSIcenowy Zheng 64992d378fbSCorentin LABBE r_rsb_pins: rsb { 6503b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 6513b38fdedSIcenowy Zheng function = "s_rsb"; 6523b38fdedSIcenowy Zheng }; 6533b38fdedSIcenowy Zheng }; 6543b38fdedSIcenowy Zheng 6553b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 6563b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 6573b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 6583b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 6593b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 6603b38fdedSIcenowy Zheng clock-frequency = <3000000>; 6613b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 6623b38fdedSIcenowy Zheng pinctrl-names = "default"; 6633b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 6643b38fdedSIcenowy Zheng status = "disabled"; 6653b38fdedSIcenowy Zheng #address-cells = <1>; 6663b38fdedSIcenowy Zheng #size-cells = <0>; 667ec427905SIcenowy Zheng }; 668d4185043SHarald Geyer 669d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 670d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 671d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 672d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 673d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 674d4185043SHarald Geyer }; 6756bc37facSAndre Przywara }; 6766bc37facSAndre Przywara}; 677