1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd. 3cabbaed7SClément Péron// based on the Allwinner H3 dtsi: 4cabbaed7SClément Péron// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara 6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 72c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 8494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 96bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 10a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 112c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 12871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 136bc37facSAndre Przywara 146bc37facSAndre Przywara/ { 156bc37facSAndre Przywara interrupt-parent = <&gic>; 166bc37facSAndre Przywara #address-cells = <1>; 176bc37facSAndre Przywara #size-cells = <1>; 186bc37facSAndre Przywara 19c1cff65fSHarald Geyer chosen { 20c1cff65fSHarald Geyer #address-cells = <1>; 21c1cff65fSHarald Geyer #size-cells = <1>; 22c1cff65fSHarald Geyer ranges; 23c1cff65fSHarald Geyer 24c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 25c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 26c1cff65fSHarald Geyer "simple-framebuffer"; 27c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 28c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 292c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 30c1cff65fSHarald Geyer status = "disabled"; 31c1cff65fSHarald Geyer }; 32fca63f58SIcenowy Zheng 33fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 34fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 35fca63f58SIcenowy Zheng "simple-framebuffer"; 36fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 37fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 38fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 39fca63f58SIcenowy Zheng status = "disabled"; 40fca63f58SIcenowy Zheng }; 41c1cff65fSHarald Geyer }; 42c1cff65fSHarald Geyer 436bc37facSAndre Przywara cpus { 446bc37facSAndre Przywara #address-cells = <1>; 456bc37facSAndre Przywara #size-cells = <0>; 466bc37facSAndre Przywara 476bc37facSAndre Przywara cpu0: cpu@0 { 4831af04cdSRob Herring compatible = "arm,cortex-a53"; 496bc37facSAndre Przywara device_type = "cpu"; 506bc37facSAndre Przywara reg = <0>; 516bc37facSAndre Przywara enable-method = "psci"; 5239defc81SAndre Przywara next-level-cache = <&L2>; 536bc37facSAndre Przywara }; 546bc37facSAndre Przywara 556bc37facSAndre Przywara cpu1: cpu@1 { 5631af04cdSRob Herring compatible = "arm,cortex-a53"; 576bc37facSAndre Przywara device_type = "cpu"; 586bc37facSAndre Przywara reg = <1>; 596bc37facSAndre Przywara enable-method = "psci"; 6039defc81SAndre Przywara next-level-cache = <&L2>; 616bc37facSAndre Przywara }; 626bc37facSAndre Przywara 636bc37facSAndre Przywara cpu2: cpu@2 { 6431af04cdSRob Herring compatible = "arm,cortex-a53"; 656bc37facSAndre Przywara device_type = "cpu"; 666bc37facSAndre Przywara reg = <2>; 676bc37facSAndre Przywara enable-method = "psci"; 6839defc81SAndre Przywara next-level-cache = <&L2>; 696bc37facSAndre Przywara }; 706bc37facSAndre Przywara 716bc37facSAndre Przywara cpu3: cpu@3 { 7231af04cdSRob Herring compatible = "arm,cortex-a53"; 736bc37facSAndre Przywara device_type = "cpu"; 746bc37facSAndre Przywara reg = <3>; 756bc37facSAndre Przywara enable-method = "psci"; 7639defc81SAndre Przywara next-level-cache = <&L2>; 7739defc81SAndre Przywara }; 7839defc81SAndre Przywara 7939defc81SAndre Przywara L2: l2-cache { 8039defc81SAndre Przywara compatible = "cache"; 8139defc81SAndre Przywara cache-level = <2>; 826bc37facSAndre Przywara }; 836bc37facSAndre Przywara }; 846bc37facSAndre Przywara 85e85f28e0SJagan Teki de: display-engine { 86e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 87e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 88e85f28e0SJagan Teki <&mixer1>; 89e85f28e0SJagan Teki status = "disabled"; 90e85f28e0SJagan Teki }; 91e85f28e0SJagan Teki 926bc37facSAndre Przywara osc24M: osc24M_clk { 936bc37facSAndre Przywara #clock-cells = <0>; 946bc37facSAndre Przywara compatible = "fixed-clock"; 956bc37facSAndre Przywara clock-frequency = <24000000>; 966bc37facSAndre Przywara clock-output-names = "osc24M"; 976bc37facSAndre Przywara }; 986bc37facSAndre Przywara 996bc37facSAndre Przywara osc32k: osc32k_clk { 1006bc37facSAndre Przywara #clock-cells = <0>; 1016bc37facSAndre Przywara compatible = "fixed-clock"; 1026bc37facSAndre Przywara clock-frequency = <32768>; 10344ff3cafSChen-Yu Tsai clock-output-names = "ext-osc32k"; 104791a9e00SIcenowy Zheng }; 105791a9e00SIcenowy Zheng 10634a97fccSHarald Geyer pmu { 10734a97fccSHarald Geyer compatible = "arm,cortex-a53-pmu"; 1086b832a14SAndre Przywara interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1096b832a14SAndre Przywara <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1106b832a14SAndre Przywara <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1116b832a14SAndre Przywara <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 11234a97fccSHarald Geyer interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 11334a97fccSHarald Geyer }; 11434a97fccSHarald Geyer 1156bc37facSAndre Przywara psci { 1166bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1176bc37facSAndre Przywara method = "smc"; 1186bc37facSAndre Przywara }; 1196bc37facSAndre Przywara 120ec4a9540SVasily Khoruzhick sound: sound { 121ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 122ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 123ec4a9540SVasily Khoruzhick simple-audio-card,format = "i2s"; 124ec4a9540SVasily Khoruzhick simple-audio-card,frame-master = <&cpudai>; 125ec4a9540SVasily Khoruzhick simple-audio-card,bitclock-master = <&cpudai>; 126ec4a9540SVasily Khoruzhick simple-audio-card,mclk-fs = <128>; 127ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 128ec4a9540SVasily Khoruzhick simple-audio-card,routing = 129ec4a9540SVasily Khoruzhick "Left DAC", "AIF1 Slot 0 Left", 130ec4a9540SVasily Khoruzhick "Right DAC", "AIF1 Slot 0 Right", 131ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Left ADC", "Left ADC", 132ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Right ADC", "Right ADC"; 133ec4a9540SVasily Khoruzhick status = "disabled"; 134ec4a9540SVasily Khoruzhick 135ec4a9540SVasily Khoruzhick cpudai: simple-audio-card,cpu { 136ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 137ec4a9540SVasily Khoruzhick }; 138ec4a9540SVasily Khoruzhick 139ec4a9540SVasily Khoruzhick link_codec: simple-audio-card,codec { 140ec4a9540SVasily Khoruzhick sound-dai = <&codec>; 141ec4a9540SVasily Khoruzhick }; 142ec4a9540SVasily Khoruzhick }; 143ec4a9540SVasily Khoruzhick 14478e07137SMarcus Cooper sound_spdif { 14578e07137SMarcus Cooper compatible = "simple-audio-card"; 14678e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 14778e07137SMarcus Cooper 14878e07137SMarcus Cooper simple-audio-card,cpu { 14978e07137SMarcus Cooper sound-dai = <&spdif>; 15078e07137SMarcus Cooper }; 15178e07137SMarcus Cooper 15278e07137SMarcus Cooper simple-audio-card,codec { 15378e07137SMarcus Cooper sound-dai = <&spdif_out>; 15478e07137SMarcus Cooper }; 15578e07137SMarcus Cooper }; 15678e07137SMarcus Cooper 15778e07137SMarcus Cooper spdif_out: spdif-out { 15878e07137SMarcus Cooper #sound-dai-cells = <0>; 15978e07137SMarcus Cooper compatible = "linux,spdif-dit"; 16078e07137SMarcus Cooper }; 16178e07137SMarcus Cooper 1626bc37facSAndre Przywara timer { 1636bc37facSAndre Przywara compatible = "arm,armv8-timer"; 16455ec26d6SSamuel Holland allwinner,erratum-unknown1; 1656bc37facSAndre Przywara interrupts = <GIC_PPI 13 1666bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1676bc37facSAndre Przywara <GIC_PPI 14 1686bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1696bc37facSAndre Przywara <GIC_PPI 11 1706bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1716bc37facSAndre Przywara <GIC_PPI 10 1726bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1736bc37facSAndre Przywara }; 1746bc37facSAndre Przywara 1756bc37facSAndre Przywara soc { 1766bc37facSAndre Przywara compatible = "simple-bus"; 1776bc37facSAndre Przywara #address-cells = <1>; 1786bc37facSAndre Przywara #size-cells = <1>; 1796bc37facSAndre Przywara ranges; 1806bc37facSAndre Przywara 181275b6317SMaxime Ripard bus@1000000 { 1822c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 1832c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 1842c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 1852c796fc8SIcenowy Zheng #address-cells = <1>; 1862c796fc8SIcenowy Zheng #size-cells = <1>; 1872c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 1882c796fc8SIcenowy Zheng 1892c796fc8SIcenowy Zheng display_clocks: clock@0 { 1902c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 1912c796fc8SIcenowy Zheng reg = <0x0 0x100000>; 1925ea40f71SMaxime Ripard clocks = <&ccu CLK_BUS_DE>, 1935ea40f71SMaxime Ripard <&ccu CLK_DE>; 1945ea40f71SMaxime Ripard clock-names = "bus", 1955ea40f71SMaxime Ripard "mod"; 1962c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 1972c796fc8SIcenowy Zheng #clock-cells = <1>; 1982c796fc8SIcenowy Zheng #reset-cells = <1>; 1992c796fc8SIcenowy Zheng }; 200e85f28e0SJagan Teki 201e85f28e0SJagan Teki mixer0: mixer@100000 { 202e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 203e85f28e0SJagan Teki reg = <0x100000 0x100000>; 204e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 205e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 206e85f28e0SJagan Teki clock-names = "bus", 207e85f28e0SJagan Teki "mod"; 208e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 209e85f28e0SJagan Teki 210e85f28e0SJagan Teki ports { 211e85f28e0SJagan Teki #address-cells = <1>; 212e85f28e0SJagan Teki #size-cells = <0>; 213e85f28e0SJagan Teki 214e85f28e0SJagan Teki mixer0_out: port@1 { 215a7f7047fSMaxime Ripard #address-cells = <1>; 216a7f7047fSMaxime Ripard #size-cells = <0>; 217e85f28e0SJagan Teki reg = <1>; 218e85f28e0SJagan Teki 219a7f7047fSMaxime Ripard mixer0_out_tcon0: endpoint@0 { 220a7f7047fSMaxime Ripard reg = <0>; 221e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 222e85f28e0SJagan Teki }; 223a7f7047fSMaxime Ripard 224a7f7047fSMaxime Ripard mixer0_out_tcon1: endpoint@1 { 225a7f7047fSMaxime Ripard reg = <1>; 226a7f7047fSMaxime Ripard remote-endpoint = <&tcon1_in_mixer0>; 227a7f7047fSMaxime Ripard }; 228e85f28e0SJagan Teki }; 229e85f28e0SJagan Teki }; 230e85f28e0SJagan Teki }; 231e85f28e0SJagan Teki 232e85f28e0SJagan Teki mixer1: mixer@200000 { 233e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 234e85f28e0SJagan Teki reg = <0x200000 0x100000>; 235e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 236e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 237e85f28e0SJagan Teki clock-names = "bus", 238e85f28e0SJagan Teki "mod"; 239e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 240e85f28e0SJagan Teki 241e85f28e0SJagan Teki ports { 242e85f28e0SJagan Teki #address-cells = <1>; 243e85f28e0SJagan Teki #size-cells = <0>; 244e85f28e0SJagan Teki 245e85f28e0SJagan Teki mixer1_out: port@1 { 246d41a43a0SMaxime Ripard #address-cells = <1>; 247d41a43a0SMaxime Ripard #size-cells = <0>; 248e85f28e0SJagan Teki reg = <1>; 249e85f28e0SJagan Teki 250a7f7047fSMaxime Ripard mixer1_out_tcon0: endpoint@0 { 251a7f7047fSMaxime Ripard reg = <0>; 252a7f7047fSMaxime Ripard remote-endpoint = <&tcon0_in_mixer1>; 253a7f7047fSMaxime Ripard }; 254a7f7047fSMaxime Ripard 255a7f7047fSMaxime Ripard mixer1_out_tcon1: endpoint@1 { 256a7f7047fSMaxime Ripard reg = <1>; 257e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 258e85f28e0SJagan Teki }; 259e85f28e0SJagan Teki }; 260e85f28e0SJagan Teki }; 261e85f28e0SJagan Teki }; 2622c796fc8SIcenowy Zheng }; 2632c796fc8SIcenowy Zheng 26479b95360SCorentin Labbe syscon: syscon@1c00000 { 2651f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 26679b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 2671f1f5183SIcenowy Zheng #address-cells = <1>; 2681f1f5183SIcenowy Zheng #size-cells = <1>; 2691f1f5183SIcenowy Zheng ranges; 2701f1f5183SIcenowy Zheng 2711f1f5183SIcenowy Zheng sram_c: sram@18000 { 2721f1f5183SIcenowy Zheng compatible = "mmio-sram"; 2731f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 2741f1f5183SIcenowy Zheng #address-cells = <1>; 2751f1f5183SIcenowy Zheng #size-cells = <1>; 2761f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 2771f1f5183SIcenowy Zheng 2781f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 2791f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 2801f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 2811f1f5183SIcenowy Zheng }; 2821f1f5183SIcenowy Zheng }; 283106deea8SPaul Kocialkowski 284106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 285106deea8SPaul Kocialkowski compatible = "mmio-sram"; 286106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 287106deea8SPaul Kocialkowski #address-cells = <1>; 288106deea8SPaul Kocialkowski #size-cells = <1>; 289106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 290106deea8SPaul Kocialkowski 291106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 292106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 293106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 294106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 295106deea8SPaul Kocialkowski }; 296106deea8SPaul Kocialkowski }; 29779b95360SCorentin Labbe }; 29879b95360SCorentin Labbe 299c32637e0SStefan Brüns dma: dma-controller@1c02000 { 300c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 301c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 302c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 303c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 304c32637e0SStefan Brüns dma-channels = <8>; 305c32637e0SStefan Brüns dma-requests = <27>; 306c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 307c32637e0SStefan Brüns #dma-cells = <1>; 308c32637e0SStefan Brüns }; 309c32637e0SStefan Brüns 310e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 311e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 312e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 313e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 314e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 315e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 316e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 317e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 31826c609d5SMaxime Ripard #clock-cells = <0>; 319e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 320e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 321e85f28e0SJagan Teki 322e85f28e0SJagan Teki ports { 323e85f28e0SJagan Teki #address-cells = <1>; 324e85f28e0SJagan Teki #size-cells = <0>; 325e85f28e0SJagan Teki 326e85f28e0SJagan Teki tcon0_in: port@0 { 327e85f28e0SJagan Teki #address-cells = <1>; 328e85f28e0SJagan Teki #size-cells = <0>; 329e85f28e0SJagan Teki reg = <0>; 330e85f28e0SJagan Teki 331e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 332e85f28e0SJagan Teki reg = <0>; 333e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 334e85f28e0SJagan Teki }; 335a7f7047fSMaxime Ripard 336a7f7047fSMaxime Ripard tcon0_in_mixer1: endpoint@1 { 337a7f7047fSMaxime Ripard reg = <1>; 338d41a43a0SMaxime Ripard remote-endpoint = <&mixer1_out_tcon0>; 339a7f7047fSMaxime Ripard }; 340e85f28e0SJagan Teki }; 341e85f28e0SJagan Teki 342e85f28e0SJagan Teki tcon0_out: port@1 { 343e85f28e0SJagan Teki #address-cells = <1>; 344e85f28e0SJagan Teki #size-cells = <0>; 345e85f28e0SJagan Teki reg = <1>; 346e85f28e0SJagan Teki }; 347e85f28e0SJagan Teki }; 348e85f28e0SJagan Teki }; 349e85f28e0SJagan Teki 350e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 351e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 352e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 353e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 354e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 355e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 356e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 357e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 358e85f28e0SJagan Teki reset-names = "lcd"; 359e85f28e0SJagan Teki 360e85f28e0SJagan Teki ports { 361e85f28e0SJagan Teki #address-cells = <1>; 362e85f28e0SJagan Teki #size-cells = <0>; 363e85f28e0SJagan Teki 364e85f28e0SJagan Teki tcon1_in: port@0 { 365a7f7047fSMaxime Ripard #address-cells = <1>; 366a7f7047fSMaxime Ripard #size-cells = <0>; 367e85f28e0SJagan Teki reg = <0>; 368e85f28e0SJagan Teki 369a7f7047fSMaxime Ripard tcon1_in_mixer0: endpoint@0 { 370a7f7047fSMaxime Ripard reg = <0>; 371a7f7047fSMaxime Ripard remote-endpoint = <&mixer0_out_tcon1>; 372a7f7047fSMaxime Ripard }; 373a7f7047fSMaxime Ripard 374a7f7047fSMaxime Ripard tcon1_in_mixer1: endpoint@1 { 375a7f7047fSMaxime Ripard reg = <1>; 376e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 377e85f28e0SJagan Teki }; 378e85f28e0SJagan Teki }; 379e85f28e0SJagan Teki 380e85f28e0SJagan Teki tcon1_out: port@1 { 381e85f28e0SJagan Teki #address-cells = <1>; 382e85f28e0SJagan Teki #size-cells = <0>; 383e85f28e0SJagan Teki reg = <1>; 384e85f28e0SJagan Teki 385e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 386e85f28e0SJagan Teki reg = <1>; 387e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 388e85f28e0SJagan Teki }; 389e85f28e0SJagan Teki }; 390e85f28e0SJagan Teki }; 391e85f28e0SJagan Teki }; 392e85f28e0SJagan Teki 393d60ce247SPaul Kocialkowski video-codec@1c0e000 { 3944ab88516SPaul Kocialkowski compatible = "allwinner,sun50i-a64-video-engine"; 395d60ce247SPaul Kocialkowski reg = <0x01c0e000 0x1000>; 396d60ce247SPaul Kocialkowski clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 397d60ce247SPaul Kocialkowski <&ccu CLK_DRAM_VE>; 398d60ce247SPaul Kocialkowski clock-names = "ahb", "mod", "ram"; 399d60ce247SPaul Kocialkowski resets = <&ccu RST_BUS_VE>; 400d60ce247SPaul Kocialkowski interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 401d60ce247SPaul Kocialkowski allwinner,sram = <&ve_sram 1>; 402d60ce247SPaul Kocialkowski }; 403d60ce247SPaul Kocialkowski 404f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 405f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 406f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 407f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 408f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 409f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 410f3dff347SAndre Przywara reset-names = "ahb"; 411f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 41222be992fSMaxime Ripard max-frequency = <150000000>; 413f3dff347SAndre Przywara status = "disabled"; 414f3dff347SAndre Przywara #address-cells = <1>; 415f3dff347SAndre Przywara #size-cells = <0>; 416f3dff347SAndre Przywara }; 417f3dff347SAndre Przywara 418f3dff347SAndre Przywara mmc1: mmc@1c10000 { 419f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 420f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 421f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 422f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 423f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 424f3dff347SAndre Przywara reset-names = "ahb"; 425f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 42622be992fSMaxime Ripard max-frequency = <150000000>; 427f3dff347SAndre Przywara status = "disabled"; 428f3dff347SAndre Przywara #address-cells = <1>; 429f3dff347SAndre Przywara #size-cells = <0>; 430f3dff347SAndre Przywara }; 431f3dff347SAndre Przywara 432f3dff347SAndre Przywara mmc2: mmc@1c11000 { 433f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 434f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 435f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 436f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 437f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 438f3dff347SAndre Przywara reset-names = "ahb"; 439f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 44022be992fSMaxime Ripard max-frequency = <200000000>; 441f3dff347SAndre Przywara status = "disabled"; 442f3dff347SAndre Przywara #address-cells = <1>; 443f3dff347SAndre Przywara #size-cells = <0>; 444f3dff347SAndre Przywara }; 445f3dff347SAndre Przywara 446ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 447ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 448ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 449ac947b17SEmmanuel Vadot }; 450ac947b17SEmmanuel Vadot 4510f5fc158SCorentin Labbe crypto: crypto@1c15000 { 4520f5fc158SCorentin Labbe compatible = "allwinner,sun50i-a64-crypto"; 4530f5fc158SCorentin Labbe reg = <0x01c15000 0x1000>; 4540f5fc158SCorentin Labbe interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 4550f5fc158SCorentin Labbe clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 4560f5fc158SCorentin Labbe clock-names = "bus", "mod"; 4570f5fc158SCorentin Labbe resets = <&ccu RST_BUS_CE>; 4580f5fc158SCorentin Labbe }; 4590f5fc158SCorentin Labbe 460d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 461972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 462972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 463972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 464972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 465972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 466972a3ecdSIcenowy Zheng interrupt-names = "mc"; 467972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 468972a3ecdSIcenowy Zheng phy-names = "usb"; 469972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 4700973c06bSMaxime Ripard dr_mode = "otg"; 471972a3ecdSIcenowy Zheng status = "disabled"; 472972a3ecdSIcenowy Zheng }; 473972a3ecdSIcenowy Zheng 474d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 475a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 476a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 4770d984797SIcenowy Zheng <0x01c1a800 0x4>, 478a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 479a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 4800d984797SIcenowy Zheng "pmu0", 481a004ee35SIcenowy Zheng "pmu1"; 482a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 483a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 484a004ee35SIcenowy Zheng clock-names = "usb0_phy", 485a004ee35SIcenowy Zheng "usb1_phy"; 486a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 487a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 488a004ee35SIcenowy Zheng reset-names = "usb0_reset", 489a004ee35SIcenowy Zheng "usb1_reset"; 490a004ee35SIcenowy Zheng status = "disabled"; 491a004ee35SIcenowy Zheng #phy-cells = <1>; 492a004ee35SIcenowy Zheng }; 493a004ee35SIcenowy Zheng 494d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 495dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 496dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 497dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 498dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 499dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 500dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 501dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 502dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 503dc03a047SIcenowy Zheng status = "disabled"; 504dc03a047SIcenowy Zheng }; 505dc03a047SIcenowy Zheng 506d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 507dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 508dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 509dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 510dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 511dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 512dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 513dc03a047SIcenowy Zheng status = "disabled"; 514dc03a047SIcenowy Zheng }; 515dc03a047SIcenowy Zheng 516d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 517a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 518a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 519a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 520a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 521a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 522a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 523a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 524a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 525a004ee35SIcenowy Zheng phys = <&usbphy 1>; 526e6064cf4SMaxime Ripard phy-names = "usb"; 527a004ee35SIcenowy Zheng status = "disabled"; 528a004ee35SIcenowy Zheng }; 529a004ee35SIcenowy Zheng 530d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 531a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 532a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 533a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 534a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 535a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 536a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 537a004ee35SIcenowy Zheng phys = <&usbphy 1>; 538e6064cf4SMaxime Ripard phy-names = "usb"; 539a004ee35SIcenowy Zheng status = "disabled"; 540a004ee35SIcenowy Zheng }; 541a004ee35SIcenowy Zheng 542d6c9da12SCorentin LABBE ccu: clock@1c20000 { 5436bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 5446bc37facSAndre Przywara reg = <0x01c20000 0x400>; 54544ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>; 5466bc37facSAndre Przywara clock-names = "hosc", "losc"; 5476bc37facSAndre Przywara #clock-cells = <1>; 5486bc37facSAndre Przywara #reset-cells = <1>; 5496bc37facSAndre Przywara }; 5506bc37facSAndre Przywara 5516bc37facSAndre Przywara pio: pinctrl@1c20800 { 5526bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 5536bc37facSAndre Przywara reg = <0x01c20800 0x400>; 5546bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 5556bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 5566bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 557562bf196SMaxime Ripard clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 558562bf196SMaxime Ripard clock-names = "apb", "hosc", "losc"; 5596bc37facSAndre Przywara gpio-controller; 5606bc37facSAndre Przywara #gpio-cells = <3>; 5616bc37facSAndre Przywara interrupt-controller; 5626bc37facSAndre Przywara #interrupt-cells = <3>; 5636bc37facSAndre Przywara 564ff29f13eSJagan Teki csi_pins: csi-pins { 565ff29f13eSJagan Teki pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 566ff29f13eSJagan Teki "PE7", "PE8", "PE9", "PE10", "PE11"; 567ff29f13eSJagan Teki function = "csi"; 568ff29f13eSJagan Teki }; 569ff29f13eSJagan Teki 570f7056b28SJagan Teki /omit-if-no-ref/ 571f7056b28SJagan Teki csi_mclk_pin: csi-mclk-pin { 572f7056b28SJagan Teki pins = "PE1"; 573f7056b28SJagan Teki function = "csi"; 574f7056b28SJagan Teki }; 575f7056b28SJagan Teki 57654eac67bSMaxime Ripard i2c0_pins: i2c0-pins { 57711239fe6SHarald Geyer pins = "PH0", "PH1"; 57811239fe6SHarald Geyer function = "i2c0"; 57911239fe6SHarald Geyer }; 58011239fe6SHarald Geyer 58154eac67bSMaxime Ripard i2c1_pins: i2c1-pins { 5826bc37facSAndre Przywara pins = "PH2", "PH3"; 5836bc37facSAndre Przywara function = "i2c1"; 5846bc37facSAndre Przywara }; 5856bc37facSAndre Przywara 586c478a12eSIcenowy Zheng /omit-if-no-ref/ 587c478a12eSIcenowy Zheng lcd_rgb666_pins: lcd-rgb666-pins { 588c478a12eSIcenowy Zheng pins = "PD0", "PD1", "PD2", "PD3", "PD4", 589c478a12eSIcenowy Zheng "PD5", "PD6", "PD7", "PD8", "PD9", 590c478a12eSIcenowy Zheng "PD10", "PD11", "PD12", "PD13", 591c478a12eSIcenowy Zheng "PD14", "PD15", "PD16", "PD17", 592c478a12eSIcenowy Zheng "PD18", "PD19", "PD20", "PD21"; 593c478a12eSIcenowy Zheng function = "lcd0"; 594c478a12eSIcenowy Zheng }; 595c478a12eSIcenowy Zheng 596a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 597a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 598a3e8f492SMaxime Ripard "PF4", "PF5"; 599a3e8f492SMaxime Ripard function = "mmc0"; 600a3e8f492SMaxime Ripard drive-strength = <30>; 601a3e8f492SMaxime Ripard bias-pull-up; 602a3e8f492SMaxime Ripard }; 603a3e8f492SMaxime Ripard 604a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 605a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 606a3e8f492SMaxime Ripard "PG4", "PG5"; 607a3e8f492SMaxime Ripard function = "mmc1"; 608a3e8f492SMaxime Ripard drive-strength = <30>; 609a3e8f492SMaxime Ripard bias-pull-up; 610a3e8f492SMaxime Ripard }; 611a3e8f492SMaxime Ripard 612a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 613fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 614a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 615a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 616a3e8f492SMaxime Ripard function = "mmc2"; 617a3e8f492SMaxime Ripard drive-strength = <30>; 618a3e8f492SMaxime Ripard bias-pull-up; 619a3e8f492SMaxime Ripard }; 620a3e8f492SMaxime Ripard 621fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 622fa59dd2eSChen-Yu Tsai pins = "PC1"; 623fa59dd2eSChen-Yu Tsai function = "mmc2"; 624fa59dd2eSChen-Yu Tsai drive-strength = <30>; 625fa59dd2eSChen-Yu Tsai bias-pull-up; 626fa59dd2eSChen-Yu Tsai }; 627fa59dd2eSChen-Yu Tsai 62854eac67bSMaxime Ripard pwm_pin: pwm-pin { 629b5df280bSAndre Przywara pins = "PD22"; 630b5df280bSAndre Przywara function = "pwm"; 631b5df280bSAndre Przywara }; 632b5df280bSAndre Przywara 63354eac67bSMaxime Ripard rmii_pins: rmii-pins { 634e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 635e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 636e53f67e9SCorentin Labbe function = "emac"; 637e53f67e9SCorentin Labbe drive-strength = <40>; 638e53f67e9SCorentin Labbe }; 639e53f67e9SCorentin Labbe 64054eac67bSMaxime Ripard rgmii_pins: rgmii-pins { 641e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 642e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 643e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 644e53f67e9SCorentin Labbe function = "emac"; 645e53f67e9SCorentin Labbe drive-strength = <40>; 646e53f67e9SCorentin Labbe }; 647e53f67e9SCorentin Labbe 64854eac67bSMaxime Ripard spdif_tx_pin: spdif-tx-pin { 649b399d2acSMarcus Cooper pins = "PH8"; 650b399d2acSMarcus Cooper function = "spdif"; 651b399d2acSMarcus Cooper }; 652b399d2acSMarcus Cooper 65354eac67bSMaxime Ripard spi0_pins: spi0-pins { 654b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 655b518bb15SStefan Brüns function = "spi0"; 656b518bb15SStefan Brüns }; 657b518bb15SStefan Brüns 65854eac67bSMaxime Ripard spi1_pins: spi1-pins { 659b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 660b518bb15SStefan Brüns function = "spi1"; 661b518bb15SStefan Brüns }; 662b518bb15SStefan Brüns 663d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 6646bc37facSAndre Przywara pins = "PB8", "PB9"; 6656bc37facSAndre Przywara function = "uart0"; 6666bc37facSAndre Przywara }; 667e7ba733dSAndre Przywara 66854eac67bSMaxime Ripard uart1_pins: uart1-pins { 669e7ba733dSAndre Przywara pins = "PG6", "PG7"; 670e7ba733dSAndre Przywara function = "uart1"; 671e7ba733dSAndre Przywara }; 672e7ba733dSAndre Przywara 67354eac67bSMaxime Ripard uart1_rts_cts_pins: uart1-rts-cts-pins { 674e7ba733dSAndre Przywara pins = "PG8", "PG9"; 675e7ba733dSAndre Przywara function = "uart1"; 676e7ba733dSAndre Przywara }; 67779825719SAndreas Färber 67879825719SAndreas Färber uart2_pins: uart2-pins { 67979825719SAndreas Färber pins = "PB0", "PB1"; 68079825719SAndreas Färber function = "uart2"; 68179825719SAndreas Färber }; 6822273aa16SAndreas Färber 6832273aa16SAndreas Färber uart3_pins: uart3-pins { 6842273aa16SAndreas Färber pins = "PD0", "PD1"; 6852273aa16SAndreas Färber function = "uart3"; 6862273aa16SAndreas Färber }; 6872273aa16SAndreas Färber 6882273aa16SAndreas Färber uart4_pins: uart4-pins { 6892273aa16SAndreas Färber pins = "PD2", "PD3"; 6902273aa16SAndreas Färber function = "uart4"; 6912273aa16SAndreas Färber }; 6922273aa16SAndreas Färber 6932273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 6942273aa16SAndreas Färber pins = "PD4", "PD5"; 6952273aa16SAndreas Färber function = "uart4"; 6962273aa16SAndreas Färber }; 6976bc37facSAndre Przywara }; 6986bc37facSAndre Przywara 699b399d2acSMarcus Cooper spdif: spdif@1c21000 { 700b399d2acSMarcus Cooper #sound-dai-cells = <0>; 701b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 702b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 703b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 704b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 705b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 706b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 707b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 708b399d2acSMarcus Cooper dmas = <&dma 2>; 709b399d2acSMarcus Cooper dma-names = "tx"; 710b399d2acSMarcus Cooper pinctrl-names = "default"; 711b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 712b399d2acSMarcus Cooper status = "disabled"; 713b399d2acSMarcus Cooper }; 714b399d2acSMarcus Cooper 71584204fb6SLuca Weiss lradc: lradc@1c21800 { 71684204fb6SLuca Weiss compatible = "allwinner,sun50i-a64-lradc", 71784204fb6SLuca Weiss "allwinner,sun8i-a83t-r-lradc"; 71884204fb6SLuca Weiss reg = <0x01c21800 0x400>; 71984204fb6SLuca Weiss interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 72084204fb6SLuca Weiss status = "disabled"; 72184204fb6SLuca Weiss }; 72284204fb6SLuca Weiss 7231c92c009SMarcus Cooper i2s0: i2s@1c22000 { 7241c92c009SMarcus Cooper #sound-dai-cells = <0>; 7251c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 7261c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 7271c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 7281c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7291c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 7301c92c009SMarcus Cooper clock-names = "apb", "mod"; 7311c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 7321c92c009SMarcus Cooper dma-names = "rx", "tx"; 7331c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 7341c92c009SMarcus Cooper status = "disabled"; 7351c92c009SMarcus Cooper }; 7361c92c009SMarcus Cooper 7371c92c009SMarcus Cooper i2s1: i2s@1c22400 { 7381c92c009SMarcus Cooper #sound-dai-cells = <0>; 7391c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 7401c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 7411c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 7421c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7431c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 7441c92c009SMarcus Cooper clock-names = "apb", "mod"; 7451c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 7461c92c009SMarcus Cooper dma-names = "rx", "tx"; 7471c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 7481c92c009SMarcus Cooper status = "disabled"; 7491c92c009SMarcus Cooper }; 7501c92c009SMarcus Cooper 751ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 752ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 753ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 754ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 755ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 756ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 757ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 758ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 759ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 760ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 761ec4a9540SVasily Khoruzhick status = "disabled"; 762ec4a9540SVasily Khoruzhick }; 763ec4a9540SVasily Khoruzhick 764ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 765ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 766ec4a9540SVasily Khoruzhick compatible = "allwinner,sun8i-a33-codec"; 767ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 768ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 769ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 770ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 771ec4a9540SVasily Khoruzhick status = "disabled"; 772ec4a9540SVasily Khoruzhick }; 773ec4a9540SVasily Khoruzhick 7746bc37facSAndre Przywara uart0: serial@1c28000 { 7756bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7766bc37facSAndre Przywara reg = <0x01c28000 0x400>; 7776bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 7786bc37facSAndre Przywara reg-shift = <2>; 7796bc37facSAndre Przywara reg-io-width = <4>; 780494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 781494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 7826bc37facSAndre Przywara status = "disabled"; 7836bc37facSAndre Przywara }; 7846bc37facSAndre Przywara 7856bc37facSAndre Przywara uart1: serial@1c28400 { 7866bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7876bc37facSAndre Przywara reg = <0x01c28400 0x400>; 7886bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 7896bc37facSAndre Przywara reg-shift = <2>; 7906bc37facSAndre Przywara reg-io-width = <4>; 791494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 792494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 7936bc37facSAndre Przywara status = "disabled"; 7946bc37facSAndre Przywara }; 7956bc37facSAndre Przywara 7966bc37facSAndre Przywara uart2: serial@1c28800 { 7976bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7986bc37facSAndre Przywara reg = <0x01c28800 0x400>; 7996bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 8006bc37facSAndre Przywara reg-shift = <2>; 8016bc37facSAndre Przywara reg-io-width = <4>; 802494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 803494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 8046bc37facSAndre Przywara status = "disabled"; 8056bc37facSAndre Przywara }; 8066bc37facSAndre Przywara 8076bc37facSAndre Przywara uart3: serial@1c28c00 { 8086bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8096bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 8106bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 8116bc37facSAndre Przywara reg-shift = <2>; 8126bc37facSAndre Przywara reg-io-width = <4>; 813494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 814494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 8156bc37facSAndre Przywara status = "disabled"; 8166bc37facSAndre Przywara }; 8176bc37facSAndre Przywara 8186bc37facSAndre Przywara uart4: serial@1c29000 { 8196bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8206bc37facSAndre Przywara reg = <0x01c29000 0x400>; 8216bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 8226bc37facSAndre Przywara reg-shift = <2>; 8236bc37facSAndre Przywara reg-io-width = <4>; 824494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 825494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 8266bc37facSAndre Przywara status = "disabled"; 8276bc37facSAndre Przywara }; 8286bc37facSAndre Przywara 8296bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 8306bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8316bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 8326bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 833494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 834494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 83570f76289SJagan Teki pinctrl-names = "default"; 83670f76289SJagan Teki pinctrl-0 = <&i2c0_pins>; 8376bc37facSAndre Przywara status = "disabled"; 8386bc37facSAndre Przywara #address-cells = <1>; 8396bc37facSAndre Przywara #size-cells = <0>; 8406bc37facSAndre Przywara }; 8416bc37facSAndre Przywara 8426bc37facSAndre Przywara i2c1: i2c@1c2b000 { 8436bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8446bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 8456bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 846494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 847494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 84870f76289SJagan Teki pinctrl-names = "default"; 84970f76289SJagan Teki pinctrl-0 = <&i2c1_pins>; 8506bc37facSAndre Przywara status = "disabled"; 8516bc37facSAndre Przywara #address-cells = <1>; 8526bc37facSAndre Przywara #size-cells = <0>; 8536bc37facSAndre Przywara }; 8546bc37facSAndre Przywara 8556bc37facSAndre Przywara i2c2: i2c@1c2b400 { 8566bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8576bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 8586bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 859494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 860494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 8616bc37facSAndre Przywara status = "disabled"; 8626bc37facSAndre Przywara #address-cells = <1>; 8636bc37facSAndre Przywara #size-cells = <0>; 8646bc37facSAndre Przywara }; 8656bc37facSAndre Przywara 866b518bb15SStefan Brüns 867d6c9da12SCorentin LABBE spi0: spi@1c68000 { 868b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 869b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 870b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 871b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 872b518bb15SStefan Brüns clock-names = "ahb", "mod"; 87306c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 87406c1258aSStefan Brüns dma-names = "rx", "tx"; 875b518bb15SStefan Brüns pinctrl-names = "default"; 876b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 877b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 878b518bb15SStefan Brüns status = "disabled"; 879b518bb15SStefan Brüns num-cs = <1>; 880b518bb15SStefan Brüns #address-cells = <1>; 881b518bb15SStefan Brüns #size-cells = <0>; 882b518bb15SStefan Brüns }; 883b518bb15SStefan Brüns 884d6c9da12SCorentin LABBE spi1: spi@1c69000 { 885b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 886b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 887b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 888b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 889b518bb15SStefan Brüns clock-names = "ahb", "mod"; 89006c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 89106c1258aSStefan Brüns dma-names = "rx", "tx"; 892b518bb15SStefan Brüns pinctrl-names = "default"; 893b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 894b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 895b518bb15SStefan Brüns status = "disabled"; 896b518bb15SStefan Brüns num-cs = <1>; 897b518bb15SStefan Brüns #address-cells = <1>; 898b518bb15SStefan Brüns #size-cells = <0>; 899b518bb15SStefan Brüns }; 900b518bb15SStefan Brüns 90194f44288SCorentin Labbe emac: ethernet@1c30000 { 90294f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 90394f44288SCorentin Labbe syscon = <&syscon>; 90494f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 90594f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 90694f44288SCorentin Labbe interrupt-names = "macirq"; 90794f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 90894f44288SCorentin Labbe reset-names = "stmmaceth"; 90994f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 91094f44288SCorentin Labbe clock-names = "stmmaceth"; 91194f44288SCorentin Labbe status = "disabled"; 91294f44288SCorentin Labbe 91394f44288SCorentin Labbe mdio: mdio { 91416416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 91594f44288SCorentin Labbe #address-cells = <1>; 91694f44288SCorentin Labbe #size-cells = <0>; 91794f44288SCorentin Labbe }; 91894f44288SCorentin Labbe }; 91994f44288SCorentin Labbe 9206b683d76SJagan Teki mali: gpu@1c40000 { 9216b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 9226b683d76SJagan Teki reg = <0x01c40000 0x10000>; 9236b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 9246b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 9256b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 9266b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 9276b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 9286b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 9296b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 9306b683d76SJagan Teki interrupt-names = "gp", 9316b683d76SJagan Teki "gpmmu", 9326b683d76SJagan Teki "pp0", 9336b683d76SJagan Teki "ppmmu0", 9346b683d76SJagan Teki "pp1", 9356b683d76SJagan Teki "ppmmu1", 9366b683d76SJagan Teki "pmu"; 9376b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 9386b683d76SJagan Teki clock-names = "bus", "core"; 9396b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 9406b683d76SJagan Teki }; 9416b683d76SJagan Teki 9426bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 9436bc37facSAndre Przywara compatible = "arm,gic-400"; 9446bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 9456bc37facSAndre Przywara <0x01c82000 0x2000>, 9466bc37facSAndre Przywara <0x01c84000 0x2000>, 9476bc37facSAndre Przywara <0x01c86000 0x2000>; 9486bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 9496bc37facSAndre Przywara interrupt-controller; 9506bc37facSAndre Przywara #interrupt-cells = <3>; 9516bc37facSAndre Przywara }; 9526bc37facSAndre Przywara 953b5df280bSAndre Przywara pwm: pwm@1c21400 { 954b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 955b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 956b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 957b5df280bSAndre Przywara clocks = <&osc24M>; 958b5df280bSAndre Przywara pinctrl-names = "default"; 959b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 960b5df280bSAndre Przywara #pwm-cells = <3>; 961b5df280bSAndre Przywara status = "disabled"; 962b5df280bSAndre Przywara }; 963b5df280bSAndre Przywara 964ff29f13eSJagan Teki csi: csi@1cb0000 { 965ff29f13eSJagan Teki compatible = "allwinner,sun50i-a64-csi"; 966ff29f13eSJagan Teki reg = <0x01cb0000 0x1000>; 967ff29f13eSJagan Teki interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 968ff29f13eSJagan Teki clocks = <&ccu CLK_BUS_CSI>, 969ff29f13eSJagan Teki <&ccu CLK_CSI_SCLK>, 970ff29f13eSJagan Teki <&ccu CLK_DRAM_CSI>; 971ff29f13eSJagan Teki clock-names = "bus", "mod", "ram"; 972ff29f13eSJagan Teki resets = <&ccu RST_BUS_CSI>; 973ff29f13eSJagan Teki pinctrl-names = "default"; 974ff29f13eSJagan Teki pinctrl-0 = <&csi_pins>; 975ff29f13eSJagan Teki status = "disabled"; 976ff29f13eSJagan Teki }; 977ff29f13eSJagan Teki 978e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 979e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 980e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 981e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 982e85f28e0SJagan Teki reg-io-width = <1>; 983e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 984e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 985e85f28e0SJagan Teki <&ccu CLK_HDMI>; 986e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 987e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 988e85f28e0SJagan Teki reset-names = "ctrl"; 989e85f28e0SJagan Teki phys = <&hdmi_phy>; 990d40113fbSMaxime Ripard phy-names = "phy"; 991e85f28e0SJagan Teki status = "disabled"; 992e85f28e0SJagan Teki 993e85f28e0SJagan Teki ports { 994e85f28e0SJagan Teki #address-cells = <1>; 995e85f28e0SJagan Teki #size-cells = <0>; 996e85f28e0SJagan Teki 997e85f28e0SJagan Teki hdmi_in: port@0 { 998e85f28e0SJagan Teki reg = <0>; 999e85f28e0SJagan Teki 1000e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 1001e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 1002e85f28e0SJagan Teki }; 1003e85f28e0SJagan Teki }; 1004e85f28e0SJagan Teki 1005e85f28e0SJagan Teki hdmi_out: port@1 { 1006e85f28e0SJagan Teki reg = <1>; 1007e85f28e0SJagan Teki }; 1008e85f28e0SJagan Teki }; 1009e85f28e0SJagan Teki }; 1010e85f28e0SJagan Teki 1011e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 1012e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 1013e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 1014e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1015e85f28e0SJagan Teki <&ccu 7>; 1016e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 1017e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 1018e85f28e0SJagan Teki reset-names = "phy"; 1019e85f28e0SJagan Teki #phy-cells = <0>; 1020e85f28e0SJagan Teki }; 1021e85f28e0SJagan Teki 10226bc37facSAndre Przywara rtc: rtc@1f00000 { 102344ff3cafSChen-Yu Tsai compatible = "allwinner,sun50i-a64-rtc", 102444ff3cafSChen-Yu Tsai "allwinner,sun8i-h3-rtc"; 102544ff3cafSChen-Yu Tsai reg = <0x01f00000 0x400>; 10266bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 10276bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 102844ff3cafSChen-Yu Tsai clock-output-names = "osc32k", "osc32k-out", "iosc"; 1029e1a9a474SJagan Teki clocks = <&osc32k>; 1030e1a9a474SJagan Teki #clock-cells = <1>; 10316bc37facSAndre Przywara }; 1032791a9e00SIcenowy Zheng 1033535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 1034535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 1035535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 1036535ca508SIcenowy Zheng interrupt-controller; 1037535ca508SIcenowy Zheng #interrupt-cells = <2>; 1038535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 1039535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1040535ca508SIcenowy Zheng }; 1041535ca508SIcenowy Zheng 1042791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 1043791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 1044791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 104544ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1046f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 1047791a9e00SIcenowy Zheng #clock-cells = <1>; 1048791a9e00SIcenowy Zheng #reset-cells = <1>; 1049791a9e00SIcenowy Zheng }; 1050ec427905SIcenowy Zheng 1051ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 1052ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 1053ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 1054ec4a9540SVasily Khoruzhick status = "disabled"; 1055ec4a9540SVasily Khoruzhick }; 1056ec4a9540SVasily Khoruzhick 1057871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 1058871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 1059871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 1060871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 1061871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1062871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1063871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1064871b5352SIcenowy Zheng status = "disabled"; 1065871b5352SIcenowy Zheng #address-cells = <1>; 1066871b5352SIcenowy Zheng #size-cells = <0>; 1067871b5352SIcenowy Zheng }; 1068871b5352SIcenowy Zheng 106944a4f416SIgors Makejevs r_ir: ir@1f02000 { 107044a4f416SIgors Makejevs compatible = "allwinner,sun50i-a64-ir", 107144a4f416SIgors Makejevs "allwinner,sun6i-a31-ir"; 107244a4f416SIgors Makejevs reg = <0x01f02000 0x400>; 107344a4f416SIgors Makejevs clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 107444a4f416SIgors Makejevs clock-names = "apb", "ir"; 107544a4f416SIgors Makejevs resets = <&r_ccu RST_APB0_IR>; 107644a4f416SIgors Makejevs interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 107744a4f416SIgors Makejevs pinctrl-names = "default"; 107844a4f416SIgors Makejevs pinctrl-0 = <&r_ir_rx_pin>; 107944a4f416SIgors Makejevs status = "disabled"; 108044a4f416SIgors Makejevs }; 108144a4f416SIgors Makejevs 1082b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1083b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1084b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1085b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1086b5df280bSAndre Przywara clocks = <&osc24M>; 1087b5df280bSAndre Przywara pinctrl-names = "default"; 1088b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1089b5df280bSAndre Przywara #pwm-cells = <3>; 1090b5df280bSAndre Przywara status = "disabled"; 1091b5df280bSAndre Przywara }; 1092b5df280bSAndre Przywara 1093d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1094ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1095ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1096ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1097494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1098ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1099ec427905SIcenowy Zheng gpio-controller; 1100ec427905SIcenowy Zheng #gpio-cells = <3>; 1101ec427905SIcenowy Zheng interrupt-controller; 1102ec427905SIcenowy Zheng #interrupt-cells = <3>; 11033b38fdedSIcenowy Zheng 11041b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1105871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1106871b5352SIcenowy Zheng function = "s_i2c"; 1107871b5352SIcenowy Zheng }; 1108871b5352SIcenowy Zheng 110944a4f416SIgors Makejevs r_ir_rx_pin: r-ir-rx-pin { 111044a4f416SIgors Makejevs pins = "PL11"; 111144a4f416SIgors Makejevs function = "s_cir_rx"; 111244a4f416SIgors Makejevs }; 111344a4f416SIgors Makejevs 111454eac67bSMaxime Ripard r_pwm_pin: r-pwm-pin { 1115b5df280bSAndre Przywara pins = "PL10"; 1116b5df280bSAndre Przywara function = "s_pwm"; 1117b5df280bSAndre Przywara }; 1118b5df280bSAndre Przywara 111954eac67bSMaxime Ripard r_rsb_pins: r-rsb-pins { 11203b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 11213b38fdedSIcenowy Zheng function = "s_rsb"; 11223b38fdedSIcenowy Zheng }; 11233b38fdedSIcenowy Zheng }; 11243b38fdedSIcenowy Zheng 11253b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 11263b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 11273b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 11283b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 11293b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 11303b38fdedSIcenowy Zheng clock-frequency = <3000000>; 11313b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 11323b38fdedSIcenowy Zheng pinctrl-names = "default"; 11333b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 11343b38fdedSIcenowy Zheng status = "disabled"; 11353b38fdedSIcenowy Zheng #address-cells = <1>; 11363b38fdedSIcenowy Zheng #size-cells = <0>; 1137ec427905SIcenowy Zheng }; 1138d4185043SHarald Geyer 1139d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 1140d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 1141d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 1142d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 1143d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 11449e1975f0SMaxime Ripard clocks = <&osc24M>; 1145d4185043SHarald Geyer }; 11466bc37facSAndre Przywara }; 11476bc37facSAndre Przywara}; 1148