16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 46494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 476bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 48a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 496bc37facSAndre Przywara 506bc37facSAndre Przywara/ { 516bc37facSAndre Przywara interrupt-parent = <&gic>; 526bc37facSAndre Przywara #address-cells = <1>; 536bc37facSAndre Przywara #size-cells = <1>; 546bc37facSAndre Przywara 55c1cff65fSHarald Geyer chosen { 56c1cff65fSHarald Geyer #address-cells = <1>; 57c1cff65fSHarald Geyer #size-cells = <1>; 58c1cff65fSHarald Geyer ranges; 59c1cff65fSHarald Geyer 60c1cff65fSHarald Geyer/* 61c1cff65fSHarald Geyer * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU. 62c1cff65fSHarald Geyer * However there is no support for this clock on A64 yet, so we depend 63c1cff65fSHarald Geyer * on the upstream clocks here to keep them (and thus CLK_MIXER0) up. 64c1cff65fSHarald Geyer */ 65c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 66c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 67c1cff65fSHarald Geyer "simple-framebuffer"; 68c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 69c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 70c1cff65fSHarald Geyer <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; 71c1cff65fSHarald Geyer status = "disabled"; 72c1cff65fSHarald Geyer }; 73c1cff65fSHarald Geyer }; 74c1cff65fSHarald Geyer 756bc37facSAndre Przywara cpus { 766bc37facSAndre Przywara #address-cells = <1>; 776bc37facSAndre Przywara #size-cells = <0>; 786bc37facSAndre Przywara 796bc37facSAndre Przywara cpu0: cpu@0 { 806bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 816bc37facSAndre Przywara device_type = "cpu"; 826bc37facSAndre Przywara reg = <0>; 836bc37facSAndre Przywara enable-method = "psci"; 846bc37facSAndre Przywara }; 856bc37facSAndre Przywara 866bc37facSAndre Przywara cpu1: cpu@1 { 876bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 886bc37facSAndre Przywara device_type = "cpu"; 896bc37facSAndre Przywara reg = <1>; 906bc37facSAndre Przywara enable-method = "psci"; 916bc37facSAndre Przywara }; 926bc37facSAndre Przywara 936bc37facSAndre Przywara cpu2: cpu@2 { 946bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 956bc37facSAndre Przywara device_type = "cpu"; 966bc37facSAndre Przywara reg = <2>; 976bc37facSAndre Przywara enable-method = "psci"; 986bc37facSAndre Przywara }; 996bc37facSAndre Przywara 1006bc37facSAndre Przywara cpu3: cpu@3 { 1016bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 1026bc37facSAndre Przywara device_type = "cpu"; 1036bc37facSAndre Przywara reg = <3>; 1046bc37facSAndre Przywara enable-method = "psci"; 1056bc37facSAndre Przywara }; 1066bc37facSAndre Przywara }; 1076bc37facSAndre Przywara 1086bc37facSAndre Przywara osc24M: osc24M_clk { 1096bc37facSAndre Przywara #clock-cells = <0>; 1106bc37facSAndre Przywara compatible = "fixed-clock"; 1116bc37facSAndre Przywara clock-frequency = <24000000>; 1126bc37facSAndre Przywara clock-output-names = "osc24M"; 1136bc37facSAndre Przywara }; 1146bc37facSAndre Przywara 1156bc37facSAndre Przywara osc32k: osc32k_clk { 1166bc37facSAndre Przywara #clock-cells = <0>; 1176bc37facSAndre Przywara compatible = "fixed-clock"; 1186bc37facSAndre Przywara clock-frequency = <32768>; 1196bc37facSAndre Przywara clock-output-names = "osc32k"; 1206bc37facSAndre Przywara }; 1216bc37facSAndre Przywara 122791a9e00SIcenowy Zheng iosc: internal-osc-clk { 123791a9e00SIcenowy Zheng #clock-cells = <0>; 124791a9e00SIcenowy Zheng compatible = "fixed-clock"; 125791a9e00SIcenowy Zheng clock-frequency = <16000000>; 126791a9e00SIcenowy Zheng clock-accuracy = <300000000>; 127791a9e00SIcenowy Zheng clock-output-names = "iosc"; 128791a9e00SIcenowy Zheng }; 129791a9e00SIcenowy Zheng 1306bc37facSAndre Przywara psci { 1316bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1326bc37facSAndre Przywara method = "smc"; 1336bc37facSAndre Przywara }; 1346bc37facSAndre Przywara 13578e07137SMarcus Cooper sound_spdif { 13678e07137SMarcus Cooper compatible = "simple-audio-card"; 13778e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 13878e07137SMarcus Cooper 13978e07137SMarcus Cooper simple-audio-card,cpu { 14078e07137SMarcus Cooper sound-dai = <&spdif>; 14178e07137SMarcus Cooper }; 14278e07137SMarcus Cooper 14378e07137SMarcus Cooper simple-audio-card,codec { 14478e07137SMarcus Cooper sound-dai = <&spdif_out>; 14578e07137SMarcus Cooper }; 14678e07137SMarcus Cooper }; 14778e07137SMarcus Cooper 14878e07137SMarcus Cooper spdif_out: spdif-out { 14978e07137SMarcus Cooper #sound-dai-cells = <0>; 15078e07137SMarcus Cooper compatible = "linux,spdif-dit"; 15178e07137SMarcus Cooper }; 15278e07137SMarcus Cooper 1536bc37facSAndre Przywara timer { 1546bc37facSAndre Przywara compatible = "arm,armv8-timer"; 1556bc37facSAndre Przywara interrupts = <GIC_PPI 13 1566bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1576bc37facSAndre Przywara <GIC_PPI 14 1586bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1596bc37facSAndre Przywara <GIC_PPI 11 1606bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1616bc37facSAndre Przywara <GIC_PPI 10 1626bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1636bc37facSAndre Przywara }; 1646bc37facSAndre Przywara 1656bc37facSAndre Przywara soc { 1666bc37facSAndre Przywara compatible = "simple-bus"; 1676bc37facSAndre Przywara #address-cells = <1>; 1686bc37facSAndre Przywara #size-cells = <1>; 1696bc37facSAndre Przywara ranges; 1706bc37facSAndre Przywara 17179b95360SCorentin Labbe syscon: syscon@1c00000 { 17279b95360SCorentin Labbe compatible = "allwinner,sun50i-a64-system-controller", 17379b95360SCorentin Labbe "syscon"; 17479b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 17579b95360SCorentin Labbe }; 17679b95360SCorentin Labbe 177c32637e0SStefan Brüns dma: dma-controller@1c02000 { 178c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 179c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 180c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 181c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 182c32637e0SStefan Brüns dma-channels = <8>; 183c32637e0SStefan Brüns dma-requests = <27>; 184c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 185c32637e0SStefan Brüns #dma-cells = <1>; 186c32637e0SStefan Brüns }; 187c32637e0SStefan Brüns 188f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 189f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 190f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 191f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 192f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 193f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 194f3dff347SAndre Przywara reset-names = "ahb"; 195f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 19622be992fSMaxime Ripard max-frequency = <150000000>; 197f3dff347SAndre Przywara status = "disabled"; 198f3dff347SAndre Przywara #address-cells = <1>; 199f3dff347SAndre Przywara #size-cells = <0>; 200f3dff347SAndre Przywara }; 201f3dff347SAndre Przywara 202f3dff347SAndre Przywara mmc1: mmc@1c10000 { 203f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 204f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 205f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 206f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 207f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 208f3dff347SAndre Przywara reset-names = "ahb"; 209f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 21022be992fSMaxime Ripard max-frequency = <150000000>; 211f3dff347SAndre Przywara status = "disabled"; 212f3dff347SAndre Przywara #address-cells = <1>; 213f3dff347SAndre Przywara #size-cells = <0>; 214f3dff347SAndre Przywara }; 215f3dff347SAndre Przywara 216f3dff347SAndre Przywara mmc2: mmc@1c11000 { 217f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 218f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 219f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 220f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 221f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 222f3dff347SAndre Przywara reset-names = "ahb"; 223f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 22422be992fSMaxime Ripard max-frequency = <200000000>; 225f3dff347SAndre Przywara status = "disabled"; 226f3dff347SAndre Przywara #address-cells = <1>; 227f3dff347SAndre Przywara #size-cells = <0>; 228f3dff347SAndre Przywara }; 229f3dff347SAndre Przywara 230d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 231972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 232972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 233972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 234972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 235972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 236972a3ecdSIcenowy Zheng interrupt-names = "mc"; 237972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 238972a3ecdSIcenowy Zheng phy-names = "usb"; 239972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 240972a3ecdSIcenowy Zheng status = "disabled"; 241972a3ecdSIcenowy Zheng }; 242972a3ecdSIcenowy Zheng 243d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 244a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 245a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 2460d984797SIcenowy Zheng <0x01c1a800 0x4>, 247a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 248a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 2490d984797SIcenowy Zheng "pmu0", 250a004ee35SIcenowy Zheng "pmu1"; 251a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 252a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 253a004ee35SIcenowy Zheng clock-names = "usb0_phy", 254a004ee35SIcenowy Zheng "usb1_phy"; 255a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 256a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 257a004ee35SIcenowy Zheng reset-names = "usb0_reset", 258a004ee35SIcenowy Zheng "usb1_reset"; 259a004ee35SIcenowy Zheng status = "disabled"; 260a004ee35SIcenowy Zheng #phy-cells = <1>; 261a004ee35SIcenowy Zheng }; 262a004ee35SIcenowy Zheng 263d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 264dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 265dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 266dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 267dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 268dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 269dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 270dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 271dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 272dc03a047SIcenowy Zheng status = "disabled"; 273dc03a047SIcenowy Zheng }; 274dc03a047SIcenowy Zheng 275d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 276dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 277dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 278dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 279dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 280dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 281dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 282dc03a047SIcenowy Zheng status = "disabled"; 283dc03a047SIcenowy Zheng }; 284dc03a047SIcenowy Zheng 285d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 286a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 287a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 288a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 289a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 290a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 291a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 292a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 293a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 294a004ee35SIcenowy Zheng phys = <&usbphy 1>; 295a004ee35SIcenowy Zheng phy-names = "usb"; 296a004ee35SIcenowy Zheng status = "disabled"; 297a004ee35SIcenowy Zheng }; 298a004ee35SIcenowy Zheng 299d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 300a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 301a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 302a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 303a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 304a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 305a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 306a004ee35SIcenowy Zheng phys = <&usbphy 1>; 307a004ee35SIcenowy Zheng phy-names = "usb"; 308a004ee35SIcenowy Zheng status = "disabled"; 309a004ee35SIcenowy Zheng }; 310a004ee35SIcenowy Zheng 311d6c9da12SCorentin LABBE ccu: clock@1c20000 { 3126bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 3136bc37facSAndre Przywara reg = <0x01c20000 0x400>; 3146bc37facSAndre Przywara clocks = <&osc24M>, <&osc32k>; 3156bc37facSAndre Przywara clock-names = "hosc", "losc"; 3166bc37facSAndre Przywara #clock-cells = <1>; 3176bc37facSAndre Przywara #reset-cells = <1>; 3186bc37facSAndre Przywara }; 3196bc37facSAndre Przywara 3206bc37facSAndre Przywara pio: pinctrl@1c20800 { 3216bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 3226bc37facSAndre Przywara reg = <0x01c20800 0x400>; 3236bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 3246bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 3256bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 326f98121f3SArnd Bergmann clocks = <&ccu 58>; 3276bc37facSAndre Przywara gpio-controller; 3286bc37facSAndre Przywara #gpio-cells = <3>; 3296bc37facSAndre Przywara interrupt-controller; 3306bc37facSAndre Przywara #interrupt-cells = <3>; 3316bc37facSAndre Przywara 33211239fe6SHarald Geyer i2c0_pins: i2c0_pins { 33311239fe6SHarald Geyer pins = "PH0", "PH1"; 33411239fe6SHarald Geyer function = "i2c0"; 33511239fe6SHarald Geyer }; 33611239fe6SHarald Geyer 3376bc37facSAndre Przywara i2c1_pins: i2c1_pins { 3386bc37facSAndre Przywara pins = "PH2", "PH3"; 3396bc37facSAndre Przywara function = "i2c1"; 3406bc37facSAndre Przywara }; 3416bc37facSAndre Przywara 342a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 343a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 344a3e8f492SMaxime Ripard "PF4", "PF5"; 345a3e8f492SMaxime Ripard function = "mmc0"; 346a3e8f492SMaxime Ripard drive-strength = <30>; 347a3e8f492SMaxime Ripard bias-pull-up; 348a3e8f492SMaxime Ripard }; 349a3e8f492SMaxime Ripard 350a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 351a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 352a3e8f492SMaxime Ripard "PG4", "PG5"; 353a3e8f492SMaxime Ripard function = "mmc1"; 354a3e8f492SMaxime Ripard drive-strength = <30>; 355a3e8f492SMaxime Ripard bias-pull-up; 356a3e8f492SMaxime Ripard }; 357a3e8f492SMaxime Ripard 358a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 359a3e8f492SMaxime Ripard pins = "PC1", "PC5", "PC6", "PC8", "PC9", 360a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 361a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 362a3e8f492SMaxime Ripard function = "mmc2"; 363a3e8f492SMaxime Ripard drive-strength = <30>; 364a3e8f492SMaxime Ripard bias-pull-up; 365a3e8f492SMaxime Ripard }; 366a3e8f492SMaxime Ripard 367e53f67e9SCorentin Labbe rmii_pins: rmii_pins { 368e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 369e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 370e53f67e9SCorentin Labbe function = "emac"; 371e53f67e9SCorentin Labbe drive-strength = <40>; 372e53f67e9SCorentin Labbe }; 373e53f67e9SCorentin Labbe 374e53f67e9SCorentin Labbe rgmii_pins: rgmii_pins { 375e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 376e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 377e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 378e53f67e9SCorentin Labbe function = "emac"; 379e53f67e9SCorentin Labbe drive-strength = <40>; 380e53f67e9SCorentin Labbe }; 381e53f67e9SCorentin Labbe 382b399d2acSMarcus Cooper spdif_tx_pin: spdif { 383b399d2acSMarcus Cooper pins = "PH8"; 384b399d2acSMarcus Cooper function = "spdif"; 385b399d2acSMarcus Cooper }; 386b399d2acSMarcus Cooper 387b518bb15SStefan Brüns spi0_pins: spi0 { 388b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 389b518bb15SStefan Brüns function = "spi0"; 390b518bb15SStefan Brüns }; 391b518bb15SStefan Brüns 392b518bb15SStefan Brüns spi1_pins: spi1 { 393b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 394b518bb15SStefan Brüns function = "spi1"; 395b518bb15SStefan Brüns }; 396b518bb15SStefan Brüns 39792d378fbSCorentin LABBE uart0_pins_a: uart0 { 3986bc37facSAndre Przywara pins = "PB8", "PB9"; 3996bc37facSAndre Przywara function = "uart0"; 4006bc37facSAndre Przywara }; 401e7ba733dSAndre Przywara 402e7ba733dSAndre Przywara uart1_pins: uart1_pins { 403e7ba733dSAndre Przywara pins = "PG6", "PG7"; 404e7ba733dSAndre Przywara function = "uart1"; 405e7ba733dSAndre Przywara }; 406e7ba733dSAndre Przywara 407e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 408e7ba733dSAndre Przywara pins = "PG8", "PG9"; 409e7ba733dSAndre Przywara function = "uart1"; 410e7ba733dSAndre Przywara }; 41179825719SAndreas Färber 41279825719SAndreas Färber uart2_pins: uart2-pins { 41379825719SAndreas Färber pins = "PB0", "PB1"; 41479825719SAndreas Färber function = "uart2"; 41579825719SAndreas Färber }; 4162273aa16SAndreas Färber 4172273aa16SAndreas Färber uart3_pins: uart3-pins { 4182273aa16SAndreas Färber pins = "PD0", "PD1"; 4192273aa16SAndreas Färber function = "uart3"; 4202273aa16SAndreas Färber }; 4212273aa16SAndreas Färber 4222273aa16SAndreas Färber uart4_pins: uart4-pins { 4232273aa16SAndreas Färber pins = "PD2", "PD3"; 4242273aa16SAndreas Färber function = "uart4"; 4252273aa16SAndreas Färber }; 4262273aa16SAndreas Färber 4272273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 4282273aa16SAndreas Färber pins = "PD4", "PD5"; 4292273aa16SAndreas Färber function = "uart4"; 4302273aa16SAndreas Färber }; 4316bc37facSAndre Przywara }; 4326bc37facSAndre Przywara 433b399d2acSMarcus Cooper spdif: spdif@1c21000 { 434b399d2acSMarcus Cooper #sound-dai-cells = <0>; 435b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 436b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 437b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 438b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 439b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 440b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 441b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 442b399d2acSMarcus Cooper dmas = <&dma 2>; 443b399d2acSMarcus Cooper dma-names = "tx"; 444b399d2acSMarcus Cooper pinctrl-names = "default"; 445b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 446b399d2acSMarcus Cooper status = "disabled"; 447b399d2acSMarcus Cooper }; 448b399d2acSMarcus Cooper 4491c92c009SMarcus Cooper i2s0: i2s@1c22000 { 4501c92c009SMarcus Cooper #sound-dai-cells = <0>; 4511c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 4521c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 4531c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 4541c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4551c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 4561c92c009SMarcus Cooper clock-names = "apb", "mod"; 4571c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 4581c92c009SMarcus Cooper dma-names = "rx", "tx"; 4591c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 4601c92c009SMarcus Cooper status = "disabled"; 4611c92c009SMarcus Cooper }; 4621c92c009SMarcus Cooper 4631c92c009SMarcus Cooper i2s1: i2s@1c22400 { 4641c92c009SMarcus Cooper #sound-dai-cells = <0>; 4651c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 4661c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 4671c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 4681c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4691c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 4701c92c009SMarcus Cooper clock-names = "apb", "mod"; 4711c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 4721c92c009SMarcus Cooper dma-names = "rx", "tx"; 4731c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 4741c92c009SMarcus Cooper status = "disabled"; 4751c92c009SMarcus Cooper }; 4761c92c009SMarcus Cooper 4776bc37facSAndre Przywara uart0: serial@1c28000 { 4786bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 4796bc37facSAndre Przywara reg = <0x01c28000 0x400>; 4806bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4816bc37facSAndre Przywara reg-shift = <2>; 4826bc37facSAndre Przywara reg-io-width = <4>; 483494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 484494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 4856bc37facSAndre Przywara status = "disabled"; 4866bc37facSAndre Przywara }; 4876bc37facSAndre Przywara 4886bc37facSAndre Przywara uart1: serial@1c28400 { 4896bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 4906bc37facSAndre Przywara reg = <0x01c28400 0x400>; 4916bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 4926bc37facSAndre Przywara reg-shift = <2>; 4936bc37facSAndre Przywara reg-io-width = <4>; 494494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 495494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 4966bc37facSAndre Przywara status = "disabled"; 4976bc37facSAndre Przywara }; 4986bc37facSAndre Przywara 4996bc37facSAndre Przywara uart2: serial@1c28800 { 5006bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5016bc37facSAndre Przywara reg = <0x01c28800 0x400>; 5026bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 5036bc37facSAndre Przywara reg-shift = <2>; 5046bc37facSAndre Przywara reg-io-width = <4>; 505494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 506494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 5076bc37facSAndre Przywara status = "disabled"; 5086bc37facSAndre Przywara }; 5096bc37facSAndre Przywara 5106bc37facSAndre Przywara uart3: serial@1c28c00 { 5116bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5126bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 5136bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 5146bc37facSAndre Przywara reg-shift = <2>; 5156bc37facSAndre Przywara reg-io-width = <4>; 516494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 517494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 5186bc37facSAndre Przywara status = "disabled"; 5196bc37facSAndre Przywara }; 5206bc37facSAndre Przywara 5216bc37facSAndre Przywara uart4: serial@1c29000 { 5226bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5236bc37facSAndre Przywara reg = <0x01c29000 0x400>; 5246bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 5256bc37facSAndre Przywara reg-shift = <2>; 5266bc37facSAndre Przywara reg-io-width = <4>; 527494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 528494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 5296bc37facSAndre Przywara status = "disabled"; 5306bc37facSAndre Przywara }; 5316bc37facSAndre Przywara 5326bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 5336bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5346bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 5356bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 536494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 537494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 5386bc37facSAndre Przywara status = "disabled"; 5396bc37facSAndre Przywara #address-cells = <1>; 5406bc37facSAndre Przywara #size-cells = <0>; 5416bc37facSAndre Przywara }; 5426bc37facSAndre Przywara 5436bc37facSAndre Przywara i2c1: i2c@1c2b000 { 5446bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5456bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 5466bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 547494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 548494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 5496bc37facSAndre Przywara status = "disabled"; 5506bc37facSAndre Przywara #address-cells = <1>; 5516bc37facSAndre Przywara #size-cells = <0>; 5526bc37facSAndre Przywara }; 5536bc37facSAndre Przywara 5546bc37facSAndre Przywara i2c2: i2c@1c2b400 { 5556bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5566bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 5576bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 558494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 559494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 5606bc37facSAndre Przywara status = "disabled"; 5616bc37facSAndre Przywara #address-cells = <1>; 5626bc37facSAndre Przywara #size-cells = <0>; 5636bc37facSAndre Przywara }; 5646bc37facSAndre Przywara 565b518bb15SStefan Brüns 566d6c9da12SCorentin LABBE spi0: spi@1c68000 { 567b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 568b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 569b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 570b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 571b518bb15SStefan Brüns clock-names = "ahb", "mod"; 57206c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 57306c1258aSStefan Brüns dma-names = "rx", "tx"; 574b518bb15SStefan Brüns pinctrl-names = "default"; 575b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 576b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 577b518bb15SStefan Brüns status = "disabled"; 578b518bb15SStefan Brüns num-cs = <1>; 579b518bb15SStefan Brüns #address-cells = <1>; 580b518bb15SStefan Brüns #size-cells = <0>; 581b518bb15SStefan Brüns }; 582b518bb15SStefan Brüns 583d6c9da12SCorentin LABBE spi1: spi@1c69000 { 584b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 585b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 586b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 587b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 588b518bb15SStefan Brüns clock-names = "ahb", "mod"; 58906c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 59006c1258aSStefan Brüns dma-names = "rx", "tx"; 591b518bb15SStefan Brüns pinctrl-names = "default"; 592b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 593b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 594b518bb15SStefan Brüns status = "disabled"; 595b518bb15SStefan Brüns num-cs = <1>; 596b518bb15SStefan Brüns #address-cells = <1>; 597b518bb15SStefan Brüns #size-cells = <0>; 598b518bb15SStefan Brüns }; 599b518bb15SStefan Brüns 60094f44288SCorentin Labbe emac: ethernet@1c30000 { 60194f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 60294f44288SCorentin Labbe syscon = <&syscon>; 60394f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 60494f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 60594f44288SCorentin Labbe interrupt-names = "macirq"; 60694f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 60794f44288SCorentin Labbe reset-names = "stmmaceth"; 60894f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 60994f44288SCorentin Labbe clock-names = "stmmaceth"; 61094f44288SCorentin Labbe status = "disabled"; 61194f44288SCorentin Labbe #address-cells = <1>; 61294f44288SCorentin Labbe #size-cells = <0>; 61394f44288SCorentin Labbe 61494f44288SCorentin Labbe mdio: mdio { 61516416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 61694f44288SCorentin Labbe #address-cells = <1>; 61794f44288SCorentin Labbe #size-cells = <0>; 61894f44288SCorentin Labbe }; 61994f44288SCorentin Labbe }; 62094f44288SCorentin Labbe 6216bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 6226bc37facSAndre Przywara compatible = "arm,gic-400"; 6236bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 6246bc37facSAndre Przywara <0x01c82000 0x2000>, 6256bc37facSAndre Przywara <0x01c84000 0x2000>, 6266bc37facSAndre Przywara <0x01c86000 0x2000>; 6276bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 6286bc37facSAndre Przywara interrupt-controller; 6296bc37facSAndre Przywara #interrupt-cells = <3>; 6306bc37facSAndre Przywara }; 6316bc37facSAndre Przywara 6326bc37facSAndre Przywara rtc: rtc@1f00000 { 6336bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-rtc"; 6346bc37facSAndre Przywara reg = <0x01f00000 0x54>; 6356bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 6366bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 6376bc37facSAndre Przywara }; 638791a9e00SIcenowy Zheng 639535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 640535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 641535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 642535ca508SIcenowy Zheng interrupt-controller; 643535ca508SIcenowy Zheng #interrupt-cells = <2>; 644535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 645535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 646535ca508SIcenowy Zheng }; 647535ca508SIcenowy Zheng 648791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 649791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 650791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 651f74994a9SChen-Yu Tsai clocks = <&osc24M>, <&osc32k>, <&iosc>, 652f74994a9SChen-Yu Tsai <&ccu 11>; 653f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 654791a9e00SIcenowy Zheng #clock-cells = <1>; 655791a9e00SIcenowy Zheng #reset-cells = <1>; 656791a9e00SIcenowy Zheng }; 657ec427905SIcenowy Zheng 658d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 659ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 660ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 661ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 662494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 663ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 664ec427905SIcenowy Zheng gpio-controller; 665ec427905SIcenowy Zheng #gpio-cells = <3>; 666ec427905SIcenowy Zheng interrupt-controller; 667ec427905SIcenowy Zheng #interrupt-cells = <3>; 6683b38fdedSIcenowy Zheng 66992d378fbSCorentin LABBE r_rsb_pins: rsb { 6703b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 6713b38fdedSIcenowy Zheng function = "s_rsb"; 6723b38fdedSIcenowy Zheng }; 6733b38fdedSIcenowy Zheng }; 6743b38fdedSIcenowy Zheng 6753b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 6763b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 6773b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 6783b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 6793b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 6803b38fdedSIcenowy Zheng clock-frequency = <3000000>; 6813b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 6823b38fdedSIcenowy Zheng pinctrl-names = "default"; 6833b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 6843b38fdedSIcenowy Zheng status = "disabled"; 6853b38fdedSIcenowy Zheng #address-cells = <1>; 6863b38fdedSIcenowy Zheng #size-cells = <0>; 687ec427905SIcenowy Zheng }; 688d4185043SHarald Geyer 689d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 690d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 691d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 692d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 693d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 694d4185043SHarald Geyer }; 6956bc37facSAndre Przywara }; 6966bc37facSAndre Przywara}; 697