16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 462c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 47494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 486bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 49a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 502c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 51871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 526bc37facSAndre Przywara 536bc37facSAndre Przywara/ { 546bc37facSAndre Przywara interrupt-parent = <&gic>; 556bc37facSAndre Przywara #address-cells = <1>; 566bc37facSAndre Przywara #size-cells = <1>; 576bc37facSAndre Przywara 58c1cff65fSHarald Geyer chosen { 59c1cff65fSHarald Geyer #address-cells = <1>; 60c1cff65fSHarald Geyer #size-cells = <1>; 61c1cff65fSHarald Geyer ranges; 62c1cff65fSHarald Geyer 63c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 64c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 65c1cff65fSHarald Geyer "simple-framebuffer"; 66c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 67c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 682c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 69c1cff65fSHarald Geyer status = "disabled"; 70c1cff65fSHarald Geyer }; 71fca63f58SIcenowy Zheng 72fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 73fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 74fca63f58SIcenowy Zheng "simple-framebuffer"; 75fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 76fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 77fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78fca63f58SIcenowy Zheng status = "disabled"; 79fca63f58SIcenowy Zheng }; 80c1cff65fSHarald Geyer }; 81c1cff65fSHarald Geyer 826bc37facSAndre Przywara cpus { 836bc37facSAndre Przywara #address-cells = <1>; 846bc37facSAndre Przywara #size-cells = <0>; 856bc37facSAndre Przywara 866bc37facSAndre Przywara cpu0: cpu@0 { 8731af04cdSRob Herring compatible = "arm,cortex-a53"; 886bc37facSAndre Przywara device_type = "cpu"; 896bc37facSAndre Przywara reg = <0>; 906bc37facSAndre Przywara enable-method = "psci"; 9139defc81SAndre Przywara next-level-cache = <&L2>; 926bc37facSAndre Przywara }; 936bc37facSAndre Przywara 946bc37facSAndre Przywara cpu1: cpu@1 { 9531af04cdSRob Herring compatible = "arm,cortex-a53"; 966bc37facSAndre Przywara device_type = "cpu"; 976bc37facSAndre Przywara reg = <1>; 986bc37facSAndre Przywara enable-method = "psci"; 9939defc81SAndre Przywara next-level-cache = <&L2>; 1006bc37facSAndre Przywara }; 1016bc37facSAndre Przywara 1026bc37facSAndre Przywara cpu2: cpu@2 { 10331af04cdSRob Herring compatible = "arm,cortex-a53"; 1046bc37facSAndre Przywara device_type = "cpu"; 1056bc37facSAndre Przywara reg = <2>; 1066bc37facSAndre Przywara enable-method = "psci"; 10739defc81SAndre Przywara next-level-cache = <&L2>; 1086bc37facSAndre Przywara }; 1096bc37facSAndre Przywara 1106bc37facSAndre Przywara cpu3: cpu@3 { 11131af04cdSRob Herring compatible = "arm,cortex-a53"; 1126bc37facSAndre Przywara device_type = "cpu"; 1136bc37facSAndre Przywara reg = <3>; 1146bc37facSAndre Przywara enable-method = "psci"; 11539defc81SAndre Przywara next-level-cache = <&L2>; 11639defc81SAndre Przywara }; 11739defc81SAndre Przywara 11839defc81SAndre Przywara L2: l2-cache { 11939defc81SAndre Przywara compatible = "cache"; 12039defc81SAndre Przywara cache-level = <2>; 1216bc37facSAndre Przywara }; 1226bc37facSAndre Przywara }; 1236bc37facSAndre Przywara 124e85f28e0SJagan Teki de: display-engine { 125e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 126e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 127e85f28e0SJagan Teki <&mixer1>; 128e85f28e0SJagan Teki status = "disabled"; 129e85f28e0SJagan Teki }; 130e85f28e0SJagan Teki 1316bc37facSAndre Przywara osc24M: osc24M_clk { 1326bc37facSAndre Przywara #clock-cells = <0>; 1336bc37facSAndre Przywara compatible = "fixed-clock"; 1346bc37facSAndre Przywara clock-frequency = <24000000>; 1356bc37facSAndre Przywara clock-output-names = "osc24M"; 1366bc37facSAndre Przywara }; 1376bc37facSAndre Przywara 1386bc37facSAndre Przywara osc32k: osc32k_clk { 1396bc37facSAndre Przywara #clock-cells = <0>; 1406bc37facSAndre Przywara compatible = "fixed-clock"; 1416bc37facSAndre Przywara clock-frequency = <32768>; 14244ff3cafSChen-Yu Tsai clock-output-names = "ext-osc32k"; 143791a9e00SIcenowy Zheng }; 144791a9e00SIcenowy Zheng 14534a97fccSHarald Geyer pmu { 14634a97fccSHarald Geyer compatible = "arm,cortex-a53-pmu"; 14734a97fccSHarald Geyer interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 14834a97fccSHarald Geyer <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 14934a97fccSHarald Geyer <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 15034a97fccSHarald Geyer <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 15134a97fccSHarald Geyer interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 15234a97fccSHarald Geyer }; 15334a97fccSHarald Geyer 1546bc37facSAndre Przywara psci { 1556bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1566bc37facSAndre Przywara method = "smc"; 1576bc37facSAndre Przywara }; 1586bc37facSAndre Przywara 159ec4a9540SVasily Khoruzhick sound: sound { 160ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 161ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 162ec4a9540SVasily Khoruzhick simple-audio-card,format = "i2s"; 163ec4a9540SVasily Khoruzhick simple-audio-card,frame-master = <&cpudai>; 164ec4a9540SVasily Khoruzhick simple-audio-card,bitclock-master = <&cpudai>; 165ec4a9540SVasily Khoruzhick simple-audio-card,mclk-fs = <128>; 166ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 167ec4a9540SVasily Khoruzhick simple-audio-card,routing = 168ec4a9540SVasily Khoruzhick "Left DAC", "AIF1 Slot 0 Left", 169ec4a9540SVasily Khoruzhick "Right DAC", "AIF1 Slot 0 Right", 170ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Left ADC", "Left ADC", 171ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Right ADC", "Right ADC"; 172ec4a9540SVasily Khoruzhick status = "disabled"; 173ec4a9540SVasily Khoruzhick 174ec4a9540SVasily Khoruzhick cpudai: simple-audio-card,cpu { 175ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 176ec4a9540SVasily Khoruzhick }; 177ec4a9540SVasily Khoruzhick 178ec4a9540SVasily Khoruzhick link_codec: simple-audio-card,codec { 179ec4a9540SVasily Khoruzhick sound-dai = <&codec>; 180ec4a9540SVasily Khoruzhick }; 181ec4a9540SVasily Khoruzhick }; 182ec4a9540SVasily Khoruzhick 18378e07137SMarcus Cooper sound_spdif { 18478e07137SMarcus Cooper compatible = "simple-audio-card"; 18578e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 18678e07137SMarcus Cooper 18778e07137SMarcus Cooper simple-audio-card,cpu { 18878e07137SMarcus Cooper sound-dai = <&spdif>; 18978e07137SMarcus Cooper }; 19078e07137SMarcus Cooper 19178e07137SMarcus Cooper simple-audio-card,codec { 19278e07137SMarcus Cooper sound-dai = <&spdif_out>; 19378e07137SMarcus Cooper }; 19478e07137SMarcus Cooper }; 19578e07137SMarcus Cooper 19678e07137SMarcus Cooper spdif_out: spdif-out { 19778e07137SMarcus Cooper #sound-dai-cells = <0>; 19878e07137SMarcus Cooper compatible = "linux,spdif-dit"; 19978e07137SMarcus Cooper }; 20078e07137SMarcus Cooper 2016bc37facSAndre Przywara timer { 2026bc37facSAndre Przywara compatible = "arm,armv8-timer"; 20355ec26d6SSamuel Holland allwinner,erratum-unknown1; 2046bc37facSAndre Przywara interrupts = <GIC_PPI 13 2056bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2066bc37facSAndre Przywara <GIC_PPI 14 2076bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2086bc37facSAndre Przywara <GIC_PPI 11 2096bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2106bc37facSAndre Przywara <GIC_PPI 10 2116bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 2126bc37facSAndre Przywara }; 2136bc37facSAndre Przywara 2146bc37facSAndre Przywara soc { 2156bc37facSAndre Przywara compatible = "simple-bus"; 2166bc37facSAndre Przywara #address-cells = <1>; 2176bc37facSAndre Przywara #size-cells = <1>; 2186bc37facSAndre Przywara ranges; 2196bc37facSAndre Przywara 2202c796fc8SIcenowy Zheng de2@1000000 { 2212c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 2222c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 2232c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 2242c796fc8SIcenowy Zheng #address-cells = <1>; 2252c796fc8SIcenowy Zheng #size-cells = <1>; 2262c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 2272c796fc8SIcenowy Zheng 2282c796fc8SIcenowy Zheng display_clocks: clock@0 { 2292c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 2302c796fc8SIcenowy Zheng reg = <0x0 0x100000>; 2312c796fc8SIcenowy Zheng clocks = <&ccu CLK_DE>, 2322c796fc8SIcenowy Zheng <&ccu CLK_BUS_DE>; 2332c796fc8SIcenowy Zheng clock-names = "mod", 2342c796fc8SIcenowy Zheng "bus"; 2352c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 2362c796fc8SIcenowy Zheng #clock-cells = <1>; 2372c796fc8SIcenowy Zheng #reset-cells = <1>; 2382c796fc8SIcenowy Zheng }; 239e85f28e0SJagan Teki 240e85f28e0SJagan Teki mixer0: mixer@100000 { 241e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 242e85f28e0SJagan Teki reg = <0x100000 0x100000>; 243e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 244e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 245e85f28e0SJagan Teki clock-names = "bus", 246e85f28e0SJagan Teki "mod"; 247e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 248e85f28e0SJagan Teki 249e85f28e0SJagan Teki ports { 250e85f28e0SJagan Teki #address-cells = <1>; 251e85f28e0SJagan Teki #size-cells = <0>; 252e85f28e0SJagan Teki 253e85f28e0SJagan Teki mixer0_out: port@1 { 254a7f7047fSMaxime Ripard #address-cells = <1>; 255a7f7047fSMaxime Ripard #size-cells = <0>; 256e85f28e0SJagan Teki reg = <1>; 257e85f28e0SJagan Teki 258a7f7047fSMaxime Ripard mixer0_out_tcon0: endpoint@0 { 259a7f7047fSMaxime Ripard reg = <0>; 260e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 261e85f28e0SJagan Teki }; 262a7f7047fSMaxime Ripard 263a7f7047fSMaxime Ripard mixer0_out_tcon1: endpoint@1 { 264a7f7047fSMaxime Ripard reg = <1>; 265a7f7047fSMaxime Ripard remote-endpoint = <&tcon1_in_mixer0>; 266a7f7047fSMaxime Ripard }; 267e85f28e0SJagan Teki }; 268e85f28e0SJagan Teki }; 269e85f28e0SJagan Teki }; 270e85f28e0SJagan Teki 271e85f28e0SJagan Teki mixer1: mixer@200000 { 272e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 273e85f28e0SJagan Teki reg = <0x200000 0x100000>; 274e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 275e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 276e85f28e0SJagan Teki clock-names = "bus", 277e85f28e0SJagan Teki "mod"; 278e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 279e85f28e0SJagan Teki 280e85f28e0SJagan Teki ports { 281e85f28e0SJagan Teki #address-cells = <1>; 282e85f28e0SJagan Teki #size-cells = <0>; 283e85f28e0SJagan Teki 284e85f28e0SJagan Teki mixer1_out: port@1 { 285e85f28e0SJagan Teki reg = <1>; 286e85f28e0SJagan Teki 287a7f7047fSMaxime Ripard mixer1_out_tcon0: endpoint@0 { 288a7f7047fSMaxime Ripard reg = <0>; 289a7f7047fSMaxime Ripard remote-endpoint = <&tcon0_in_mixer1>; 290a7f7047fSMaxime Ripard }; 291a7f7047fSMaxime Ripard 292a7f7047fSMaxime Ripard mixer1_out_tcon1: endpoint@1 { 293a7f7047fSMaxime Ripard reg = <1>; 294e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 295e85f28e0SJagan Teki }; 296e85f28e0SJagan Teki }; 297e85f28e0SJagan Teki }; 298e85f28e0SJagan Teki }; 2992c796fc8SIcenowy Zheng }; 3002c796fc8SIcenowy Zheng 30179b95360SCorentin Labbe syscon: syscon@1c00000 { 3021f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 30379b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 3041f1f5183SIcenowy Zheng #address-cells = <1>; 3051f1f5183SIcenowy Zheng #size-cells = <1>; 3061f1f5183SIcenowy Zheng ranges; 3071f1f5183SIcenowy Zheng 3081f1f5183SIcenowy Zheng sram_c: sram@18000 { 3091f1f5183SIcenowy Zheng compatible = "mmio-sram"; 3101f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 3111f1f5183SIcenowy Zheng #address-cells = <1>; 3121f1f5183SIcenowy Zheng #size-cells = <1>; 3131f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 3141f1f5183SIcenowy Zheng 3151f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 3161f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 3171f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 3181f1f5183SIcenowy Zheng }; 3191f1f5183SIcenowy Zheng }; 320106deea8SPaul Kocialkowski 321106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 322106deea8SPaul Kocialkowski compatible = "mmio-sram"; 323106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 324106deea8SPaul Kocialkowski #address-cells = <1>; 325106deea8SPaul Kocialkowski #size-cells = <1>; 326106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 327106deea8SPaul Kocialkowski 328106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 329106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 330106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 331106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 332106deea8SPaul Kocialkowski }; 333106deea8SPaul Kocialkowski }; 33479b95360SCorentin Labbe }; 33579b95360SCorentin Labbe 336c32637e0SStefan Brüns dma: dma-controller@1c02000 { 337c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 338c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 339c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 340c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 341c32637e0SStefan Brüns dma-channels = <8>; 342c32637e0SStefan Brüns dma-requests = <27>; 343c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 344c32637e0SStefan Brüns #dma-cells = <1>; 345c32637e0SStefan Brüns }; 346c32637e0SStefan Brüns 347e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 348e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 349e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 350e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 351e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 352e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 353e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 354e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 355e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 356e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 357e85f28e0SJagan Teki 358e85f28e0SJagan Teki ports { 359e85f28e0SJagan Teki #address-cells = <1>; 360e85f28e0SJagan Teki #size-cells = <0>; 361e85f28e0SJagan Teki 362e85f28e0SJagan Teki tcon0_in: port@0 { 363e85f28e0SJagan Teki #address-cells = <1>; 364e85f28e0SJagan Teki #size-cells = <0>; 365e85f28e0SJagan Teki reg = <0>; 366e85f28e0SJagan Teki 367e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 368e85f28e0SJagan Teki reg = <0>; 369e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 370e85f28e0SJagan Teki }; 371a7f7047fSMaxime Ripard 372a7f7047fSMaxime Ripard tcon0_in_mixer1: endpoint@1 { 373a7f7047fSMaxime Ripard reg = <1>; 374a7f7047fSMaxime Ripard remote-endpoint = <&mixer1_out_tcon1>; 375a7f7047fSMaxime Ripard }; 376e85f28e0SJagan Teki }; 377e85f28e0SJagan Teki 378e85f28e0SJagan Teki tcon0_out: port@1 { 379e85f28e0SJagan Teki #address-cells = <1>; 380e85f28e0SJagan Teki #size-cells = <0>; 381e85f28e0SJagan Teki reg = <1>; 382e85f28e0SJagan Teki }; 383e85f28e0SJagan Teki }; 384e85f28e0SJagan Teki }; 385e85f28e0SJagan Teki 386e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 387e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 388e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 389e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 390e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 391e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 392e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 393e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 394e85f28e0SJagan Teki reset-names = "lcd"; 395e85f28e0SJagan Teki 396e85f28e0SJagan Teki ports { 397e85f28e0SJagan Teki #address-cells = <1>; 398e85f28e0SJagan Teki #size-cells = <0>; 399e85f28e0SJagan Teki 400e85f28e0SJagan Teki tcon1_in: port@0 { 401a7f7047fSMaxime Ripard #address-cells = <1>; 402a7f7047fSMaxime Ripard #size-cells = <0>; 403e85f28e0SJagan Teki reg = <0>; 404e85f28e0SJagan Teki 405a7f7047fSMaxime Ripard tcon1_in_mixer0: endpoint@0 { 406a7f7047fSMaxime Ripard reg = <0>; 407a7f7047fSMaxime Ripard remote-endpoint = <&mixer0_out_tcon1>; 408a7f7047fSMaxime Ripard }; 409a7f7047fSMaxime Ripard 410a7f7047fSMaxime Ripard tcon1_in_mixer1: endpoint@1 { 411a7f7047fSMaxime Ripard reg = <1>; 412e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 413e85f28e0SJagan Teki }; 414e85f28e0SJagan Teki }; 415e85f28e0SJagan Teki 416e85f28e0SJagan Teki tcon1_out: port@1 { 417e85f28e0SJagan Teki #address-cells = <1>; 418e85f28e0SJagan Teki #size-cells = <0>; 419e85f28e0SJagan Teki reg = <1>; 420e85f28e0SJagan Teki 421e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 422e85f28e0SJagan Teki reg = <1>; 423e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 424e85f28e0SJagan Teki }; 425e85f28e0SJagan Teki }; 426e85f28e0SJagan Teki }; 427e85f28e0SJagan Teki }; 428e85f28e0SJagan Teki 429d60ce247SPaul Kocialkowski video-codec@1c0e000 { 4304ab88516SPaul Kocialkowski compatible = "allwinner,sun50i-a64-video-engine"; 431d60ce247SPaul Kocialkowski reg = <0x01c0e000 0x1000>; 432d60ce247SPaul Kocialkowski clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 433d60ce247SPaul Kocialkowski <&ccu CLK_DRAM_VE>; 434d60ce247SPaul Kocialkowski clock-names = "ahb", "mod", "ram"; 435d60ce247SPaul Kocialkowski resets = <&ccu RST_BUS_VE>; 436d60ce247SPaul Kocialkowski interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 437d60ce247SPaul Kocialkowski allwinner,sram = <&ve_sram 1>; 438d60ce247SPaul Kocialkowski }; 439d60ce247SPaul Kocialkowski 440f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 441f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 442f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 443f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 444f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 445f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 446f3dff347SAndre Przywara reset-names = "ahb"; 447f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 44822be992fSMaxime Ripard max-frequency = <150000000>; 449f3dff347SAndre Przywara status = "disabled"; 450f3dff347SAndre Przywara #address-cells = <1>; 451f3dff347SAndre Przywara #size-cells = <0>; 452f3dff347SAndre Przywara }; 453f3dff347SAndre Przywara 454f3dff347SAndre Przywara mmc1: mmc@1c10000 { 455f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 456f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 457f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 458f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 459f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 460f3dff347SAndre Przywara reset-names = "ahb"; 461f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 46222be992fSMaxime Ripard max-frequency = <150000000>; 463f3dff347SAndre Przywara status = "disabled"; 464f3dff347SAndre Przywara #address-cells = <1>; 465f3dff347SAndre Przywara #size-cells = <0>; 466f3dff347SAndre Przywara }; 467f3dff347SAndre Przywara 468f3dff347SAndre Przywara mmc2: mmc@1c11000 { 469f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 470f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 471f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 472f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 473f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 474f3dff347SAndre Przywara reset-names = "ahb"; 475f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 47622be992fSMaxime Ripard max-frequency = <200000000>; 477f3dff347SAndre Przywara status = "disabled"; 478f3dff347SAndre Przywara #address-cells = <1>; 479f3dff347SAndre Przywara #size-cells = <0>; 480f3dff347SAndre Przywara }; 481f3dff347SAndre Przywara 482ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 483ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 484ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 485ac947b17SEmmanuel Vadot }; 486ac947b17SEmmanuel Vadot 487d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 488972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 489972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 490972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 491972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 492972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 493972a3ecdSIcenowy Zheng interrupt-names = "mc"; 494972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 495972a3ecdSIcenowy Zheng phy-names = "usb"; 496972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 497972a3ecdSIcenowy Zheng status = "disabled"; 498972a3ecdSIcenowy Zheng }; 499972a3ecdSIcenowy Zheng 500d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 501a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 502a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 5030d984797SIcenowy Zheng <0x01c1a800 0x4>, 504a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 505a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 5060d984797SIcenowy Zheng "pmu0", 507a004ee35SIcenowy Zheng "pmu1"; 508a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 509a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 510a004ee35SIcenowy Zheng clock-names = "usb0_phy", 511a004ee35SIcenowy Zheng "usb1_phy"; 512a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 513a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 514a004ee35SIcenowy Zheng reset-names = "usb0_reset", 515a004ee35SIcenowy Zheng "usb1_reset"; 516a004ee35SIcenowy Zheng status = "disabled"; 517a004ee35SIcenowy Zheng #phy-cells = <1>; 518a004ee35SIcenowy Zheng }; 519a004ee35SIcenowy Zheng 520d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 521dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 522dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 523dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 524dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 525dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 526dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 527dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 528dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 529dc03a047SIcenowy Zheng status = "disabled"; 530dc03a047SIcenowy Zheng }; 531dc03a047SIcenowy Zheng 532d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 533dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 534dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 535dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 536dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 537dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 538dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 539dc03a047SIcenowy Zheng status = "disabled"; 540dc03a047SIcenowy Zheng }; 541dc03a047SIcenowy Zheng 542d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 543a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 544a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 545a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 546a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 547a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 548a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 549a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 550a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 551a004ee35SIcenowy Zheng phys = <&usbphy 1>; 552a004ee35SIcenowy Zheng phy-names = "usb"; 553a004ee35SIcenowy Zheng status = "disabled"; 554a004ee35SIcenowy Zheng }; 555a004ee35SIcenowy Zheng 556d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 557a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 558a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 559a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 560a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 561a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 562a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 563a004ee35SIcenowy Zheng phys = <&usbphy 1>; 564a004ee35SIcenowy Zheng phy-names = "usb"; 565a004ee35SIcenowy Zheng status = "disabled"; 566a004ee35SIcenowy Zheng }; 567a004ee35SIcenowy Zheng 568d6c9da12SCorentin LABBE ccu: clock@1c20000 { 5696bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 5706bc37facSAndre Przywara reg = <0x01c20000 0x400>; 57144ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>; 5726bc37facSAndre Przywara clock-names = "hosc", "losc"; 5736bc37facSAndre Przywara #clock-cells = <1>; 5746bc37facSAndre Przywara #reset-cells = <1>; 5756bc37facSAndre Przywara }; 5766bc37facSAndre Przywara 5776bc37facSAndre Przywara pio: pinctrl@1c20800 { 5786bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 5796bc37facSAndre Przywara reg = <0x01c20800 0x400>; 5806bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 5816bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 5826bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 583f98121f3SArnd Bergmann clocks = <&ccu 58>; 5846bc37facSAndre Przywara gpio-controller; 5856bc37facSAndre Przywara #gpio-cells = <3>; 5866bc37facSAndre Przywara interrupt-controller; 5876bc37facSAndre Przywara #interrupt-cells = <3>; 5886bc37facSAndre Przywara 589ff29f13eSJagan Teki csi_pins: csi-pins { 590ff29f13eSJagan Teki pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 591ff29f13eSJagan Teki "PE7", "PE8", "PE9", "PE10", "PE11"; 592ff29f13eSJagan Teki function = "csi"; 593ff29f13eSJagan Teki }; 594ff29f13eSJagan Teki 59511239fe6SHarald Geyer i2c0_pins: i2c0_pins { 59611239fe6SHarald Geyer pins = "PH0", "PH1"; 59711239fe6SHarald Geyer function = "i2c0"; 59811239fe6SHarald Geyer }; 59911239fe6SHarald Geyer 6006bc37facSAndre Przywara i2c1_pins: i2c1_pins { 6016bc37facSAndre Przywara pins = "PH2", "PH3"; 6026bc37facSAndre Przywara function = "i2c1"; 6036bc37facSAndre Przywara }; 6046bc37facSAndre Przywara 605a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 606a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 607a3e8f492SMaxime Ripard "PF4", "PF5"; 608a3e8f492SMaxime Ripard function = "mmc0"; 609a3e8f492SMaxime Ripard drive-strength = <30>; 610a3e8f492SMaxime Ripard bias-pull-up; 611a3e8f492SMaxime Ripard }; 612a3e8f492SMaxime Ripard 613a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 614a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 615a3e8f492SMaxime Ripard "PG4", "PG5"; 616a3e8f492SMaxime Ripard function = "mmc1"; 617a3e8f492SMaxime Ripard drive-strength = <30>; 618a3e8f492SMaxime Ripard bias-pull-up; 619a3e8f492SMaxime Ripard }; 620a3e8f492SMaxime Ripard 621a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 622fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 623a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 624a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 625a3e8f492SMaxime Ripard function = "mmc2"; 626a3e8f492SMaxime Ripard drive-strength = <30>; 627a3e8f492SMaxime Ripard bias-pull-up; 628a3e8f492SMaxime Ripard }; 629a3e8f492SMaxime Ripard 630fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 631fa59dd2eSChen-Yu Tsai pins = "PC1"; 632fa59dd2eSChen-Yu Tsai function = "mmc2"; 633fa59dd2eSChen-Yu Tsai drive-strength = <30>; 634fa59dd2eSChen-Yu Tsai bias-pull-up; 635fa59dd2eSChen-Yu Tsai }; 636fa59dd2eSChen-Yu Tsai 637b5df280bSAndre Przywara pwm_pin: pwm_pin { 638b5df280bSAndre Przywara pins = "PD22"; 639b5df280bSAndre Przywara function = "pwm"; 640b5df280bSAndre Przywara }; 641b5df280bSAndre Przywara 642e53f67e9SCorentin Labbe rmii_pins: rmii_pins { 643e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 644e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 645e53f67e9SCorentin Labbe function = "emac"; 646e53f67e9SCorentin Labbe drive-strength = <40>; 647e53f67e9SCorentin Labbe }; 648e53f67e9SCorentin Labbe 649e53f67e9SCorentin Labbe rgmii_pins: rgmii_pins { 650e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 651e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 652e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 653e53f67e9SCorentin Labbe function = "emac"; 654e53f67e9SCorentin Labbe drive-strength = <40>; 655e53f67e9SCorentin Labbe }; 656e53f67e9SCorentin Labbe 657b399d2acSMarcus Cooper spdif_tx_pin: spdif { 658b399d2acSMarcus Cooper pins = "PH8"; 659b399d2acSMarcus Cooper function = "spdif"; 660b399d2acSMarcus Cooper }; 661b399d2acSMarcus Cooper 662b518bb15SStefan Brüns spi0_pins: spi0 { 663b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 664b518bb15SStefan Brüns function = "spi0"; 665b518bb15SStefan Brüns }; 666b518bb15SStefan Brüns 667b518bb15SStefan Brüns spi1_pins: spi1 { 668b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 669b518bb15SStefan Brüns function = "spi1"; 670b518bb15SStefan Brüns }; 671b518bb15SStefan Brüns 672d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 6736bc37facSAndre Przywara pins = "PB8", "PB9"; 6746bc37facSAndre Przywara function = "uart0"; 6756bc37facSAndre Przywara }; 676e7ba733dSAndre Przywara 677e7ba733dSAndre Przywara uart1_pins: uart1_pins { 678e7ba733dSAndre Przywara pins = "PG6", "PG7"; 679e7ba733dSAndre Przywara function = "uart1"; 680e7ba733dSAndre Przywara }; 681e7ba733dSAndre Przywara 682e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 683e7ba733dSAndre Przywara pins = "PG8", "PG9"; 684e7ba733dSAndre Przywara function = "uart1"; 685e7ba733dSAndre Przywara }; 68679825719SAndreas Färber 68779825719SAndreas Färber uart2_pins: uart2-pins { 68879825719SAndreas Färber pins = "PB0", "PB1"; 68979825719SAndreas Färber function = "uart2"; 69079825719SAndreas Färber }; 6912273aa16SAndreas Färber 6922273aa16SAndreas Färber uart3_pins: uart3-pins { 6932273aa16SAndreas Färber pins = "PD0", "PD1"; 6942273aa16SAndreas Färber function = "uart3"; 6952273aa16SAndreas Färber }; 6962273aa16SAndreas Färber 6972273aa16SAndreas Färber uart4_pins: uart4-pins { 6982273aa16SAndreas Färber pins = "PD2", "PD3"; 6992273aa16SAndreas Färber function = "uart4"; 7002273aa16SAndreas Färber }; 7012273aa16SAndreas Färber 7022273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 7032273aa16SAndreas Färber pins = "PD4", "PD5"; 7042273aa16SAndreas Färber function = "uart4"; 7052273aa16SAndreas Färber }; 7066bc37facSAndre Przywara }; 7076bc37facSAndre Przywara 708b399d2acSMarcus Cooper spdif: spdif@1c21000 { 709b399d2acSMarcus Cooper #sound-dai-cells = <0>; 710b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 711b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 712b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 713b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 714b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 715b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 716b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 717b399d2acSMarcus Cooper dmas = <&dma 2>; 718b399d2acSMarcus Cooper dma-names = "tx"; 719b399d2acSMarcus Cooper pinctrl-names = "default"; 720b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 721b399d2acSMarcus Cooper status = "disabled"; 722b399d2acSMarcus Cooper }; 723b399d2acSMarcus Cooper 7241c92c009SMarcus Cooper i2s0: i2s@1c22000 { 7251c92c009SMarcus Cooper #sound-dai-cells = <0>; 7261c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 7271c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 7281c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 7291c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7301c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 7311c92c009SMarcus Cooper clock-names = "apb", "mod"; 7321c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 7331c92c009SMarcus Cooper dma-names = "rx", "tx"; 7341c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 7351c92c009SMarcus Cooper status = "disabled"; 7361c92c009SMarcus Cooper }; 7371c92c009SMarcus Cooper 7381c92c009SMarcus Cooper i2s1: i2s@1c22400 { 7391c92c009SMarcus Cooper #sound-dai-cells = <0>; 7401c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 7411c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 7421c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 7431c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7441c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 7451c92c009SMarcus Cooper clock-names = "apb", "mod"; 7461c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 7471c92c009SMarcus Cooper dma-names = "rx", "tx"; 7481c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 7491c92c009SMarcus Cooper status = "disabled"; 7501c92c009SMarcus Cooper }; 7511c92c009SMarcus Cooper 752ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 753ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 754ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 755ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 756ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 757ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 758ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 759ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 760ec4a9540SVasily Khoruzhick reset-names = "rst"; 761ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 762ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 763ec4a9540SVasily Khoruzhick status = "disabled"; 764ec4a9540SVasily Khoruzhick }; 765ec4a9540SVasily Khoruzhick 766ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 767ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 768ec4a9540SVasily Khoruzhick compatible = "allwinner,sun8i-a33-codec"; 769ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 770ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 771ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 772ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 773ec4a9540SVasily Khoruzhick status = "disabled"; 774ec4a9540SVasily Khoruzhick }; 775ec4a9540SVasily Khoruzhick 7766bc37facSAndre Przywara uart0: serial@1c28000 { 7776bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7786bc37facSAndre Przywara reg = <0x01c28000 0x400>; 7796bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 7806bc37facSAndre Przywara reg-shift = <2>; 7816bc37facSAndre Przywara reg-io-width = <4>; 782494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 783494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 7846bc37facSAndre Przywara status = "disabled"; 7856bc37facSAndre Przywara }; 7866bc37facSAndre Przywara 7876bc37facSAndre Przywara uart1: serial@1c28400 { 7886bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7896bc37facSAndre Przywara reg = <0x01c28400 0x400>; 7906bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 7916bc37facSAndre Przywara reg-shift = <2>; 7926bc37facSAndre Przywara reg-io-width = <4>; 793494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 794494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 7956bc37facSAndre Przywara status = "disabled"; 7966bc37facSAndre Przywara }; 7976bc37facSAndre Przywara 7986bc37facSAndre Przywara uart2: serial@1c28800 { 7996bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8006bc37facSAndre Przywara reg = <0x01c28800 0x400>; 8016bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 8026bc37facSAndre Przywara reg-shift = <2>; 8036bc37facSAndre Przywara reg-io-width = <4>; 804494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 805494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 8066bc37facSAndre Przywara status = "disabled"; 8076bc37facSAndre Przywara }; 8086bc37facSAndre Przywara 8096bc37facSAndre Przywara uart3: serial@1c28c00 { 8106bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8116bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 8126bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 8136bc37facSAndre Przywara reg-shift = <2>; 8146bc37facSAndre Przywara reg-io-width = <4>; 815494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 816494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 8176bc37facSAndre Przywara status = "disabled"; 8186bc37facSAndre Przywara }; 8196bc37facSAndre Przywara 8206bc37facSAndre Przywara uart4: serial@1c29000 { 8216bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8226bc37facSAndre Przywara reg = <0x01c29000 0x400>; 8236bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 8246bc37facSAndre Przywara reg-shift = <2>; 8256bc37facSAndre Przywara reg-io-width = <4>; 826494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 827494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 8286bc37facSAndre Przywara status = "disabled"; 8296bc37facSAndre Przywara }; 8306bc37facSAndre Przywara 8316bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 8326bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8336bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 8346bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 835494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 836494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 8376bc37facSAndre Przywara status = "disabled"; 8386bc37facSAndre Przywara #address-cells = <1>; 8396bc37facSAndre Przywara #size-cells = <0>; 8406bc37facSAndre Przywara }; 8416bc37facSAndre Przywara 8426bc37facSAndre Przywara i2c1: i2c@1c2b000 { 8436bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8446bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 8456bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 846494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 847494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 8486bc37facSAndre Przywara status = "disabled"; 8496bc37facSAndre Przywara #address-cells = <1>; 8506bc37facSAndre Przywara #size-cells = <0>; 8516bc37facSAndre Przywara }; 8526bc37facSAndre Przywara 8536bc37facSAndre Przywara i2c2: i2c@1c2b400 { 8546bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8556bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 8566bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 857494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 858494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 8596bc37facSAndre Przywara status = "disabled"; 8606bc37facSAndre Przywara #address-cells = <1>; 8616bc37facSAndre Przywara #size-cells = <0>; 8626bc37facSAndre Przywara }; 8636bc37facSAndre Przywara 864b518bb15SStefan Brüns 865d6c9da12SCorentin LABBE spi0: spi@1c68000 { 866b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 867b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 868b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 869b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 870b518bb15SStefan Brüns clock-names = "ahb", "mod"; 87106c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 87206c1258aSStefan Brüns dma-names = "rx", "tx"; 873b518bb15SStefan Brüns pinctrl-names = "default"; 874b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 875b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 876b518bb15SStefan Brüns status = "disabled"; 877b518bb15SStefan Brüns num-cs = <1>; 878b518bb15SStefan Brüns #address-cells = <1>; 879b518bb15SStefan Brüns #size-cells = <0>; 880b518bb15SStefan Brüns }; 881b518bb15SStefan Brüns 882d6c9da12SCorentin LABBE spi1: spi@1c69000 { 883b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 884b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 885b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 886b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 887b518bb15SStefan Brüns clock-names = "ahb", "mod"; 88806c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 88906c1258aSStefan Brüns dma-names = "rx", "tx"; 890b518bb15SStefan Brüns pinctrl-names = "default"; 891b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 892b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 893b518bb15SStefan Brüns status = "disabled"; 894b518bb15SStefan Brüns num-cs = <1>; 895b518bb15SStefan Brüns #address-cells = <1>; 896b518bb15SStefan Brüns #size-cells = <0>; 897b518bb15SStefan Brüns }; 898b518bb15SStefan Brüns 89994f44288SCorentin Labbe emac: ethernet@1c30000 { 90094f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 90194f44288SCorentin Labbe syscon = <&syscon>; 90294f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 90394f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 90494f44288SCorentin Labbe interrupt-names = "macirq"; 90594f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 90694f44288SCorentin Labbe reset-names = "stmmaceth"; 90794f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 90894f44288SCorentin Labbe clock-names = "stmmaceth"; 90994f44288SCorentin Labbe status = "disabled"; 91094f44288SCorentin Labbe 91194f44288SCorentin Labbe mdio: mdio { 91216416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 91394f44288SCorentin Labbe #address-cells = <1>; 91494f44288SCorentin Labbe #size-cells = <0>; 91594f44288SCorentin Labbe }; 91694f44288SCorentin Labbe }; 91794f44288SCorentin Labbe 9186b683d76SJagan Teki mali: gpu@1c40000 { 9196b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 9206b683d76SJagan Teki reg = <0x01c40000 0x10000>; 9216b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 9226b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 9236b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 9246b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 9256b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 9266b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 9276b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 9286b683d76SJagan Teki interrupt-names = "gp", 9296b683d76SJagan Teki "gpmmu", 9306b683d76SJagan Teki "pp0", 9316b683d76SJagan Teki "ppmmu0", 9326b683d76SJagan Teki "pp1", 9336b683d76SJagan Teki "ppmmu1", 9346b683d76SJagan Teki "pmu"; 9356b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 9366b683d76SJagan Teki clock-names = "bus", "core"; 9376b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 9386b683d76SJagan Teki }; 9396b683d76SJagan Teki 9406bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 9416bc37facSAndre Przywara compatible = "arm,gic-400"; 9426bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 9436bc37facSAndre Przywara <0x01c82000 0x2000>, 9446bc37facSAndre Przywara <0x01c84000 0x2000>, 9456bc37facSAndre Przywara <0x01c86000 0x2000>; 9466bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 9476bc37facSAndre Przywara interrupt-controller; 9486bc37facSAndre Przywara #interrupt-cells = <3>; 9496bc37facSAndre Przywara }; 9506bc37facSAndre Przywara 951b5df280bSAndre Przywara pwm: pwm@1c21400 { 952b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 953b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 954b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 955b5df280bSAndre Przywara clocks = <&osc24M>; 956b5df280bSAndre Przywara pinctrl-names = "default"; 957b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 958b5df280bSAndre Przywara #pwm-cells = <3>; 959b5df280bSAndre Przywara status = "disabled"; 960b5df280bSAndre Przywara }; 961b5df280bSAndre Przywara 962ff29f13eSJagan Teki csi: csi@1cb0000 { 963ff29f13eSJagan Teki compatible = "allwinner,sun50i-a64-csi"; 964ff29f13eSJagan Teki reg = <0x01cb0000 0x1000>; 965ff29f13eSJagan Teki interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 966ff29f13eSJagan Teki clocks = <&ccu CLK_BUS_CSI>, 967ff29f13eSJagan Teki <&ccu CLK_CSI_SCLK>, 968ff29f13eSJagan Teki <&ccu CLK_DRAM_CSI>; 969ff29f13eSJagan Teki clock-names = "bus", "mod", "ram"; 970ff29f13eSJagan Teki resets = <&ccu RST_BUS_CSI>; 971ff29f13eSJagan Teki pinctrl-names = "default"; 972ff29f13eSJagan Teki pinctrl-0 = <&csi_pins>; 973ff29f13eSJagan Teki status = "disabled"; 974ff29f13eSJagan Teki }; 975ff29f13eSJagan Teki 976e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 977e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 978e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 979e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 980e85f28e0SJagan Teki reg-io-width = <1>; 981e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 982e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 983e85f28e0SJagan Teki <&ccu CLK_HDMI>; 984e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 985e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 986e85f28e0SJagan Teki reset-names = "ctrl"; 987e85f28e0SJagan Teki phys = <&hdmi_phy>; 988e85f28e0SJagan Teki phy-names = "hdmi-phy"; 989e85f28e0SJagan Teki status = "disabled"; 990e85f28e0SJagan Teki 991e85f28e0SJagan Teki ports { 992e85f28e0SJagan Teki #address-cells = <1>; 993e85f28e0SJagan Teki #size-cells = <0>; 994e85f28e0SJagan Teki 995e85f28e0SJagan Teki hdmi_in: port@0 { 996e85f28e0SJagan Teki reg = <0>; 997e85f28e0SJagan Teki 998e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 999e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 1000e85f28e0SJagan Teki }; 1001e85f28e0SJagan Teki }; 1002e85f28e0SJagan Teki 1003e85f28e0SJagan Teki hdmi_out: port@1 { 1004e85f28e0SJagan Teki reg = <1>; 1005e85f28e0SJagan Teki }; 1006e85f28e0SJagan Teki }; 1007e85f28e0SJagan Teki }; 1008e85f28e0SJagan Teki 1009e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 1010e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 1011e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 1012e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1013e85f28e0SJagan Teki <&ccu 7>; 1014e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 1015e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 1016e85f28e0SJagan Teki reset-names = "phy"; 1017e85f28e0SJagan Teki #phy-cells = <0>; 1018e85f28e0SJagan Teki }; 1019e85f28e0SJagan Teki 10206bc37facSAndre Przywara rtc: rtc@1f00000 { 102144ff3cafSChen-Yu Tsai compatible = "allwinner,sun50i-a64-rtc", 102244ff3cafSChen-Yu Tsai "allwinner,sun8i-h3-rtc"; 102344ff3cafSChen-Yu Tsai reg = <0x01f00000 0x400>; 10246bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 10256bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 102644ff3cafSChen-Yu Tsai clock-output-names = "osc32k", "osc32k-out", "iosc"; 1027e1a9a474SJagan Teki clocks = <&osc32k>; 1028e1a9a474SJagan Teki #clock-cells = <1>; 10296bc37facSAndre Przywara }; 1030791a9e00SIcenowy Zheng 1031535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 1032535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 1033535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 1034535ca508SIcenowy Zheng interrupt-controller; 1035535ca508SIcenowy Zheng #interrupt-cells = <2>; 1036535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 1037535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1038535ca508SIcenowy Zheng }; 1039535ca508SIcenowy Zheng 1040791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 1041791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 1042791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 104344ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1044f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 1045791a9e00SIcenowy Zheng #clock-cells = <1>; 1046791a9e00SIcenowy Zheng #reset-cells = <1>; 1047791a9e00SIcenowy Zheng }; 1048ec427905SIcenowy Zheng 1049ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 1050ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 1051ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 1052ec4a9540SVasily Khoruzhick status = "disabled"; 1053ec4a9540SVasily Khoruzhick }; 1054ec4a9540SVasily Khoruzhick 1055871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 1056871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 1057871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 1058871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 1059871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1060871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1061871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1062871b5352SIcenowy Zheng status = "disabled"; 1063871b5352SIcenowy Zheng #address-cells = <1>; 1064871b5352SIcenowy Zheng #size-cells = <0>; 1065871b5352SIcenowy Zheng }; 1066871b5352SIcenowy Zheng 1067b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1068b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1069b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1070b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1071b5df280bSAndre Przywara clocks = <&osc24M>; 1072b5df280bSAndre Przywara pinctrl-names = "default"; 1073b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1074b5df280bSAndre Przywara #pwm-cells = <3>; 1075b5df280bSAndre Przywara status = "disabled"; 1076b5df280bSAndre Przywara }; 1077b5df280bSAndre Przywara 1078d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1079ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1080ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1081ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1082494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1083ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1084ec427905SIcenowy Zheng gpio-controller; 1085ec427905SIcenowy Zheng #gpio-cells = <3>; 1086ec427905SIcenowy Zheng interrupt-controller; 1087ec427905SIcenowy Zheng #interrupt-cells = <3>; 10883b38fdedSIcenowy Zheng 10891b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1090871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1091871b5352SIcenowy Zheng function = "s_i2c"; 1092871b5352SIcenowy Zheng }; 1093871b5352SIcenowy Zheng 1094b5df280bSAndre Przywara r_pwm_pin: pwm { 1095b5df280bSAndre Przywara pins = "PL10"; 1096b5df280bSAndre Przywara function = "s_pwm"; 1097b5df280bSAndre Przywara }; 1098b5df280bSAndre Przywara 109992d378fbSCorentin LABBE r_rsb_pins: rsb { 11003b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 11013b38fdedSIcenowy Zheng function = "s_rsb"; 11023b38fdedSIcenowy Zheng }; 11033b38fdedSIcenowy Zheng }; 11043b38fdedSIcenowy Zheng 11053b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 11063b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 11073b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 11083b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 11093b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 11103b38fdedSIcenowy Zheng clock-frequency = <3000000>; 11113b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 11123b38fdedSIcenowy Zheng pinctrl-names = "default"; 11133b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 11143b38fdedSIcenowy Zheng status = "disabled"; 11153b38fdedSIcenowy Zheng #address-cells = <1>; 11163b38fdedSIcenowy Zheng #size-cells = <0>; 1117ec427905SIcenowy Zheng }; 1118d4185043SHarald Geyer 1119d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 1120d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 1121d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 1122d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 1123d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1124d4185043SHarald Geyer }; 11256bc37facSAndre Przywara }; 11266bc37facSAndre Przywara}; 1127