1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd. 3cabbaed7SClément Péron// based on the Allwinner H3 dtsi: 4cabbaed7SClément Péron// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara 6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 72c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 8494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 96bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 10a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 112c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 12871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 1359f5e9b9SVasily Khoruzhick#include <dt-bindings/thermal/thermal.h> 146bc37facSAndre Przywara 156bc37facSAndre Przywara/ { 166bc37facSAndre Przywara interrupt-parent = <&gic>; 176bc37facSAndre Przywara #address-cells = <1>; 186bc37facSAndre Przywara #size-cells = <1>; 196bc37facSAndre Przywara 20c1cff65fSHarald Geyer chosen { 21c1cff65fSHarald Geyer #address-cells = <1>; 22c1cff65fSHarald Geyer #size-cells = <1>; 23c1cff65fSHarald Geyer ranges; 24c1cff65fSHarald Geyer 25c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 26c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 27c1cff65fSHarald Geyer "simple-framebuffer"; 28c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 29c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 302c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 31c1cff65fSHarald Geyer status = "disabled"; 32c1cff65fSHarald Geyer }; 33fca63f58SIcenowy Zheng 34fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 35fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 36fca63f58SIcenowy Zheng "simple-framebuffer"; 37fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 38fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 39fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40fca63f58SIcenowy Zheng status = "disabled"; 41fca63f58SIcenowy Zheng }; 42c1cff65fSHarald Geyer }; 43c1cff65fSHarald Geyer 446bc37facSAndre Przywara cpus { 456bc37facSAndre Przywara #address-cells = <1>; 466bc37facSAndre Przywara #size-cells = <0>; 476bc37facSAndre Przywara 486bc37facSAndre Przywara cpu0: cpu@0 { 4931af04cdSRob Herring compatible = "arm,cortex-a53"; 506bc37facSAndre Przywara device_type = "cpu"; 516bc37facSAndre Przywara reg = <0>; 526bc37facSAndre Przywara enable-method = "psci"; 5339defc81SAndre Przywara next-level-cache = <&L2>; 547db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 55f267eff7SVasily Khoruzhick clock-names = "cpu"; 56e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 576bc37facSAndre Przywara }; 586bc37facSAndre Przywara 596bc37facSAndre Przywara cpu1: cpu@1 { 6031af04cdSRob Herring compatible = "arm,cortex-a53"; 616bc37facSAndre Przywara device_type = "cpu"; 626bc37facSAndre Przywara reg = <1>; 636bc37facSAndre Przywara enable-method = "psci"; 6439defc81SAndre Przywara next-level-cache = <&L2>; 657db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 66f267eff7SVasily Khoruzhick clock-names = "cpu"; 67e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 686bc37facSAndre Przywara }; 696bc37facSAndre Przywara 706bc37facSAndre Przywara cpu2: cpu@2 { 7131af04cdSRob Herring compatible = "arm,cortex-a53"; 726bc37facSAndre Przywara device_type = "cpu"; 736bc37facSAndre Przywara reg = <2>; 746bc37facSAndre Przywara enable-method = "psci"; 7539defc81SAndre Przywara next-level-cache = <&L2>; 767db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 77f267eff7SVasily Khoruzhick clock-names = "cpu"; 78e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 796bc37facSAndre Przywara }; 806bc37facSAndre Przywara 816bc37facSAndre Przywara cpu3: cpu@3 { 8231af04cdSRob Herring compatible = "arm,cortex-a53"; 836bc37facSAndre Przywara device_type = "cpu"; 846bc37facSAndre Przywara reg = <3>; 856bc37facSAndre Przywara enable-method = "psci"; 8639defc81SAndre Przywara next-level-cache = <&L2>; 877db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 88f267eff7SVasily Khoruzhick clock-names = "cpu"; 89e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 9039defc81SAndre Przywara }; 9139defc81SAndre Przywara 9239defc81SAndre Przywara L2: l2-cache { 9339defc81SAndre Przywara compatible = "cache"; 9439defc81SAndre Przywara cache-level = <2>; 956bc37facSAndre Przywara }; 966bc37facSAndre Przywara }; 976bc37facSAndre Przywara 98e85f28e0SJagan Teki de: display-engine { 99e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 100e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 101e85f28e0SJagan Teki <&mixer1>; 102e85f28e0SJagan Teki status = "disabled"; 103e85f28e0SJagan Teki }; 104e85f28e0SJagan Teki 1056bc37facSAndre Przywara osc24M: osc24M_clk { 1066bc37facSAndre Przywara #clock-cells = <0>; 1076bc37facSAndre Przywara compatible = "fixed-clock"; 1086bc37facSAndre Przywara clock-frequency = <24000000>; 1096bc37facSAndre Przywara clock-output-names = "osc24M"; 1106bc37facSAndre Przywara }; 1116bc37facSAndre Przywara 1126bc37facSAndre Przywara osc32k: osc32k_clk { 1136bc37facSAndre Przywara #clock-cells = <0>; 1146bc37facSAndre Przywara compatible = "fixed-clock"; 1156bc37facSAndre Przywara clock-frequency = <32768>; 11644ff3cafSChen-Yu Tsai clock-output-names = "ext-osc32k"; 117791a9e00SIcenowy Zheng }; 118791a9e00SIcenowy Zheng 11934a97fccSHarald Geyer pmu { 12034a97fccSHarald Geyer compatible = "arm,cortex-a53-pmu"; 1216b832a14SAndre Przywara interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1226b832a14SAndre Przywara <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1236b832a14SAndre Przywara <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1246b832a14SAndre Przywara <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 12534a97fccSHarald Geyer interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 12634a97fccSHarald Geyer }; 12734a97fccSHarald Geyer 1286bc37facSAndre Przywara psci { 1296bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1306bc37facSAndre Przywara method = "smc"; 1316bc37facSAndre Przywara }; 1326bc37facSAndre Przywara 133ec4a9540SVasily Khoruzhick sound: sound { 134*984a51c5SSamuel Holland #address-cells = <1>; 135*984a51c5SSamuel Holland #size-cells = <0>; 136ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 137ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 138ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 139ec4a9540SVasily Khoruzhick simple-audio-card,routing = 140631e6a35SSamuel Holland "Left DAC", "DACL", 141631e6a35SSamuel Holland "Right DAC", "DACR", 142631e6a35SSamuel Holland "ADCL", "Left ADC", 143631e6a35SSamuel Holland "ADCR", "Right ADC"; 144ec4a9540SVasily Khoruzhick status = "disabled"; 145ec4a9540SVasily Khoruzhick 146*984a51c5SSamuel Holland simple-audio-card,dai-link@0 { 147*984a51c5SSamuel Holland format = "i2s"; 148*984a51c5SSamuel Holland frame-master = <&link0_cpu>; 149*984a51c5SSamuel Holland bitclock-master = <&link0_cpu>; 150*984a51c5SSamuel Holland mclk-fs = <128>; 151*984a51c5SSamuel Holland 152*984a51c5SSamuel Holland link0_cpu: cpu { 153ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 154ec4a9540SVasily Khoruzhick }; 155ec4a9540SVasily Khoruzhick 156*984a51c5SSamuel Holland link0_codec: codec { 157e0cd8e01SSamuel Holland sound-dai = <&codec 0>; 158ec4a9540SVasily Khoruzhick }; 159ec4a9540SVasily Khoruzhick }; 160*984a51c5SSamuel Holland }; 161ec4a9540SVasily Khoruzhick 1626bc37facSAndre Przywara timer { 1636bc37facSAndre Przywara compatible = "arm,armv8-timer"; 16455ec26d6SSamuel Holland allwinner,erratum-unknown1; 165a371b1bdSSamuel Holland arm,no-tick-in-suspend; 1666bc37facSAndre Przywara interrupts = <GIC_PPI 13 1676bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1686bc37facSAndre Przywara <GIC_PPI 14 1696bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1706bc37facSAndre Przywara <GIC_PPI 11 1716bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1726bc37facSAndre Przywara <GIC_PPI 10 1736bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1746bc37facSAndre Przywara }; 1756bc37facSAndre Przywara 17659f5e9b9SVasily Khoruzhick thermal-zones { 17759f5e9b9SVasily Khoruzhick cpu_thermal: cpu0-thermal { 17859f5e9b9SVasily Khoruzhick /* milliseconds */ 17959f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 18059f5e9b9SVasily Khoruzhick polling-delay = <0>; 18159f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 0>; 182e1c3804aSVasily Khoruzhick 183e1c3804aSVasily Khoruzhick cooling-maps { 184e1c3804aSVasily Khoruzhick map0 { 185e1c3804aSVasily Khoruzhick trip = <&cpu_alert0>; 186e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 187e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 188e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 189e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 190e1c3804aSVasily Khoruzhick }; 191e1c3804aSVasily Khoruzhick map1 { 192e1c3804aSVasily Khoruzhick trip = <&cpu_alert1>; 193e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 194e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 195e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 196e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 197e1c3804aSVasily Khoruzhick }; 198e1c3804aSVasily Khoruzhick }; 199e1c3804aSVasily Khoruzhick 200e1c3804aSVasily Khoruzhick trips { 201e1c3804aSVasily Khoruzhick cpu_alert0: cpu_alert0 { 202e1c3804aSVasily Khoruzhick /* milliCelsius */ 203e1c3804aSVasily Khoruzhick temperature = <75000>; 204e1c3804aSVasily Khoruzhick hysteresis = <2000>; 205e1c3804aSVasily Khoruzhick type = "passive"; 206e1c3804aSVasily Khoruzhick }; 207e1c3804aSVasily Khoruzhick 208e1c3804aSVasily Khoruzhick cpu_alert1: cpu_alert1 { 209e1c3804aSVasily Khoruzhick /* milliCelsius */ 210e1c3804aSVasily Khoruzhick temperature = <90000>; 211e1c3804aSVasily Khoruzhick hysteresis = <2000>; 212e1c3804aSVasily Khoruzhick type = "hot"; 213e1c3804aSVasily Khoruzhick }; 214e1c3804aSVasily Khoruzhick 215e1c3804aSVasily Khoruzhick cpu_crit: cpu_crit { 216e1c3804aSVasily Khoruzhick /* milliCelsius */ 217e1c3804aSVasily Khoruzhick temperature = <110000>; 218e1c3804aSVasily Khoruzhick hysteresis = <2000>; 219e1c3804aSVasily Khoruzhick type = "critical"; 220e1c3804aSVasily Khoruzhick }; 221e1c3804aSVasily Khoruzhick }; 22259f5e9b9SVasily Khoruzhick }; 22359f5e9b9SVasily Khoruzhick 22459f5e9b9SVasily Khoruzhick gpu0_thermal: gpu0-thermal { 22559f5e9b9SVasily Khoruzhick /* milliseconds */ 22659f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 22759f5e9b9SVasily Khoruzhick polling-delay = <0>; 22859f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 1>; 22959f5e9b9SVasily Khoruzhick }; 23059f5e9b9SVasily Khoruzhick 23159f5e9b9SVasily Khoruzhick gpu1_thermal: gpu1-thermal { 23259f5e9b9SVasily Khoruzhick /* milliseconds */ 23359f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 23459f5e9b9SVasily Khoruzhick polling-delay = <0>; 23559f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 2>; 23659f5e9b9SVasily Khoruzhick }; 23759f5e9b9SVasily Khoruzhick }; 23859f5e9b9SVasily Khoruzhick 2396bc37facSAndre Przywara soc { 2406bc37facSAndre Przywara compatible = "simple-bus"; 2416bc37facSAndre Przywara #address-cells = <1>; 2426bc37facSAndre Przywara #size-cells = <1>; 2436bc37facSAndre Przywara ranges; 2446bc37facSAndre Przywara 245275b6317SMaxime Ripard bus@1000000 { 2462c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 2472c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 2482c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 2492c796fc8SIcenowy Zheng #address-cells = <1>; 2502c796fc8SIcenowy Zheng #size-cells = <1>; 2512c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 2522c796fc8SIcenowy Zheng 2532c796fc8SIcenowy Zheng display_clocks: clock@0 { 2542c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 2553e9a1a8bSJernej Skrabec reg = <0x0 0x10000>; 2565ea40f71SMaxime Ripard clocks = <&ccu CLK_BUS_DE>, 2575ea40f71SMaxime Ripard <&ccu CLK_DE>; 2585ea40f71SMaxime Ripard clock-names = "bus", 2595ea40f71SMaxime Ripard "mod"; 2602c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 2612c796fc8SIcenowy Zheng #clock-cells = <1>; 2622c796fc8SIcenowy Zheng #reset-cells = <1>; 2632c796fc8SIcenowy Zheng }; 264e85f28e0SJagan Teki 265048cdfceSJernej Skrabec rotate: rotate@20000 { 266048cdfceSJernej Skrabec compatible = "allwinner,sun50i-a64-de2-rotate", 267048cdfceSJernej Skrabec "allwinner,sun8i-a83t-de2-rotate"; 268048cdfceSJernej Skrabec reg = <0x20000 0x10000>; 269048cdfceSJernej Skrabec interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 270048cdfceSJernej Skrabec clocks = <&display_clocks CLK_BUS_ROT>, 271048cdfceSJernej Skrabec <&display_clocks CLK_ROT>; 272048cdfceSJernej Skrabec clock-names = "bus", 273048cdfceSJernej Skrabec "mod"; 274048cdfceSJernej Skrabec resets = <&display_clocks RST_ROT>; 275048cdfceSJernej Skrabec }; 276048cdfceSJernej Skrabec 277e85f28e0SJagan Teki mixer0: mixer@100000 { 278e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 279e85f28e0SJagan Teki reg = <0x100000 0x100000>; 280e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 281e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 282e85f28e0SJagan Teki clock-names = "bus", 283e85f28e0SJagan Teki "mod"; 284e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 285e85f28e0SJagan Teki 286e85f28e0SJagan Teki ports { 287e85f28e0SJagan Teki #address-cells = <1>; 288e85f28e0SJagan Teki #size-cells = <0>; 289e85f28e0SJagan Teki 290e85f28e0SJagan Teki mixer0_out: port@1 { 291a7f7047fSMaxime Ripard #address-cells = <1>; 292a7f7047fSMaxime Ripard #size-cells = <0>; 293e85f28e0SJagan Teki reg = <1>; 294e85f28e0SJagan Teki 295a7f7047fSMaxime Ripard mixer0_out_tcon0: endpoint@0 { 296a7f7047fSMaxime Ripard reg = <0>; 297e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 298e85f28e0SJagan Teki }; 299a7f7047fSMaxime Ripard 300a7f7047fSMaxime Ripard mixer0_out_tcon1: endpoint@1 { 301a7f7047fSMaxime Ripard reg = <1>; 302a7f7047fSMaxime Ripard remote-endpoint = <&tcon1_in_mixer0>; 303a7f7047fSMaxime Ripard }; 304e85f28e0SJagan Teki }; 305e85f28e0SJagan Teki }; 306e85f28e0SJagan Teki }; 307e85f28e0SJagan Teki 308e85f28e0SJagan Teki mixer1: mixer@200000 { 309e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 310e85f28e0SJagan Teki reg = <0x200000 0x100000>; 311e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 312e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 313e85f28e0SJagan Teki clock-names = "bus", 314e85f28e0SJagan Teki "mod"; 315e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 316e85f28e0SJagan Teki 317e85f28e0SJagan Teki ports { 318e85f28e0SJagan Teki #address-cells = <1>; 319e85f28e0SJagan Teki #size-cells = <0>; 320e85f28e0SJagan Teki 321e85f28e0SJagan Teki mixer1_out: port@1 { 322d41a43a0SMaxime Ripard #address-cells = <1>; 323d41a43a0SMaxime Ripard #size-cells = <0>; 324e85f28e0SJagan Teki reg = <1>; 325e85f28e0SJagan Teki 326a7f7047fSMaxime Ripard mixer1_out_tcon0: endpoint@0 { 327a7f7047fSMaxime Ripard reg = <0>; 328a7f7047fSMaxime Ripard remote-endpoint = <&tcon0_in_mixer1>; 329a7f7047fSMaxime Ripard }; 330a7f7047fSMaxime Ripard 331a7f7047fSMaxime Ripard mixer1_out_tcon1: endpoint@1 { 332a7f7047fSMaxime Ripard reg = <1>; 333e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 334e85f28e0SJagan Teki }; 335e85f28e0SJagan Teki }; 336e85f28e0SJagan Teki }; 337e85f28e0SJagan Teki }; 3382c796fc8SIcenowy Zheng }; 3392c796fc8SIcenowy Zheng 34079b95360SCorentin Labbe syscon: syscon@1c00000 { 3411f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 34279b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 3431f1f5183SIcenowy Zheng #address-cells = <1>; 3441f1f5183SIcenowy Zheng #size-cells = <1>; 3451f1f5183SIcenowy Zheng ranges; 3461f1f5183SIcenowy Zheng 3471f1f5183SIcenowy Zheng sram_c: sram@18000 { 3481f1f5183SIcenowy Zheng compatible = "mmio-sram"; 3491f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 3501f1f5183SIcenowy Zheng #address-cells = <1>; 3511f1f5183SIcenowy Zheng #size-cells = <1>; 3521f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 3531f1f5183SIcenowy Zheng 3541f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 3551f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 3561f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 3571f1f5183SIcenowy Zheng }; 3581f1f5183SIcenowy Zheng }; 359106deea8SPaul Kocialkowski 360106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 361106deea8SPaul Kocialkowski compatible = "mmio-sram"; 362106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 363106deea8SPaul Kocialkowski #address-cells = <1>; 364106deea8SPaul Kocialkowski #size-cells = <1>; 365106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 366106deea8SPaul Kocialkowski 367106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 368106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 369106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 370106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 371106deea8SPaul Kocialkowski }; 372106deea8SPaul Kocialkowski }; 37379b95360SCorentin Labbe }; 37479b95360SCorentin Labbe 375c32637e0SStefan Brüns dma: dma-controller@1c02000 { 376c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 377c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 378c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 379c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 380c32637e0SStefan Brüns dma-channels = <8>; 381c32637e0SStefan Brüns dma-requests = <27>; 382c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 383c32637e0SStefan Brüns #dma-cells = <1>; 384c32637e0SStefan Brüns }; 385c32637e0SStefan Brüns 386e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 387e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 388e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 389e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 390e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 391e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 392e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 393e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 39426c609d5SMaxime Ripard #clock-cells = <0>; 395e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 396e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 397e85f28e0SJagan Teki 398e85f28e0SJagan Teki ports { 399e85f28e0SJagan Teki #address-cells = <1>; 400e85f28e0SJagan Teki #size-cells = <0>; 401e85f28e0SJagan Teki 402e85f28e0SJagan Teki tcon0_in: port@0 { 403e85f28e0SJagan Teki #address-cells = <1>; 404e85f28e0SJagan Teki #size-cells = <0>; 405e85f28e0SJagan Teki reg = <0>; 406e85f28e0SJagan Teki 407e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 408e85f28e0SJagan Teki reg = <0>; 409e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 410e85f28e0SJagan Teki }; 411a7f7047fSMaxime Ripard 412a7f7047fSMaxime Ripard tcon0_in_mixer1: endpoint@1 { 413a7f7047fSMaxime Ripard reg = <1>; 414d41a43a0SMaxime Ripard remote-endpoint = <&mixer1_out_tcon0>; 415a7f7047fSMaxime Ripard }; 416e85f28e0SJagan Teki }; 417e85f28e0SJagan Teki 418e85f28e0SJagan Teki tcon0_out: port@1 { 419e85f28e0SJagan Teki #address-cells = <1>; 420e85f28e0SJagan Teki #size-cells = <0>; 421e85f28e0SJagan Teki reg = <1>; 42216c8ff57SJagan Teki 42316c8ff57SJagan Teki tcon0_out_dsi: endpoint@1 { 42416c8ff57SJagan Teki reg = <1>; 42516c8ff57SJagan Teki remote-endpoint = <&dsi_in_tcon0>; 42616c8ff57SJagan Teki allwinner,tcon-channel = <1>; 42716c8ff57SJagan Teki }; 428e85f28e0SJagan Teki }; 429e85f28e0SJagan Teki }; 430e85f28e0SJagan Teki }; 431e85f28e0SJagan Teki 432e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 433e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 434e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 435e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 436e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 437e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 438e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 439e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 440e85f28e0SJagan Teki reset-names = "lcd"; 441e85f28e0SJagan Teki 442e85f28e0SJagan Teki ports { 443e85f28e0SJagan Teki #address-cells = <1>; 444e85f28e0SJagan Teki #size-cells = <0>; 445e85f28e0SJagan Teki 446e85f28e0SJagan Teki tcon1_in: port@0 { 447a7f7047fSMaxime Ripard #address-cells = <1>; 448a7f7047fSMaxime Ripard #size-cells = <0>; 449e85f28e0SJagan Teki reg = <0>; 450e85f28e0SJagan Teki 451a7f7047fSMaxime Ripard tcon1_in_mixer0: endpoint@0 { 452a7f7047fSMaxime Ripard reg = <0>; 453a7f7047fSMaxime Ripard remote-endpoint = <&mixer0_out_tcon1>; 454a7f7047fSMaxime Ripard }; 455a7f7047fSMaxime Ripard 456a7f7047fSMaxime Ripard tcon1_in_mixer1: endpoint@1 { 457a7f7047fSMaxime Ripard reg = <1>; 458e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 459e85f28e0SJagan Teki }; 460e85f28e0SJagan Teki }; 461e85f28e0SJagan Teki 462e85f28e0SJagan Teki tcon1_out: port@1 { 463e85f28e0SJagan Teki #address-cells = <1>; 464e85f28e0SJagan Teki #size-cells = <0>; 465e85f28e0SJagan Teki reg = <1>; 466e85f28e0SJagan Teki 467e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 468e85f28e0SJagan Teki reg = <1>; 469e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 470e85f28e0SJagan Teki }; 471e85f28e0SJagan Teki }; 472e85f28e0SJagan Teki }; 473e85f28e0SJagan Teki }; 474e85f28e0SJagan Teki 475d60ce247SPaul Kocialkowski video-codec@1c0e000 { 4764ab88516SPaul Kocialkowski compatible = "allwinner,sun50i-a64-video-engine"; 477d60ce247SPaul Kocialkowski reg = <0x01c0e000 0x1000>; 478d60ce247SPaul Kocialkowski clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 479d60ce247SPaul Kocialkowski <&ccu CLK_DRAM_VE>; 480d60ce247SPaul Kocialkowski clock-names = "ahb", "mod", "ram"; 481d60ce247SPaul Kocialkowski resets = <&ccu RST_BUS_VE>; 482d60ce247SPaul Kocialkowski interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 483d60ce247SPaul Kocialkowski allwinner,sram = <&ve_sram 1>; 484d60ce247SPaul Kocialkowski }; 485d60ce247SPaul Kocialkowski 486f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 487f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 488f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 489f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 490f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 491f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 492f3dff347SAndre Przywara reset-names = "ahb"; 493f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 49422be992fSMaxime Ripard max-frequency = <150000000>; 495f3dff347SAndre Przywara status = "disabled"; 496f3dff347SAndre Przywara #address-cells = <1>; 497f3dff347SAndre Przywara #size-cells = <0>; 498f3dff347SAndre Przywara }; 499f3dff347SAndre Przywara 500f3dff347SAndre Przywara mmc1: mmc@1c10000 { 501f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 502f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 503f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 504f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 505f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 506f3dff347SAndre Przywara reset-names = "ahb"; 507f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 50822be992fSMaxime Ripard max-frequency = <150000000>; 509f3dff347SAndre Przywara status = "disabled"; 510f3dff347SAndre Przywara #address-cells = <1>; 511f3dff347SAndre Przywara #size-cells = <0>; 512f3dff347SAndre Przywara }; 513f3dff347SAndre Przywara 514f3dff347SAndre Przywara mmc2: mmc@1c11000 { 515f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 516f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 517f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 518f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 519f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 520f3dff347SAndre Przywara reset-names = "ahb"; 521f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 522948c657cSAndre Przywara max-frequency = <150000000>; 523f3dff347SAndre Przywara status = "disabled"; 524f3dff347SAndre Przywara #address-cells = <1>; 525f3dff347SAndre Przywara #size-cells = <0>; 526f3dff347SAndre Przywara }; 527f3dff347SAndre Przywara 528ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 529ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 530ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 53159f5e9b9SVasily Khoruzhick #address-cells = <1>; 53259f5e9b9SVasily Khoruzhick #size-cells = <1>; 53359f5e9b9SVasily Khoruzhick 53459f5e9b9SVasily Khoruzhick ths_calibration: thermal-sensor-calibration@34 { 53559f5e9b9SVasily Khoruzhick reg = <0x34 0x8>; 53659f5e9b9SVasily Khoruzhick }; 537ac947b17SEmmanuel Vadot }; 538ac947b17SEmmanuel Vadot 5390f5fc158SCorentin Labbe crypto: crypto@1c15000 { 5400f5fc158SCorentin Labbe compatible = "allwinner,sun50i-a64-crypto"; 5410f5fc158SCorentin Labbe reg = <0x01c15000 0x1000>; 5420f5fc158SCorentin Labbe interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 5430f5fc158SCorentin Labbe clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 5440f5fc158SCorentin Labbe clock-names = "bus", "mod"; 5450f5fc158SCorentin Labbe resets = <&ccu RST_BUS_CE>; 5460f5fc158SCorentin Labbe }; 5470f5fc158SCorentin Labbe 5483e3f39a7SSamuel Holland msgbox: mailbox@1c17000 { 5493e3f39a7SSamuel Holland compatible = "allwinner,sun50i-a64-msgbox", 5503e3f39a7SSamuel Holland "allwinner,sun6i-a31-msgbox"; 5513e3f39a7SSamuel Holland reg = <0x01c17000 0x1000>; 5523e3f39a7SSamuel Holland clocks = <&ccu CLK_BUS_MSGBOX>; 5533e3f39a7SSamuel Holland resets = <&ccu RST_BUS_MSGBOX>; 5543e3f39a7SSamuel Holland interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 5553e3f39a7SSamuel Holland #mbox-cells = <1>; 5563e3f39a7SSamuel Holland }; 5573e3f39a7SSamuel Holland 558d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 559972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 560972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 561972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 562972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 563972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 564972a3ecdSIcenowy Zheng interrupt-names = "mc"; 565972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 566972a3ecdSIcenowy Zheng phy-names = "usb"; 567972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 5680973c06bSMaxime Ripard dr_mode = "otg"; 569972a3ecdSIcenowy Zheng status = "disabled"; 570972a3ecdSIcenowy Zheng }; 571972a3ecdSIcenowy Zheng 572d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 573a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 574a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 5750d984797SIcenowy Zheng <0x01c1a800 0x4>, 576a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 577a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 5780d984797SIcenowy Zheng "pmu0", 579a004ee35SIcenowy Zheng "pmu1"; 580a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 581a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 582a004ee35SIcenowy Zheng clock-names = "usb0_phy", 583a004ee35SIcenowy Zheng "usb1_phy"; 584a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 585a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 586a004ee35SIcenowy Zheng reset-names = "usb0_reset", 587a004ee35SIcenowy Zheng "usb1_reset"; 588a004ee35SIcenowy Zheng status = "disabled"; 589a004ee35SIcenowy Zheng #phy-cells = <1>; 590a004ee35SIcenowy Zheng }; 591a004ee35SIcenowy Zheng 592d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 593dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 594dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 595dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 596dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 597dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 598dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 599dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 600dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 601cc725707SAndre Przywara phys = <&usbphy 0>; 602cc725707SAndre Przywara phy-names = "usb"; 603dc03a047SIcenowy Zheng status = "disabled"; 604dc03a047SIcenowy Zheng }; 605dc03a047SIcenowy Zheng 606d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 607dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 608dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 609dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 610dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 611dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 612dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 613cc725707SAndre Przywara phys = <&usbphy 0>; 614cc725707SAndre Przywara phy-names = "usb"; 615dc03a047SIcenowy Zheng status = "disabled"; 616dc03a047SIcenowy Zheng }; 617dc03a047SIcenowy Zheng 618d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 619a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 620a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 621a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 622a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 623a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 624a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 625a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 626a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 627a004ee35SIcenowy Zheng phys = <&usbphy 1>; 628e6064cf4SMaxime Ripard phy-names = "usb"; 629a004ee35SIcenowy Zheng status = "disabled"; 630a004ee35SIcenowy Zheng }; 631a004ee35SIcenowy Zheng 632d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 633a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 634a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 635a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 636a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 637a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 638a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 639a004ee35SIcenowy Zheng phys = <&usbphy 1>; 640e6064cf4SMaxime Ripard phy-names = "usb"; 641a004ee35SIcenowy Zheng status = "disabled"; 642a004ee35SIcenowy Zheng }; 643a004ee35SIcenowy Zheng 644d6c9da12SCorentin LABBE ccu: clock@1c20000 { 6456bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 6466bc37facSAndre Przywara reg = <0x01c20000 0x400>; 64744ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>; 6486bc37facSAndre Przywara clock-names = "hosc", "losc"; 6496bc37facSAndre Przywara #clock-cells = <1>; 6506bc37facSAndre Przywara #reset-cells = <1>; 6516bc37facSAndre Przywara }; 6526bc37facSAndre Przywara 6536bc37facSAndre Przywara pio: pinctrl@1c20800 { 6546bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 6556bc37facSAndre Przywara reg = <0x01c20800 0x400>; 656189bef23SSamuel Holland interrupt-parent = <&r_intc>; 6576bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 6586bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 6596bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 660b71818cbSChen-Yu Tsai clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 661562bf196SMaxime Ripard clock-names = "apb", "hosc", "losc"; 6626bc37facSAndre Przywara gpio-controller; 6636bc37facSAndre Przywara #gpio-cells = <3>; 6646bc37facSAndre Przywara interrupt-controller; 6656bc37facSAndre Przywara #interrupt-cells = <3>; 6666bc37facSAndre Przywara 66709e0a7eaSSamuel Holland /omit-if-no-ref/ 66809e0a7eaSSamuel Holland aif2_pins: aif2-pins { 66909e0a7eaSSamuel Holland pins = "PB4", "PB5", "PB6", "PB7"; 67009e0a7eaSSamuel Holland function = "aif2"; 67109e0a7eaSSamuel Holland }; 67209e0a7eaSSamuel Holland 67309e0a7eaSSamuel Holland /omit-if-no-ref/ 67409e0a7eaSSamuel Holland aif3_pins: aif3-pins { 67509e0a7eaSSamuel Holland pins = "PG10", "PG11", "PG12", "PG13"; 67609e0a7eaSSamuel Holland function = "aif3"; 67709e0a7eaSSamuel Holland }; 67809e0a7eaSSamuel Holland 679ff29f13eSJagan Teki csi_pins: csi-pins { 680ff29f13eSJagan Teki pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 681ff29f13eSJagan Teki "PE7", "PE8", "PE9", "PE10", "PE11"; 682ff29f13eSJagan Teki function = "csi"; 683ff29f13eSJagan Teki }; 684ff29f13eSJagan Teki 685f7056b28SJagan Teki /omit-if-no-ref/ 686f7056b28SJagan Teki csi_mclk_pin: csi-mclk-pin { 687f7056b28SJagan Teki pins = "PE1"; 688f7056b28SJagan Teki function = "csi"; 689f7056b28SJagan Teki }; 690f7056b28SJagan Teki 69154eac67bSMaxime Ripard i2c0_pins: i2c0-pins { 69211239fe6SHarald Geyer pins = "PH0", "PH1"; 69311239fe6SHarald Geyer function = "i2c0"; 69411239fe6SHarald Geyer }; 69511239fe6SHarald Geyer 69654eac67bSMaxime Ripard i2c1_pins: i2c1-pins { 6976bc37facSAndre Przywara pins = "PH2", "PH3"; 6986bc37facSAndre Przywara function = "i2c1"; 6996bc37facSAndre Przywara }; 7006bc37facSAndre Przywara 70129b2c68bSOndrej Jirman i2c2_pins: i2c2-pins { 70229b2c68bSOndrej Jirman pins = "PE14", "PE15"; 70329b2c68bSOndrej Jirman function = "i2c2"; 70429b2c68bSOndrej Jirman }; 70529b2c68bSOndrej Jirman 706c478a12eSIcenowy Zheng /omit-if-no-ref/ 707c478a12eSIcenowy Zheng lcd_rgb666_pins: lcd-rgb666-pins { 708c478a12eSIcenowy Zheng pins = "PD0", "PD1", "PD2", "PD3", "PD4", 709c478a12eSIcenowy Zheng "PD5", "PD6", "PD7", "PD8", "PD9", 710c478a12eSIcenowy Zheng "PD10", "PD11", "PD12", "PD13", 711c478a12eSIcenowy Zheng "PD14", "PD15", "PD16", "PD17", 712c478a12eSIcenowy Zheng "PD18", "PD19", "PD20", "PD21"; 713c478a12eSIcenowy Zheng function = "lcd0"; 714c478a12eSIcenowy Zheng }; 715c478a12eSIcenowy Zheng 716a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 717a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 718a3e8f492SMaxime Ripard "PF4", "PF5"; 719a3e8f492SMaxime Ripard function = "mmc0"; 720a3e8f492SMaxime Ripard drive-strength = <30>; 721a3e8f492SMaxime Ripard bias-pull-up; 722a3e8f492SMaxime Ripard }; 723a3e8f492SMaxime Ripard 724a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 725a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 726a3e8f492SMaxime Ripard "PG4", "PG5"; 727a3e8f492SMaxime Ripard function = "mmc1"; 728a3e8f492SMaxime Ripard drive-strength = <30>; 729a3e8f492SMaxime Ripard bias-pull-up; 730a3e8f492SMaxime Ripard }; 731a3e8f492SMaxime Ripard 732a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 733fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 734a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 735a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 736a3e8f492SMaxime Ripard function = "mmc2"; 737a3e8f492SMaxime Ripard drive-strength = <30>; 738a3e8f492SMaxime Ripard bias-pull-up; 739a3e8f492SMaxime Ripard }; 740a3e8f492SMaxime Ripard 741fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 742fa59dd2eSChen-Yu Tsai pins = "PC1"; 743fa59dd2eSChen-Yu Tsai function = "mmc2"; 744fa59dd2eSChen-Yu Tsai drive-strength = <30>; 745fa59dd2eSChen-Yu Tsai bias-pull-up; 746fa59dd2eSChen-Yu Tsai }; 747fa59dd2eSChen-Yu Tsai 74854eac67bSMaxime Ripard pwm_pin: pwm-pin { 749b5df280bSAndre Przywara pins = "PD22"; 750b5df280bSAndre Przywara function = "pwm"; 751b5df280bSAndre Przywara }; 752b5df280bSAndre Przywara 75354eac67bSMaxime Ripard rmii_pins: rmii-pins { 754e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 755e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 756e53f67e9SCorentin Labbe function = "emac"; 757e53f67e9SCorentin Labbe drive-strength = <40>; 758e53f67e9SCorentin Labbe }; 759e53f67e9SCorentin Labbe 76054eac67bSMaxime Ripard rgmii_pins: rgmii-pins { 761e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 762e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 763e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 764e53f67e9SCorentin Labbe function = "emac"; 765e53f67e9SCorentin Labbe drive-strength = <40>; 766e53f67e9SCorentin Labbe }; 767e53f67e9SCorentin Labbe 76854eac67bSMaxime Ripard spdif_tx_pin: spdif-tx-pin { 769b399d2acSMarcus Cooper pins = "PH8"; 770b399d2acSMarcus Cooper function = "spdif"; 771b399d2acSMarcus Cooper }; 772b399d2acSMarcus Cooper 77354eac67bSMaxime Ripard spi0_pins: spi0-pins { 774b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 775b518bb15SStefan Brüns function = "spi0"; 776b518bb15SStefan Brüns }; 777b518bb15SStefan Brüns 77854eac67bSMaxime Ripard spi1_pins: spi1-pins { 779b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 780b518bb15SStefan Brüns function = "spi1"; 781b518bb15SStefan Brüns }; 782b518bb15SStefan Brüns 783d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 7846bc37facSAndre Przywara pins = "PB8", "PB9"; 7856bc37facSAndre Przywara function = "uart0"; 7866bc37facSAndre Przywara }; 787e7ba733dSAndre Przywara 78854eac67bSMaxime Ripard uart1_pins: uart1-pins { 789e7ba733dSAndre Przywara pins = "PG6", "PG7"; 790e7ba733dSAndre Przywara function = "uart1"; 791e7ba733dSAndre Przywara }; 792e7ba733dSAndre Przywara 79354eac67bSMaxime Ripard uart1_rts_cts_pins: uart1-rts-cts-pins { 794e7ba733dSAndre Przywara pins = "PG8", "PG9"; 795e7ba733dSAndre Przywara function = "uart1"; 796e7ba733dSAndre Przywara }; 79779825719SAndreas Färber 79879825719SAndreas Färber uart2_pins: uart2-pins { 79979825719SAndreas Färber pins = "PB0", "PB1"; 80079825719SAndreas Färber function = "uart2"; 80179825719SAndreas Färber }; 8022273aa16SAndreas Färber 8032273aa16SAndreas Färber uart3_pins: uart3-pins { 8042273aa16SAndreas Färber pins = "PD0", "PD1"; 8052273aa16SAndreas Färber function = "uart3"; 8062273aa16SAndreas Färber }; 8072273aa16SAndreas Färber 8082273aa16SAndreas Färber uart4_pins: uart4-pins { 8092273aa16SAndreas Färber pins = "PD2", "PD3"; 8102273aa16SAndreas Färber function = "uart4"; 8112273aa16SAndreas Färber }; 8122273aa16SAndreas Färber 8132273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 8142273aa16SAndreas Färber pins = "PD4", "PD5"; 8152273aa16SAndreas Färber function = "uart4"; 8162273aa16SAndreas Färber }; 8176bc37facSAndre Przywara }; 8186bc37facSAndre Przywara 81912bcaacaSSamuel Holland timer@1c20c00 { 82012bcaacaSSamuel Holland compatible = "allwinner,sun50i-a64-timer", 82112bcaacaSSamuel Holland "allwinner,sun8i-a23-timer"; 82212bcaacaSSamuel Holland reg = <0x01c20c00 0xa0>; 82312bcaacaSSamuel Holland interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 82412bcaacaSSamuel Holland <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 82512bcaacaSSamuel Holland clocks = <&osc24M>; 82612bcaacaSSamuel Holland }; 82712bcaacaSSamuel Holland 828af97dd55SSamuel Holland wdt0: watchdog@1c20ca0 { 829af97dd55SSamuel Holland compatible = "allwinner,sun50i-a64-wdt", 830af97dd55SSamuel Holland "allwinner,sun6i-a31-wdt"; 831af97dd55SSamuel Holland reg = <0x01c20ca0 0x20>; 832af97dd55SSamuel Holland interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 833af97dd55SSamuel Holland clocks = <&osc24M>; 834af97dd55SSamuel Holland }; 835af97dd55SSamuel Holland 836b399d2acSMarcus Cooper spdif: spdif@1c21000 { 837b399d2acSMarcus Cooper #sound-dai-cells = <0>; 838b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 839b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 840b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 841b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 842b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 843b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 844b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 845b399d2acSMarcus Cooper dmas = <&dma 2>; 846b399d2acSMarcus Cooper dma-names = "tx"; 847b399d2acSMarcus Cooper pinctrl-names = "default"; 848b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 849b399d2acSMarcus Cooper status = "disabled"; 850b399d2acSMarcus Cooper }; 851b399d2acSMarcus Cooper 85284204fb6SLuca Weiss lradc: lradc@1c21800 { 85384204fb6SLuca Weiss compatible = "allwinner,sun50i-a64-lradc", 85484204fb6SLuca Weiss "allwinner,sun8i-a83t-r-lradc"; 85584204fb6SLuca Weiss reg = <0x01c21800 0x400>; 856189bef23SSamuel Holland interrupt-parent = <&r_intc>; 85784204fb6SLuca Weiss interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 85884204fb6SLuca Weiss status = "disabled"; 85984204fb6SLuca Weiss }; 86084204fb6SLuca Weiss 8611c92c009SMarcus Cooper i2s0: i2s@1c22000 { 8621c92c009SMarcus Cooper #sound-dai-cells = <0>; 8631c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8641c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8651c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 8661c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8671c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 8681c92c009SMarcus Cooper clock-names = "apb", "mod"; 8691c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 8701c92c009SMarcus Cooper dma-names = "rx", "tx"; 8711c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 8721c92c009SMarcus Cooper status = "disabled"; 8731c92c009SMarcus Cooper }; 8741c92c009SMarcus Cooper 8751c92c009SMarcus Cooper i2s1: i2s@1c22400 { 8761c92c009SMarcus Cooper #sound-dai-cells = <0>; 8771c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8781c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8791c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 8801c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8811c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 8821c92c009SMarcus Cooper clock-names = "apb", "mod"; 8831c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 8841c92c009SMarcus Cooper dma-names = "rx", "tx"; 8851c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 8861c92c009SMarcus Cooper status = "disabled"; 8871c92c009SMarcus Cooper }; 8881c92c009SMarcus Cooper 889796c994eSMarcus Cooper i2s2: i2s@1c22800 { 890796c994eSMarcus Cooper #sound-dai-cells = <0>; 891796c994eSMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 892796c994eSMarcus Cooper "allwinner,sun8i-h3-i2s"; 893796c994eSMarcus Cooper reg = <0x01c22800 0x400>; 894796c994eSMarcus Cooper interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 895796c994eSMarcus Cooper clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 896796c994eSMarcus Cooper clock-names = "apb", "mod"; 897796c994eSMarcus Cooper resets = <&ccu RST_BUS_I2S2>; 898796c994eSMarcus Cooper dma-names = "rx", "tx"; 899796c994eSMarcus Cooper dmas = <&dma 27>, <&dma 27>; 900796c994eSMarcus Cooper status = "disabled"; 901796c994eSMarcus Cooper }; 902796c994eSMarcus Cooper 903ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 904ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 905ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 906ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 907ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 908ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 909ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 910ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 911ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 912ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 913ec4a9540SVasily Khoruzhick status = "disabled"; 914ec4a9540SVasily Khoruzhick }; 915ec4a9540SVasily Khoruzhick 916ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 917e0cd8e01SSamuel Holland #sound-dai-cells = <1>; 918db9c6ad2SSamuel Holland compatible = "allwinner,sun50i-a64-codec", 919db9c6ad2SSamuel Holland "allwinner,sun8i-a33-codec"; 920ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 921ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 922ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 923ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 924ec4a9540SVasily Khoruzhick status = "disabled"; 925ec4a9540SVasily Khoruzhick }; 926ec4a9540SVasily Khoruzhick 92759f5e9b9SVasily Khoruzhick ths: thermal-sensor@1c25000 { 92859f5e9b9SVasily Khoruzhick compatible = "allwinner,sun50i-a64-ths"; 92959f5e9b9SVasily Khoruzhick reg = <0x01c25000 0x100>; 93059f5e9b9SVasily Khoruzhick clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 93159f5e9b9SVasily Khoruzhick clock-names = "bus", "mod"; 93259f5e9b9SVasily Khoruzhick interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 93359f5e9b9SVasily Khoruzhick resets = <&ccu RST_BUS_THS>; 93459f5e9b9SVasily Khoruzhick nvmem-cells = <&ths_calibration>; 93559f5e9b9SVasily Khoruzhick nvmem-cell-names = "calibration"; 93659f5e9b9SVasily Khoruzhick #thermal-sensor-cells = <1>; 93759f5e9b9SVasily Khoruzhick }; 93859f5e9b9SVasily Khoruzhick 9396bc37facSAndre Przywara uart0: serial@1c28000 { 9406bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9416bc37facSAndre Przywara reg = <0x01c28000 0x400>; 9426bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 9436bc37facSAndre Przywara reg-shift = <2>; 9446bc37facSAndre Przywara reg-io-width = <4>; 945494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 946494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 9476bc37facSAndre Przywara status = "disabled"; 9486bc37facSAndre Przywara }; 9496bc37facSAndre Przywara 9506bc37facSAndre Przywara uart1: serial@1c28400 { 9516bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9526bc37facSAndre Przywara reg = <0x01c28400 0x400>; 9536bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 9546bc37facSAndre Przywara reg-shift = <2>; 9556bc37facSAndre Przywara reg-io-width = <4>; 956494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 957494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 9586bc37facSAndre Przywara status = "disabled"; 9596bc37facSAndre Przywara }; 9606bc37facSAndre Przywara 9616bc37facSAndre Przywara uart2: serial@1c28800 { 9626bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9636bc37facSAndre Przywara reg = <0x01c28800 0x400>; 9646bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 9656bc37facSAndre Przywara reg-shift = <2>; 9666bc37facSAndre Przywara reg-io-width = <4>; 967494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 968494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 9696bc37facSAndre Przywara status = "disabled"; 9706bc37facSAndre Przywara }; 9716bc37facSAndre Przywara 9726bc37facSAndre Przywara uart3: serial@1c28c00 { 9736bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9746bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 9756bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 9766bc37facSAndre Przywara reg-shift = <2>; 9776bc37facSAndre Przywara reg-io-width = <4>; 978494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 979494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 9806bc37facSAndre Przywara status = "disabled"; 9816bc37facSAndre Przywara }; 9826bc37facSAndre Przywara 9836bc37facSAndre Przywara uart4: serial@1c29000 { 9846bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9856bc37facSAndre Przywara reg = <0x01c29000 0x400>; 9866bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 9876bc37facSAndre Przywara reg-shift = <2>; 9886bc37facSAndre Przywara reg-io-width = <4>; 989494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 990494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 9916bc37facSAndre Przywara status = "disabled"; 9926bc37facSAndre Przywara }; 9936bc37facSAndre Przywara 9946bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 9956bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9966bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 9976bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 998494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 999494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 100070f76289SJagan Teki pinctrl-names = "default"; 100170f76289SJagan Teki pinctrl-0 = <&i2c0_pins>; 10026bc37facSAndre Przywara status = "disabled"; 10036bc37facSAndre Przywara #address-cells = <1>; 10046bc37facSAndre Przywara #size-cells = <0>; 10056bc37facSAndre Przywara }; 10066bc37facSAndre Przywara 10076bc37facSAndre Przywara i2c1: i2c@1c2b000 { 10086bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 10096bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 10106bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1011494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 1012494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 101370f76289SJagan Teki pinctrl-names = "default"; 101470f76289SJagan Teki pinctrl-0 = <&i2c1_pins>; 10156bc37facSAndre Przywara status = "disabled"; 10166bc37facSAndre Przywara #address-cells = <1>; 10176bc37facSAndre Przywara #size-cells = <0>; 10186bc37facSAndre Przywara }; 10196bc37facSAndre Przywara 10206bc37facSAndre Przywara i2c2: i2c@1c2b400 { 10216bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 10226bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 10236bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1024494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 1025494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 102629b2c68bSOndrej Jirman pinctrl-names = "default"; 102729b2c68bSOndrej Jirman pinctrl-0 = <&i2c2_pins>; 10286bc37facSAndre Przywara status = "disabled"; 10296bc37facSAndre Przywara #address-cells = <1>; 10306bc37facSAndre Przywara #size-cells = <0>; 10316bc37facSAndre Przywara }; 10326bc37facSAndre Przywara 1033d6c9da12SCorentin LABBE spi0: spi@1c68000 { 1034b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 1035b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 1036b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1037b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1038b518bb15SStefan Brüns clock-names = "ahb", "mod"; 103906c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 104006c1258aSStefan Brüns dma-names = "rx", "tx"; 1041b518bb15SStefan Brüns pinctrl-names = "default"; 1042b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 1043b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 1044b518bb15SStefan Brüns status = "disabled"; 1045b518bb15SStefan Brüns num-cs = <1>; 1046b518bb15SStefan Brüns #address-cells = <1>; 1047b518bb15SStefan Brüns #size-cells = <0>; 1048b518bb15SStefan Brüns }; 1049b518bb15SStefan Brüns 1050d6c9da12SCorentin LABBE spi1: spi@1c69000 { 1051b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 1052b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 1053b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1054b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1055b518bb15SStefan Brüns clock-names = "ahb", "mod"; 105606c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 105706c1258aSStefan Brüns dma-names = "rx", "tx"; 1058b518bb15SStefan Brüns pinctrl-names = "default"; 1059b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 1060b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 1061b518bb15SStefan Brüns status = "disabled"; 1062b518bb15SStefan Brüns num-cs = <1>; 1063b518bb15SStefan Brüns #address-cells = <1>; 1064b518bb15SStefan Brüns #size-cells = <0>; 1065b518bb15SStefan Brüns }; 1066b518bb15SStefan Brüns 106794f44288SCorentin Labbe emac: ethernet@1c30000 { 106894f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 106994f44288SCorentin Labbe syscon = <&syscon>; 107094f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 107194f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 107294f44288SCorentin Labbe interrupt-names = "macirq"; 107394f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 107494f44288SCorentin Labbe reset-names = "stmmaceth"; 107594f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 107694f44288SCorentin Labbe clock-names = "stmmaceth"; 107794f44288SCorentin Labbe status = "disabled"; 107894f44288SCorentin Labbe 107994f44288SCorentin Labbe mdio: mdio { 108016416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 108194f44288SCorentin Labbe #address-cells = <1>; 108294f44288SCorentin Labbe #size-cells = <0>; 108394f44288SCorentin Labbe }; 108494f44288SCorentin Labbe }; 108594f44288SCorentin Labbe 10866b683d76SJagan Teki mali: gpu@1c40000 { 10876b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 10886b683d76SJagan Teki reg = <0x01c40000 0x10000>; 10896b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 10906b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 10916b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 10926b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 10936b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 10946b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 10956b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 10966b683d76SJagan Teki interrupt-names = "gp", 10976b683d76SJagan Teki "gpmmu", 10986b683d76SJagan Teki "pp0", 10996b683d76SJagan Teki "ppmmu0", 11006b683d76SJagan Teki "pp1", 11016b683d76SJagan Teki "ppmmu1", 11026b683d76SJagan Teki "pmu"; 11036b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 11046b683d76SJagan Teki clock-names = "bus", "core"; 11056b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 11066b683d76SJagan Teki }; 11076b683d76SJagan Teki 11086bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 11096bc37facSAndre Przywara compatible = "arm,gic-400"; 11106bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 11116bc37facSAndre Przywara <0x01c82000 0x2000>, 11126bc37facSAndre Przywara <0x01c84000 0x2000>, 11136bc37facSAndre Przywara <0x01c86000 0x2000>; 11146bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 11156bc37facSAndre Przywara interrupt-controller; 11166bc37facSAndre Przywara #interrupt-cells = <3>; 11176bc37facSAndre Przywara }; 11186bc37facSAndre Przywara 1119b5df280bSAndre Przywara pwm: pwm@1c21400 { 1120b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1121b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1122b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 1123b5df280bSAndre Przywara clocks = <&osc24M>; 1124b5df280bSAndre Przywara pinctrl-names = "default"; 1125b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 1126b5df280bSAndre Przywara #pwm-cells = <3>; 1127b5df280bSAndre Przywara status = "disabled"; 1128b5df280bSAndre Przywara }; 1129b5df280bSAndre Przywara 1130fc7c2bfbSJernej Skrabec mbus: dram-controller@1c62000 { 1131fc7c2bfbSJernej Skrabec compatible = "allwinner,sun50i-a64-mbus"; 1132fc7c2bfbSJernej Skrabec reg = <0x01c62000 0x1000>; 1133fc7c2bfbSJernej Skrabec clocks = <&ccu 112>; 1134cff11101SOndrej Jirman #address-cells = <1>; 1135cff11101SOndrej Jirman #size-cells = <1>; 1136fc7c2bfbSJernej Skrabec dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1137fc7c2bfbSJernej Skrabec #interconnect-cells = <1>; 1138fc7c2bfbSJernej Skrabec }; 1139fc7c2bfbSJernej Skrabec 1140ff29f13eSJagan Teki csi: csi@1cb0000 { 1141ff29f13eSJagan Teki compatible = "allwinner,sun50i-a64-csi"; 1142ff29f13eSJagan Teki reg = <0x01cb0000 0x1000>; 1143ff29f13eSJagan Teki interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1144ff29f13eSJagan Teki clocks = <&ccu CLK_BUS_CSI>, 1145ff29f13eSJagan Teki <&ccu CLK_CSI_SCLK>, 1146ff29f13eSJagan Teki <&ccu CLK_DRAM_CSI>; 1147ff29f13eSJagan Teki clock-names = "bus", "mod", "ram"; 1148ff29f13eSJagan Teki resets = <&ccu RST_BUS_CSI>; 1149ff29f13eSJagan Teki pinctrl-names = "default"; 1150ff29f13eSJagan Teki pinctrl-0 = <&csi_pins>; 1151ff29f13eSJagan Teki status = "disabled"; 1152ff29f13eSJagan Teki }; 1153ff29f13eSJagan Teki 115416c8ff57SJagan Teki dsi: dsi@1ca0000 { 115516c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dsi"; 115616c8ff57SJagan Teki reg = <0x01ca0000 0x1000>; 115716c8ff57SJagan Teki interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 115816c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>; 115916c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 116016c8ff57SJagan Teki phys = <&dphy>; 116116c8ff57SJagan Teki phy-names = "dphy"; 116216c8ff57SJagan Teki status = "disabled"; 116316c8ff57SJagan Teki #address-cells = <1>; 116416c8ff57SJagan Teki #size-cells = <0>; 116516c8ff57SJagan Teki 116616c8ff57SJagan Teki port { 116716c8ff57SJagan Teki dsi_in_tcon0: endpoint { 116816c8ff57SJagan Teki remote-endpoint = <&tcon0_out_dsi>; 116916c8ff57SJagan Teki }; 117016c8ff57SJagan Teki }; 117116c8ff57SJagan Teki }; 117216c8ff57SJagan Teki 117316c8ff57SJagan Teki dphy: d-phy@1ca1000 { 117416c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dphy", 117516c8ff57SJagan Teki "allwinner,sun6i-a31-mipi-dphy"; 117616c8ff57SJagan Teki reg = <0x01ca1000 0x1000>; 117716c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>, 117816c8ff57SJagan Teki <&ccu CLK_DSI_DPHY>; 117916c8ff57SJagan Teki clock-names = "bus", "mod"; 118016c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 118116c8ff57SJagan Teki status = "disabled"; 118216c8ff57SJagan Teki #phy-cells = <0>; 118316c8ff57SJagan Teki }; 118416c8ff57SJagan Teki 1185dd00d78dSJernej Skrabec deinterlace: deinterlace@1e00000 { 1186dd00d78dSJernej Skrabec compatible = "allwinner,sun50i-a64-deinterlace", 1187dd00d78dSJernej Skrabec "allwinner,sun8i-h3-deinterlace"; 1188dd00d78dSJernej Skrabec reg = <0x01e00000 0x20000>; 1189dd00d78dSJernej Skrabec clocks = <&ccu CLK_BUS_DEINTERLACE>, 1190dd00d78dSJernej Skrabec <&ccu CLK_DEINTERLACE>, 1191dd00d78dSJernej Skrabec <&ccu CLK_DRAM_DEINTERLACE>; 1192dd00d78dSJernej Skrabec clock-names = "bus", "mod", "ram"; 1193dd00d78dSJernej Skrabec resets = <&ccu RST_BUS_DEINTERLACE>; 1194dd00d78dSJernej Skrabec interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1195dd00d78dSJernej Skrabec interconnects = <&mbus 9>; 1196dd00d78dSJernej Skrabec interconnect-names = "dma-mem"; 1197dd00d78dSJernej Skrabec }; 1198dd00d78dSJernej Skrabec 1199e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 1200e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 1201e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 1202e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 1203e85f28e0SJagan Teki reg-io-width = <1>; 1204e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1205e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1206e85f28e0SJagan Teki <&ccu CLK_HDMI>; 1207e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 1208e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 1209e85f28e0SJagan Teki reset-names = "ctrl"; 1210e85f28e0SJagan Teki phys = <&hdmi_phy>; 1211d40113fbSMaxime Ripard phy-names = "phy"; 1212e85f28e0SJagan Teki status = "disabled"; 1213e85f28e0SJagan Teki 1214e85f28e0SJagan Teki ports { 1215e85f28e0SJagan Teki #address-cells = <1>; 1216e85f28e0SJagan Teki #size-cells = <0>; 1217e85f28e0SJagan Teki 1218e85f28e0SJagan Teki hdmi_in: port@0 { 1219e85f28e0SJagan Teki reg = <0>; 1220e85f28e0SJagan Teki 1221e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 1222e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 1223e85f28e0SJagan Teki }; 1224e85f28e0SJagan Teki }; 1225e85f28e0SJagan Teki 1226e85f28e0SJagan Teki hdmi_out: port@1 { 1227e85f28e0SJagan Teki reg = <1>; 1228e85f28e0SJagan Teki }; 1229e85f28e0SJagan Teki }; 1230e85f28e0SJagan Teki }; 1231e85f28e0SJagan Teki 1232e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 1233e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 1234e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 1235e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1236b71818cbSChen-Yu Tsai <&ccu CLK_PLL_VIDEO0>; 1237e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 1238e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 1239e85f28e0SJagan Teki reset-names = "phy"; 1240e85f28e0SJagan Teki #phy-cells = <0>; 1241e85f28e0SJagan Teki }; 1242e85f28e0SJagan Teki 12436bc37facSAndre Przywara rtc: rtc@1f00000 { 124444ff3cafSChen-Yu Tsai compatible = "allwinner,sun50i-a64-rtc", 124544ff3cafSChen-Yu Tsai "allwinner,sun8i-h3-rtc"; 124644ff3cafSChen-Yu Tsai reg = <0x01f00000 0x400>; 1247189bef23SSamuel Holland interrupt-parent = <&r_intc>; 12486bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 12496bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 125044ff3cafSChen-Yu Tsai clock-output-names = "osc32k", "osc32k-out", "iosc"; 1251e1a9a474SJagan Teki clocks = <&osc32k>; 1252e1a9a474SJagan Teki #clock-cells = <1>; 12536bc37facSAndre Przywara }; 1254791a9e00SIcenowy Zheng 1255535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 1256535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 1257535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 1258535ca508SIcenowy Zheng interrupt-controller; 125973088dfeSSamuel Holland #interrupt-cells = <3>; 1260535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 1261535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1262535ca508SIcenowy Zheng }; 1263535ca508SIcenowy Zheng 1264791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 1265791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 1266791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 1267b71818cbSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 1268b71818cbSChen-Yu Tsai <&ccu CLK_PLL_PERIPH0>; 1269f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 1270791a9e00SIcenowy Zheng #clock-cells = <1>; 1271791a9e00SIcenowy Zheng #reset-cells = <1>; 1272791a9e00SIcenowy Zheng }; 1273ec427905SIcenowy Zheng 1274ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 1275ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 1276ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 1277ec4a9540SVasily Khoruzhick status = "disabled"; 1278ec4a9540SVasily Khoruzhick }; 1279ec4a9540SVasily Khoruzhick 1280871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 1281871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 1282871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 1283871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 1284871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1285871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1286871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1287871b5352SIcenowy Zheng status = "disabled"; 1288871b5352SIcenowy Zheng #address-cells = <1>; 1289871b5352SIcenowy Zheng #size-cells = <0>; 1290871b5352SIcenowy Zheng }; 1291871b5352SIcenowy Zheng 129244a4f416SIgors Makejevs r_ir: ir@1f02000 { 129344a4f416SIgors Makejevs compatible = "allwinner,sun50i-a64-ir", 129444a4f416SIgors Makejevs "allwinner,sun6i-a31-ir"; 129544a4f416SIgors Makejevs reg = <0x01f02000 0x400>; 129644a4f416SIgors Makejevs clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 129744a4f416SIgors Makejevs clock-names = "apb", "ir"; 129844a4f416SIgors Makejevs resets = <&r_ccu RST_APB0_IR>; 129944a4f416SIgors Makejevs interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 130044a4f416SIgors Makejevs pinctrl-names = "default"; 130144a4f416SIgors Makejevs pinctrl-0 = <&r_ir_rx_pin>; 130244a4f416SIgors Makejevs status = "disabled"; 130344a4f416SIgors Makejevs }; 130444a4f416SIgors Makejevs 1305b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1306b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1307b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1308b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1309b5df280bSAndre Przywara clocks = <&osc24M>; 1310b5df280bSAndre Przywara pinctrl-names = "default"; 1311b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1312b5df280bSAndre Przywara #pwm-cells = <3>; 1313b5df280bSAndre Przywara status = "disabled"; 1314b5df280bSAndre Przywara }; 1315b5df280bSAndre Przywara 1316d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1317ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1318ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1319189bef23SSamuel Holland interrupt-parent = <&r_intc>; 1320ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1321494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1322ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1323ec427905SIcenowy Zheng gpio-controller; 1324ec427905SIcenowy Zheng #gpio-cells = <3>; 1325ec427905SIcenowy Zheng interrupt-controller; 1326ec427905SIcenowy Zheng #interrupt-cells = <3>; 13273b38fdedSIcenowy Zheng 13281b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1329871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1330871b5352SIcenowy Zheng function = "s_i2c"; 1331871b5352SIcenowy Zheng }; 1332871b5352SIcenowy Zheng 133344a4f416SIgors Makejevs r_ir_rx_pin: r-ir-rx-pin { 133444a4f416SIgors Makejevs pins = "PL11"; 133544a4f416SIgors Makejevs function = "s_cir_rx"; 133644a4f416SIgors Makejevs }; 133744a4f416SIgors Makejevs 133854eac67bSMaxime Ripard r_pwm_pin: r-pwm-pin { 1339b5df280bSAndre Przywara pins = "PL10"; 1340b5df280bSAndre Przywara function = "s_pwm"; 1341b5df280bSAndre Przywara }; 1342b5df280bSAndre Przywara 134354eac67bSMaxime Ripard r_rsb_pins: r-rsb-pins { 13443b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 13453b38fdedSIcenowy Zheng function = "s_rsb"; 13463b38fdedSIcenowy Zheng }; 13473b38fdedSIcenowy Zheng }; 13483b38fdedSIcenowy Zheng 13493b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 13503b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 13513b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 13523b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 13533b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 13543b38fdedSIcenowy Zheng clock-frequency = <3000000>; 13553b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 13563b38fdedSIcenowy Zheng pinctrl-names = "default"; 13573b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 13583b38fdedSIcenowy Zheng status = "disabled"; 13593b38fdedSIcenowy Zheng #address-cells = <1>; 13603b38fdedSIcenowy Zheng #size-cells = <0>; 1361ec427905SIcenowy Zheng }; 13626bc37facSAndre Przywara }; 13636bc37facSAndre Przywara}; 1364