1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd. 3cabbaed7SClément Péron// based on the Allwinner H3 dtsi: 4cabbaed7SClément Péron// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara 6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 72c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 8494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 96bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 10a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 112c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 12871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 1359f5e9b9SVasily Khoruzhick#include <dt-bindings/thermal/thermal.h> 146bc37facSAndre Przywara 156bc37facSAndre Przywara/ { 166bc37facSAndre Przywara interrupt-parent = <&gic>; 176bc37facSAndre Przywara #address-cells = <1>; 186bc37facSAndre Przywara #size-cells = <1>; 196bc37facSAndre Przywara 20c1cff65fSHarald Geyer chosen { 21c1cff65fSHarald Geyer #address-cells = <1>; 22c1cff65fSHarald Geyer #size-cells = <1>; 23c1cff65fSHarald Geyer ranges; 24c1cff65fSHarald Geyer 25c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 26c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 27c1cff65fSHarald Geyer "simple-framebuffer"; 28c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 29c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 302c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 31c1cff65fSHarald Geyer status = "disabled"; 32c1cff65fSHarald Geyer }; 33fca63f58SIcenowy Zheng 34fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 35fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 36fca63f58SIcenowy Zheng "simple-framebuffer"; 37fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 38fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 39fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40fca63f58SIcenowy Zheng status = "disabled"; 41fca63f58SIcenowy Zheng }; 42c1cff65fSHarald Geyer }; 43c1cff65fSHarald Geyer 446bc37facSAndre Przywara cpus { 456bc37facSAndre Przywara #address-cells = <1>; 466bc37facSAndre Przywara #size-cells = <0>; 476bc37facSAndre Przywara 486bc37facSAndre Przywara cpu0: cpu@0 { 4931af04cdSRob Herring compatible = "arm,cortex-a53"; 506bc37facSAndre Przywara device_type = "cpu"; 516bc37facSAndre Przywara reg = <0>; 526bc37facSAndre Przywara enable-method = "psci"; 5339defc81SAndre Przywara next-level-cache = <&L2>; 547db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 55f267eff7SVasily Khoruzhick clock-names = "cpu"; 56e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 576bc37facSAndre Przywara }; 586bc37facSAndre Przywara 596bc37facSAndre Przywara cpu1: cpu@1 { 6031af04cdSRob Herring compatible = "arm,cortex-a53"; 616bc37facSAndre Przywara device_type = "cpu"; 626bc37facSAndre Przywara reg = <1>; 636bc37facSAndre Przywara enable-method = "psci"; 6439defc81SAndre Przywara next-level-cache = <&L2>; 657db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 66f267eff7SVasily Khoruzhick clock-names = "cpu"; 67e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 686bc37facSAndre Przywara }; 696bc37facSAndre Przywara 706bc37facSAndre Przywara cpu2: cpu@2 { 7131af04cdSRob Herring compatible = "arm,cortex-a53"; 726bc37facSAndre Przywara device_type = "cpu"; 736bc37facSAndre Przywara reg = <2>; 746bc37facSAndre Przywara enable-method = "psci"; 7539defc81SAndre Przywara next-level-cache = <&L2>; 767db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 77f267eff7SVasily Khoruzhick clock-names = "cpu"; 78e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 796bc37facSAndre Przywara }; 806bc37facSAndre Przywara 816bc37facSAndre Przywara cpu3: cpu@3 { 8231af04cdSRob Herring compatible = "arm,cortex-a53"; 836bc37facSAndre Przywara device_type = "cpu"; 846bc37facSAndre Przywara reg = <3>; 856bc37facSAndre Przywara enable-method = "psci"; 8639defc81SAndre Przywara next-level-cache = <&L2>; 877db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 88f267eff7SVasily Khoruzhick clock-names = "cpu"; 89e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 9039defc81SAndre Przywara }; 9139defc81SAndre Przywara 9239defc81SAndre Przywara L2: l2-cache { 9339defc81SAndre Przywara compatible = "cache"; 9439defc81SAndre Przywara cache-level = <2>; 956bc37facSAndre Przywara }; 966bc37facSAndre Przywara }; 976bc37facSAndre Przywara 98e85f28e0SJagan Teki de: display-engine { 99e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 100e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 101e85f28e0SJagan Teki <&mixer1>; 102e85f28e0SJagan Teki status = "disabled"; 103e85f28e0SJagan Teki }; 104e85f28e0SJagan Teki 1056bc37facSAndre Przywara osc24M: osc24M_clk { 1066bc37facSAndre Przywara #clock-cells = <0>; 1076bc37facSAndre Przywara compatible = "fixed-clock"; 1086bc37facSAndre Przywara clock-frequency = <24000000>; 1096bc37facSAndre Przywara clock-output-names = "osc24M"; 1106bc37facSAndre Przywara }; 1116bc37facSAndre Przywara 1126bc37facSAndre Przywara osc32k: osc32k_clk { 1136bc37facSAndre Przywara #clock-cells = <0>; 1146bc37facSAndre Przywara compatible = "fixed-clock"; 1156bc37facSAndre Przywara clock-frequency = <32768>; 11644ff3cafSChen-Yu Tsai clock-output-names = "ext-osc32k"; 117791a9e00SIcenowy Zheng }; 118791a9e00SIcenowy Zheng 11934a97fccSHarald Geyer pmu { 12034a97fccSHarald Geyer compatible = "arm,cortex-a53-pmu"; 1216b832a14SAndre Przywara interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1226b832a14SAndre Przywara <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1236b832a14SAndre Przywara <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1246b832a14SAndre Przywara <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 12534a97fccSHarald Geyer interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 12634a97fccSHarald Geyer }; 12734a97fccSHarald Geyer 1286bc37facSAndre Przywara psci { 1296bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1306bc37facSAndre Przywara method = "smc"; 1316bc37facSAndre Przywara }; 1326bc37facSAndre Przywara 133ec4a9540SVasily Khoruzhick sound: sound { 134ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 135ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 136ec4a9540SVasily Khoruzhick simple-audio-card,format = "i2s"; 137ec4a9540SVasily Khoruzhick simple-audio-card,frame-master = <&cpudai>; 138ec4a9540SVasily Khoruzhick simple-audio-card,bitclock-master = <&cpudai>; 139ec4a9540SVasily Khoruzhick simple-audio-card,mclk-fs = <128>; 140ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 141ec4a9540SVasily Khoruzhick simple-audio-card,routing = 142631e6a35SSamuel Holland "Left DAC", "DACL", 143631e6a35SSamuel Holland "Right DAC", "DACR", 144631e6a35SSamuel Holland "ADCL", "Left ADC", 145631e6a35SSamuel Holland "ADCR", "Right ADC"; 146ec4a9540SVasily Khoruzhick status = "disabled"; 147ec4a9540SVasily Khoruzhick 148ec4a9540SVasily Khoruzhick cpudai: simple-audio-card,cpu { 149ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 150ec4a9540SVasily Khoruzhick }; 151ec4a9540SVasily Khoruzhick 152ec4a9540SVasily Khoruzhick link_codec: simple-audio-card,codec { 153ec4a9540SVasily Khoruzhick sound-dai = <&codec>; 154ec4a9540SVasily Khoruzhick }; 155ec4a9540SVasily Khoruzhick }; 156ec4a9540SVasily Khoruzhick 1576bc37facSAndre Przywara timer { 1586bc37facSAndre Przywara compatible = "arm,armv8-timer"; 15955ec26d6SSamuel Holland allwinner,erratum-unknown1; 160a371b1bdSSamuel Holland arm,no-tick-in-suspend; 1616bc37facSAndre Przywara interrupts = <GIC_PPI 13 1626bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1636bc37facSAndre Przywara <GIC_PPI 14 1646bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1656bc37facSAndre Przywara <GIC_PPI 11 1666bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1676bc37facSAndre Przywara <GIC_PPI 10 1686bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1696bc37facSAndre Przywara }; 1706bc37facSAndre Przywara 17159f5e9b9SVasily Khoruzhick thermal-zones { 17259f5e9b9SVasily Khoruzhick cpu_thermal: cpu0-thermal { 17359f5e9b9SVasily Khoruzhick /* milliseconds */ 17459f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 17559f5e9b9SVasily Khoruzhick polling-delay = <0>; 17659f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 0>; 177e1c3804aSVasily Khoruzhick 178e1c3804aSVasily Khoruzhick cooling-maps { 179e1c3804aSVasily Khoruzhick map0 { 180e1c3804aSVasily Khoruzhick trip = <&cpu_alert0>; 181e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 182e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 183e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 184e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 185e1c3804aSVasily Khoruzhick }; 186e1c3804aSVasily Khoruzhick map1 { 187e1c3804aSVasily Khoruzhick trip = <&cpu_alert1>; 188e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 189e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 190e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 191e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 192e1c3804aSVasily Khoruzhick }; 193e1c3804aSVasily Khoruzhick }; 194e1c3804aSVasily Khoruzhick 195e1c3804aSVasily Khoruzhick trips { 196e1c3804aSVasily Khoruzhick cpu_alert0: cpu_alert0 { 197e1c3804aSVasily Khoruzhick /* milliCelsius */ 198e1c3804aSVasily Khoruzhick temperature = <75000>; 199e1c3804aSVasily Khoruzhick hysteresis = <2000>; 200e1c3804aSVasily Khoruzhick type = "passive"; 201e1c3804aSVasily Khoruzhick }; 202e1c3804aSVasily Khoruzhick 203e1c3804aSVasily Khoruzhick cpu_alert1: cpu_alert1 { 204e1c3804aSVasily Khoruzhick /* milliCelsius */ 205e1c3804aSVasily Khoruzhick temperature = <90000>; 206e1c3804aSVasily Khoruzhick hysteresis = <2000>; 207e1c3804aSVasily Khoruzhick type = "hot"; 208e1c3804aSVasily Khoruzhick }; 209e1c3804aSVasily Khoruzhick 210e1c3804aSVasily Khoruzhick cpu_crit: cpu_crit { 211e1c3804aSVasily Khoruzhick /* milliCelsius */ 212e1c3804aSVasily Khoruzhick temperature = <110000>; 213e1c3804aSVasily Khoruzhick hysteresis = <2000>; 214e1c3804aSVasily Khoruzhick type = "critical"; 215e1c3804aSVasily Khoruzhick }; 216e1c3804aSVasily Khoruzhick }; 21759f5e9b9SVasily Khoruzhick }; 21859f5e9b9SVasily Khoruzhick 21959f5e9b9SVasily Khoruzhick gpu0_thermal: gpu0-thermal { 22059f5e9b9SVasily Khoruzhick /* milliseconds */ 22159f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 22259f5e9b9SVasily Khoruzhick polling-delay = <0>; 22359f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 1>; 22459f5e9b9SVasily Khoruzhick }; 22559f5e9b9SVasily Khoruzhick 22659f5e9b9SVasily Khoruzhick gpu1_thermal: gpu1-thermal { 22759f5e9b9SVasily Khoruzhick /* milliseconds */ 22859f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 22959f5e9b9SVasily Khoruzhick polling-delay = <0>; 23059f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 2>; 23159f5e9b9SVasily Khoruzhick }; 23259f5e9b9SVasily Khoruzhick }; 23359f5e9b9SVasily Khoruzhick 2346bc37facSAndre Przywara soc { 2356bc37facSAndre Przywara compatible = "simple-bus"; 2366bc37facSAndre Przywara #address-cells = <1>; 2376bc37facSAndre Przywara #size-cells = <1>; 2386bc37facSAndre Przywara ranges; 2396bc37facSAndre Przywara 240275b6317SMaxime Ripard bus@1000000 { 2412c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 2422c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 2432c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 2442c796fc8SIcenowy Zheng #address-cells = <1>; 2452c796fc8SIcenowy Zheng #size-cells = <1>; 2462c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 2472c796fc8SIcenowy Zheng 2482c796fc8SIcenowy Zheng display_clocks: clock@0 { 2492c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 2503e9a1a8bSJernej Skrabec reg = <0x0 0x10000>; 2515ea40f71SMaxime Ripard clocks = <&ccu CLK_BUS_DE>, 2525ea40f71SMaxime Ripard <&ccu CLK_DE>; 2535ea40f71SMaxime Ripard clock-names = "bus", 2545ea40f71SMaxime Ripard "mod"; 2552c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 2562c796fc8SIcenowy Zheng #clock-cells = <1>; 2572c796fc8SIcenowy Zheng #reset-cells = <1>; 2582c796fc8SIcenowy Zheng }; 259e85f28e0SJagan Teki 260048cdfceSJernej Skrabec rotate: rotate@20000 { 261048cdfceSJernej Skrabec compatible = "allwinner,sun50i-a64-de2-rotate", 262048cdfceSJernej Skrabec "allwinner,sun8i-a83t-de2-rotate"; 263048cdfceSJernej Skrabec reg = <0x20000 0x10000>; 264048cdfceSJernej Skrabec interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 265048cdfceSJernej Skrabec clocks = <&display_clocks CLK_BUS_ROT>, 266048cdfceSJernej Skrabec <&display_clocks CLK_ROT>; 267048cdfceSJernej Skrabec clock-names = "bus", 268048cdfceSJernej Skrabec "mod"; 269048cdfceSJernej Skrabec resets = <&display_clocks RST_ROT>; 270048cdfceSJernej Skrabec }; 271048cdfceSJernej Skrabec 272e85f28e0SJagan Teki mixer0: mixer@100000 { 273e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 274e85f28e0SJagan Teki reg = <0x100000 0x100000>; 275e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 276e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 277e85f28e0SJagan Teki clock-names = "bus", 278e85f28e0SJagan Teki "mod"; 279e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 280e85f28e0SJagan Teki 281e85f28e0SJagan Teki ports { 282e85f28e0SJagan Teki #address-cells = <1>; 283e85f28e0SJagan Teki #size-cells = <0>; 284e85f28e0SJagan Teki 285e85f28e0SJagan Teki mixer0_out: port@1 { 286a7f7047fSMaxime Ripard #address-cells = <1>; 287a7f7047fSMaxime Ripard #size-cells = <0>; 288e85f28e0SJagan Teki reg = <1>; 289e85f28e0SJagan Teki 290a7f7047fSMaxime Ripard mixer0_out_tcon0: endpoint@0 { 291a7f7047fSMaxime Ripard reg = <0>; 292e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 293e85f28e0SJagan Teki }; 294a7f7047fSMaxime Ripard 295a7f7047fSMaxime Ripard mixer0_out_tcon1: endpoint@1 { 296a7f7047fSMaxime Ripard reg = <1>; 297a7f7047fSMaxime Ripard remote-endpoint = <&tcon1_in_mixer0>; 298a7f7047fSMaxime Ripard }; 299e85f28e0SJagan Teki }; 300e85f28e0SJagan Teki }; 301e85f28e0SJagan Teki }; 302e85f28e0SJagan Teki 303e85f28e0SJagan Teki mixer1: mixer@200000 { 304e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 305e85f28e0SJagan Teki reg = <0x200000 0x100000>; 306e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 307e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 308e85f28e0SJagan Teki clock-names = "bus", 309e85f28e0SJagan Teki "mod"; 310e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 311e85f28e0SJagan Teki 312e85f28e0SJagan Teki ports { 313e85f28e0SJagan Teki #address-cells = <1>; 314e85f28e0SJagan Teki #size-cells = <0>; 315e85f28e0SJagan Teki 316e85f28e0SJagan Teki mixer1_out: port@1 { 317d41a43a0SMaxime Ripard #address-cells = <1>; 318d41a43a0SMaxime Ripard #size-cells = <0>; 319e85f28e0SJagan Teki reg = <1>; 320e85f28e0SJagan Teki 321a7f7047fSMaxime Ripard mixer1_out_tcon0: endpoint@0 { 322a7f7047fSMaxime Ripard reg = <0>; 323a7f7047fSMaxime Ripard remote-endpoint = <&tcon0_in_mixer1>; 324a7f7047fSMaxime Ripard }; 325a7f7047fSMaxime Ripard 326a7f7047fSMaxime Ripard mixer1_out_tcon1: endpoint@1 { 327a7f7047fSMaxime Ripard reg = <1>; 328e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 329e85f28e0SJagan Teki }; 330e85f28e0SJagan Teki }; 331e85f28e0SJagan Teki }; 332e85f28e0SJagan Teki }; 3332c796fc8SIcenowy Zheng }; 3342c796fc8SIcenowy Zheng 33579b95360SCorentin Labbe syscon: syscon@1c00000 { 3361f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 33779b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 3381f1f5183SIcenowy Zheng #address-cells = <1>; 3391f1f5183SIcenowy Zheng #size-cells = <1>; 3401f1f5183SIcenowy Zheng ranges; 3411f1f5183SIcenowy Zheng 3421f1f5183SIcenowy Zheng sram_c: sram@18000 { 3431f1f5183SIcenowy Zheng compatible = "mmio-sram"; 3441f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 3451f1f5183SIcenowy Zheng #address-cells = <1>; 3461f1f5183SIcenowy Zheng #size-cells = <1>; 3471f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 3481f1f5183SIcenowy Zheng 3491f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 3501f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 3511f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 3521f1f5183SIcenowy Zheng }; 3531f1f5183SIcenowy Zheng }; 354106deea8SPaul Kocialkowski 355106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 356106deea8SPaul Kocialkowski compatible = "mmio-sram"; 357106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 358106deea8SPaul Kocialkowski #address-cells = <1>; 359106deea8SPaul Kocialkowski #size-cells = <1>; 360106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 361106deea8SPaul Kocialkowski 362106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 363106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 364106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 365106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 366106deea8SPaul Kocialkowski }; 367106deea8SPaul Kocialkowski }; 36879b95360SCorentin Labbe }; 36979b95360SCorentin Labbe 370c32637e0SStefan Brüns dma: dma-controller@1c02000 { 371c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 372c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 373c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 374c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 375c32637e0SStefan Brüns dma-channels = <8>; 376c32637e0SStefan Brüns dma-requests = <27>; 377c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 378c32637e0SStefan Brüns #dma-cells = <1>; 379c32637e0SStefan Brüns }; 380c32637e0SStefan Brüns 381e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 382e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 383e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 384e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 385e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 386e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 387e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 388e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 38926c609d5SMaxime Ripard #clock-cells = <0>; 390e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 391e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 392e85f28e0SJagan Teki 393e85f28e0SJagan Teki ports { 394e85f28e0SJagan Teki #address-cells = <1>; 395e85f28e0SJagan Teki #size-cells = <0>; 396e85f28e0SJagan Teki 397e85f28e0SJagan Teki tcon0_in: port@0 { 398e85f28e0SJagan Teki #address-cells = <1>; 399e85f28e0SJagan Teki #size-cells = <0>; 400e85f28e0SJagan Teki reg = <0>; 401e85f28e0SJagan Teki 402e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 403e85f28e0SJagan Teki reg = <0>; 404e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 405e85f28e0SJagan Teki }; 406a7f7047fSMaxime Ripard 407a7f7047fSMaxime Ripard tcon0_in_mixer1: endpoint@1 { 408a7f7047fSMaxime Ripard reg = <1>; 409d41a43a0SMaxime Ripard remote-endpoint = <&mixer1_out_tcon0>; 410a7f7047fSMaxime Ripard }; 411e85f28e0SJagan Teki }; 412e85f28e0SJagan Teki 413e85f28e0SJagan Teki tcon0_out: port@1 { 414e85f28e0SJagan Teki #address-cells = <1>; 415e85f28e0SJagan Teki #size-cells = <0>; 416e85f28e0SJagan Teki reg = <1>; 41716c8ff57SJagan Teki 41816c8ff57SJagan Teki tcon0_out_dsi: endpoint@1 { 41916c8ff57SJagan Teki reg = <1>; 42016c8ff57SJagan Teki remote-endpoint = <&dsi_in_tcon0>; 42116c8ff57SJagan Teki allwinner,tcon-channel = <1>; 42216c8ff57SJagan Teki }; 423e85f28e0SJagan Teki }; 424e85f28e0SJagan Teki }; 425e85f28e0SJagan Teki }; 426e85f28e0SJagan Teki 427e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 428e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 429e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 430e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 431e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 432e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 433e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 434e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 435e85f28e0SJagan Teki reset-names = "lcd"; 436e85f28e0SJagan Teki 437e85f28e0SJagan Teki ports { 438e85f28e0SJagan Teki #address-cells = <1>; 439e85f28e0SJagan Teki #size-cells = <0>; 440e85f28e0SJagan Teki 441e85f28e0SJagan Teki tcon1_in: port@0 { 442a7f7047fSMaxime Ripard #address-cells = <1>; 443a7f7047fSMaxime Ripard #size-cells = <0>; 444e85f28e0SJagan Teki reg = <0>; 445e85f28e0SJagan Teki 446a7f7047fSMaxime Ripard tcon1_in_mixer0: endpoint@0 { 447a7f7047fSMaxime Ripard reg = <0>; 448a7f7047fSMaxime Ripard remote-endpoint = <&mixer0_out_tcon1>; 449a7f7047fSMaxime Ripard }; 450a7f7047fSMaxime Ripard 451a7f7047fSMaxime Ripard tcon1_in_mixer1: endpoint@1 { 452a7f7047fSMaxime Ripard reg = <1>; 453e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 454e85f28e0SJagan Teki }; 455e85f28e0SJagan Teki }; 456e85f28e0SJagan Teki 457e85f28e0SJagan Teki tcon1_out: port@1 { 458e85f28e0SJagan Teki #address-cells = <1>; 459e85f28e0SJagan Teki #size-cells = <0>; 460e85f28e0SJagan Teki reg = <1>; 461e85f28e0SJagan Teki 462e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 463e85f28e0SJagan Teki reg = <1>; 464e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 465e85f28e0SJagan Teki }; 466e85f28e0SJagan Teki }; 467e85f28e0SJagan Teki }; 468e85f28e0SJagan Teki }; 469e85f28e0SJagan Teki 470d60ce247SPaul Kocialkowski video-codec@1c0e000 { 4714ab88516SPaul Kocialkowski compatible = "allwinner,sun50i-a64-video-engine"; 472d60ce247SPaul Kocialkowski reg = <0x01c0e000 0x1000>; 473d60ce247SPaul Kocialkowski clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 474d60ce247SPaul Kocialkowski <&ccu CLK_DRAM_VE>; 475d60ce247SPaul Kocialkowski clock-names = "ahb", "mod", "ram"; 476d60ce247SPaul Kocialkowski resets = <&ccu RST_BUS_VE>; 477d60ce247SPaul Kocialkowski interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 478d60ce247SPaul Kocialkowski allwinner,sram = <&ve_sram 1>; 479d60ce247SPaul Kocialkowski }; 480d60ce247SPaul Kocialkowski 481f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 482f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 483f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 484f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 485f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 486f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 487f3dff347SAndre Przywara reset-names = "ahb"; 488f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 48922be992fSMaxime Ripard max-frequency = <150000000>; 490f3dff347SAndre Przywara status = "disabled"; 491f3dff347SAndre Przywara #address-cells = <1>; 492f3dff347SAndre Przywara #size-cells = <0>; 493f3dff347SAndre Przywara }; 494f3dff347SAndre Przywara 495f3dff347SAndre Przywara mmc1: mmc@1c10000 { 496f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 497f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 498f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 499f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 500f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 501f3dff347SAndre Przywara reset-names = "ahb"; 502f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 50322be992fSMaxime Ripard max-frequency = <150000000>; 504f3dff347SAndre Przywara status = "disabled"; 505f3dff347SAndre Przywara #address-cells = <1>; 506f3dff347SAndre Przywara #size-cells = <0>; 507f3dff347SAndre Przywara }; 508f3dff347SAndre Przywara 509f3dff347SAndre Przywara mmc2: mmc@1c11000 { 510f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 511f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 512f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 513f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 514f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 515f3dff347SAndre Przywara reset-names = "ahb"; 516f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 517*948c657cSAndre Przywara max-frequency = <150000000>; 518f3dff347SAndre Przywara status = "disabled"; 519f3dff347SAndre Przywara #address-cells = <1>; 520f3dff347SAndre Przywara #size-cells = <0>; 521f3dff347SAndre Przywara }; 522f3dff347SAndre Przywara 523ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 524ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 525ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 52659f5e9b9SVasily Khoruzhick #address-cells = <1>; 52759f5e9b9SVasily Khoruzhick #size-cells = <1>; 52859f5e9b9SVasily Khoruzhick 52959f5e9b9SVasily Khoruzhick ths_calibration: thermal-sensor-calibration@34 { 53059f5e9b9SVasily Khoruzhick reg = <0x34 0x8>; 53159f5e9b9SVasily Khoruzhick }; 532ac947b17SEmmanuel Vadot }; 533ac947b17SEmmanuel Vadot 5340f5fc158SCorentin Labbe crypto: crypto@1c15000 { 5350f5fc158SCorentin Labbe compatible = "allwinner,sun50i-a64-crypto"; 5360f5fc158SCorentin Labbe reg = <0x01c15000 0x1000>; 5370f5fc158SCorentin Labbe interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 5380f5fc158SCorentin Labbe clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 5390f5fc158SCorentin Labbe clock-names = "bus", "mod"; 5400f5fc158SCorentin Labbe resets = <&ccu RST_BUS_CE>; 5410f5fc158SCorentin Labbe }; 5420f5fc158SCorentin Labbe 5433e3f39a7SSamuel Holland msgbox: mailbox@1c17000 { 5443e3f39a7SSamuel Holland compatible = "allwinner,sun50i-a64-msgbox", 5453e3f39a7SSamuel Holland "allwinner,sun6i-a31-msgbox"; 5463e3f39a7SSamuel Holland reg = <0x01c17000 0x1000>; 5473e3f39a7SSamuel Holland clocks = <&ccu CLK_BUS_MSGBOX>; 5483e3f39a7SSamuel Holland resets = <&ccu RST_BUS_MSGBOX>; 5493e3f39a7SSamuel Holland interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 5503e3f39a7SSamuel Holland #mbox-cells = <1>; 5513e3f39a7SSamuel Holland }; 5523e3f39a7SSamuel Holland 553d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 554972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 555972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 556972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 557972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 558972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 559972a3ecdSIcenowy Zheng interrupt-names = "mc"; 560972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 561972a3ecdSIcenowy Zheng phy-names = "usb"; 562972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 5630973c06bSMaxime Ripard dr_mode = "otg"; 564972a3ecdSIcenowy Zheng status = "disabled"; 565972a3ecdSIcenowy Zheng }; 566972a3ecdSIcenowy Zheng 567d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 568a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 569a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 5700d984797SIcenowy Zheng <0x01c1a800 0x4>, 571a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 572a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 5730d984797SIcenowy Zheng "pmu0", 574a004ee35SIcenowy Zheng "pmu1"; 575a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 576a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 577a004ee35SIcenowy Zheng clock-names = "usb0_phy", 578a004ee35SIcenowy Zheng "usb1_phy"; 579a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 580a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 581a004ee35SIcenowy Zheng reset-names = "usb0_reset", 582a004ee35SIcenowy Zheng "usb1_reset"; 583a004ee35SIcenowy Zheng status = "disabled"; 584a004ee35SIcenowy Zheng #phy-cells = <1>; 585a004ee35SIcenowy Zheng }; 586a004ee35SIcenowy Zheng 587d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 588dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 589dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 590dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 591dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 592dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 593dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 594dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 595dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 596cc725707SAndre Przywara phys = <&usbphy 0>; 597cc725707SAndre Przywara phy-names = "usb"; 598dc03a047SIcenowy Zheng status = "disabled"; 599dc03a047SIcenowy Zheng }; 600dc03a047SIcenowy Zheng 601d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 602dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 603dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 604dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 605dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 606dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 607dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 608cc725707SAndre Przywara phys = <&usbphy 0>; 609cc725707SAndre Przywara phy-names = "usb"; 610dc03a047SIcenowy Zheng status = "disabled"; 611dc03a047SIcenowy Zheng }; 612dc03a047SIcenowy Zheng 613d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 614a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 615a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 616a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 617a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 618a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 619a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 620a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 621a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 622a004ee35SIcenowy Zheng phys = <&usbphy 1>; 623e6064cf4SMaxime Ripard phy-names = "usb"; 624a004ee35SIcenowy Zheng status = "disabled"; 625a004ee35SIcenowy Zheng }; 626a004ee35SIcenowy Zheng 627d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 628a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 629a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 630a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 631a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 632a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 633a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 634a004ee35SIcenowy Zheng phys = <&usbphy 1>; 635e6064cf4SMaxime Ripard phy-names = "usb"; 636a004ee35SIcenowy Zheng status = "disabled"; 637a004ee35SIcenowy Zheng }; 638a004ee35SIcenowy Zheng 639d6c9da12SCorentin LABBE ccu: clock@1c20000 { 6406bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 6416bc37facSAndre Przywara reg = <0x01c20000 0x400>; 64244ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>; 6436bc37facSAndre Przywara clock-names = "hosc", "losc"; 6446bc37facSAndre Przywara #clock-cells = <1>; 6456bc37facSAndre Przywara #reset-cells = <1>; 6466bc37facSAndre Przywara }; 6476bc37facSAndre Przywara 6486bc37facSAndre Przywara pio: pinctrl@1c20800 { 6496bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 6506bc37facSAndre Przywara reg = <0x01c20800 0x400>; 6516bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 6526bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 6536bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 654b71818cbSChen-Yu Tsai clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 655562bf196SMaxime Ripard clock-names = "apb", "hosc", "losc"; 6566bc37facSAndre Przywara gpio-controller; 6576bc37facSAndre Przywara #gpio-cells = <3>; 6586bc37facSAndre Przywara interrupt-controller; 6596bc37facSAndre Przywara #interrupt-cells = <3>; 6606bc37facSAndre Przywara 661ff29f13eSJagan Teki csi_pins: csi-pins { 662ff29f13eSJagan Teki pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 663ff29f13eSJagan Teki "PE7", "PE8", "PE9", "PE10", "PE11"; 664ff29f13eSJagan Teki function = "csi"; 665ff29f13eSJagan Teki }; 666ff29f13eSJagan Teki 667f7056b28SJagan Teki /omit-if-no-ref/ 668f7056b28SJagan Teki csi_mclk_pin: csi-mclk-pin { 669f7056b28SJagan Teki pins = "PE1"; 670f7056b28SJagan Teki function = "csi"; 671f7056b28SJagan Teki }; 672f7056b28SJagan Teki 67354eac67bSMaxime Ripard i2c0_pins: i2c0-pins { 67411239fe6SHarald Geyer pins = "PH0", "PH1"; 67511239fe6SHarald Geyer function = "i2c0"; 67611239fe6SHarald Geyer }; 67711239fe6SHarald Geyer 67854eac67bSMaxime Ripard i2c1_pins: i2c1-pins { 6796bc37facSAndre Przywara pins = "PH2", "PH3"; 6806bc37facSAndre Przywara function = "i2c1"; 6816bc37facSAndre Przywara }; 6826bc37facSAndre Przywara 68329b2c68bSOndrej Jirman i2c2_pins: i2c2-pins { 68429b2c68bSOndrej Jirman pins = "PE14", "PE15"; 68529b2c68bSOndrej Jirman function = "i2c2"; 68629b2c68bSOndrej Jirman }; 68729b2c68bSOndrej Jirman 688c478a12eSIcenowy Zheng /omit-if-no-ref/ 689c478a12eSIcenowy Zheng lcd_rgb666_pins: lcd-rgb666-pins { 690c478a12eSIcenowy Zheng pins = "PD0", "PD1", "PD2", "PD3", "PD4", 691c478a12eSIcenowy Zheng "PD5", "PD6", "PD7", "PD8", "PD9", 692c478a12eSIcenowy Zheng "PD10", "PD11", "PD12", "PD13", 693c478a12eSIcenowy Zheng "PD14", "PD15", "PD16", "PD17", 694c478a12eSIcenowy Zheng "PD18", "PD19", "PD20", "PD21"; 695c478a12eSIcenowy Zheng function = "lcd0"; 696c478a12eSIcenowy Zheng }; 697c478a12eSIcenowy Zheng 698a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 699a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 700a3e8f492SMaxime Ripard "PF4", "PF5"; 701a3e8f492SMaxime Ripard function = "mmc0"; 702a3e8f492SMaxime Ripard drive-strength = <30>; 703a3e8f492SMaxime Ripard bias-pull-up; 704a3e8f492SMaxime Ripard }; 705a3e8f492SMaxime Ripard 706a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 707a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 708a3e8f492SMaxime Ripard "PG4", "PG5"; 709a3e8f492SMaxime Ripard function = "mmc1"; 710a3e8f492SMaxime Ripard drive-strength = <30>; 711a3e8f492SMaxime Ripard bias-pull-up; 712a3e8f492SMaxime Ripard }; 713a3e8f492SMaxime Ripard 714a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 715fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 716a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 717a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 718a3e8f492SMaxime Ripard function = "mmc2"; 719a3e8f492SMaxime Ripard drive-strength = <30>; 720a3e8f492SMaxime Ripard bias-pull-up; 721a3e8f492SMaxime Ripard }; 722a3e8f492SMaxime Ripard 723fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 724fa59dd2eSChen-Yu Tsai pins = "PC1"; 725fa59dd2eSChen-Yu Tsai function = "mmc2"; 726fa59dd2eSChen-Yu Tsai drive-strength = <30>; 727fa59dd2eSChen-Yu Tsai bias-pull-up; 728fa59dd2eSChen-Yu Tsai }; 729fa59dd2eSChen-Yu Tsai 73054eac67bSMaxime Ripard pwm_pin: pwm-pin { 731b5df280bSAndre Przywara pins = "PD22"; 732b5df280bSAndre Przywara function = "pwm"; 733b5df280bSAndre Przywara }; 734b5df280bSAndre Przywara 73554eac67bSMaxime Ripard rmii_pins: rmii-pins { 736e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 737e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 738e53f67e9SCorentin Labbe function = "emac"; 739e53f67e9SCorentin Labbe drive-strength = <40>; 740e53f67e9SCorentin Labbe }; 741e53f67e9SCorentin Labbe 74254eac67bSMaxime Ripard rgmii_pins: rgmii-pins { 743e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 744e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 745e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 746e53f67e9SCorentin Labbe function = "emac"; 747e53f67e9SCorentin Labbe drive-strength = <40>; 748e53f67e9SCorentin Labbe }; 749e53f67e9SCorentin Labbe 75054eac67bSMaxime Ripard spdif_tx_pin: spdif-tx-pin { 751b399d2acSMarcus Cooper pins = "PH8"; 752b399d2acSMarcus Cooper function = "spdif"; 753b399d2acSMarcus Cooper }; 754b399d2acSMarcus Cooper 75554eac67bSMaxime Ripard spi0_pins: spi0-pins { 756b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 757b518bb15SStefan Brüns function = "spi0"; 758b518bb15SStefan Brüns }; 759b518bb15SStefan Brüns 76054eac67bSMaxime Ripard spi1_pins: spi1-pins { 761b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 762b518bb15SStefan Brüns function = "spi1"; 763b518bb15SStefan Brüns }; 764b518bb15SStefan Brüns 765d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 7666bc37facSAndre Przywara pins = "PB8", "PB9"; 7676bc37facSAndre Przywara function = "uart0"; 7686bc37facSAndre Przywara }; 769e7ba733dSAndre Przywara 77054eac67bSMaxime Ripard uart1_pins: uart1-pins { 771e7ba733dSAndre Przywara pins = "PG6", "PG7"; 772e7ba733dSAndre Przywara function = "uart1"; 773e7ba733dSAndre Przywara }; 774e7ba733dSAndre Przywara 77554eac67bSMaxime Ripard uart1_rts_cts_pins: uart1-rts-cts-pins { 776e7ba733dSAndre Przywara pins = "PG8", "PG9"; 777e7ba733dSAndre Przywara function = "uart1"; 778e7ba733dSAndre Przywara }; 77979825719SAndreas Färber 78079825719SAndreas Färber uart2_pins: uart2-pins { 78179825719SAndreas Färber pins = "PB0", "PB1"; 78279825719SAndreas Färber function = "uart2"; 78379825719SAndreas Färber }; 7842273aa16SAndreas Färber 7852273aa16SAndreas Färber uart3_pins: uart3-pins { 7862273aa16SAndreas Färber pins = "PD0", "PD1"; 7872273aa16SAndreas Färber function = "uart3"; 7882273aa16SAndreas Färber }; 7892273aa16SAndreas Färber 7902273aa16SAndreas Färber uart4_pins: uart4-pins { 7912273aa16SAndreas Färber pins = "PD2", "PD3"; 7922273aa16SAndreas Färber function = "uart4"; 7932273aa16SAndreas Färber }; 7942273aa16SAndreas Färber 7952273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 7962273aa16SAndreas Färber pins = "PD4", "PD5"; 7972273aa16SAndreas Färber function = "uart4"; 7982273aa16SAndreas Färber }; 7996bc37facSAndre Przywara }; 8006bc37facSAndre Przywara 801b399d2acSMarcus Cooper spdif: spdif@1c21000 { 802b399d2acSMarcus Cooper #sound-dai-cells = <0>; 803b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 804b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 805b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 806b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 807b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 808b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 809b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 810b399d2acSMarcus Cooper dmas = <&dma 2>; 811b399d2acSMarcus Cooper dma-names = "tx"; 812b399d2acSMarcus Cooper pinctrl-names = "default"; 813b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 814b399d2acSMarcus Cooper status = "disabled"; 815b399d2acSMarcus Cooper }; 816b399d2acSMarcus Cooper 81784204fb6SLuca Weiss lradc: lradc@1c21800 { 81884204fb6SLuca Weiss compatible = "allwinner,sun50i-a64-lradc", 81984204fb6SLuca Weiss "allwinner,sun8i-a83t-r-lradc"; 82084204fb6SLuca Weiss reg = <0x01c21800 0x400>; 82184204fb6SLuca Weiss interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 82284204fb6SLuca Weiss status = "disabled"; 82384204fb6SLuca Weiss }; 82484204fb6SLuca Weiss 8251c92c009SMarcus Cooper i2s0: i2s@1c22000 { 8261c92c009SMarcus Cooper #sound-dai-cells = <0>; 8271c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8281c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8291c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 8301c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8311c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 8321c92c009SMarcus Cooper clock-names = "apb", "mod"; 8331c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 8341c92c009SMarcus Cooper dma-names = "rx", "tx"; 8351c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 8361c92c009SMarcus Cooper status = "disabled"; 8371c92c009SMarcus Cooper }; 8381c92c009SMarcus Cooper 8391c92c009SMarcus Cooper i2s1: i2s@1c22400 { 8401c92c009SMarcus Cooper #sound-dai-cells = <0>; 8411c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8421c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8431c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 8441c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8451c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 8461c92c009SMarcus Cooper clock-names = "apb", "mod"; 8471c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 8481c92c009SMarcus Cooper dma-names = "rx", "tx"; 8491c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 8501c92c009SMarcus Cooper status = "disabled"; 8511c92c009SMarcus Cooper }; 8521c92c009SMarcus Cooper 853796c994eSMarcus Cooper i2s2: i2s@1c22800 { 854796c994eSMarcus Cooper #sound-dai-cells = <0>; 855796c994eSMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 856796c994eSMarcus Cooper "allwinner,sun8i-h3-i2s"; 857796c994eSMarcus Cooper reg = <0x01c22800 0x400>; 858796c994eSMarcus Cooper interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 859796c994eSMarcus Cooper clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 860796c994eSMarcus Cooper clock-names = "apb", "mod"; 861796c994eSMarcus Cooper resets = <&ccu RST_BUS_I2S2>; 862796c994eSMarcus Cooper dma-names = "rx", "tx"; 863796c994eSMarcus Cooper dmas = <&dma 27>, <&dma 27>; 864796c994eSMarcus Cooper status = "disabled"; 865796c994eSMarcus Cooper }; 866796c994eSMarcus Cooper 867ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 868ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 869ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 870ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 871ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 872ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 873ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 874ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 875ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 876ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 877ec4a9540SVasily Khoruzhick status = "disabled"; 878ec4a9540SVasily Khoruzhick }; 879ec4a9540SVasily Khoruzhick 880ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 881ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 882db9c6ad2SSamuel Holland compatible = "allwinner,sun50i-a64-codec", 883db9c6ad2SSamuel Holland "allwinner,sun8i-a33-codec"; 884ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 885ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 886ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 887ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 888ec4a9540SVasily Khoruzhick status = "disabled"; 889ec4a9540SVasily Khoruzhick }; 890ec4a9540SVasily Khoruzhick 89159f5e9b9SVasily Khoruzhick ths: thermal-sensor@1c25000 { 89259f5e9b9SVasily Khoruzhick compatible = "allwinner,sun50i-a64-ths"; 89359f5e9b9SVasily Khoruzhick reg = <0x01c25000 0x100>; 89459f5e9b9SVasily Khoruzhick clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 89559f5e9b9SVasily Khoruzhick clock-names = "bus", "mod"; 89659f5e9b9SVasily Khoruzhick interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 89759f5e9b9SVasily Khoruzhick resets = <&ccu RST_BUS_THS>; 89859f5e9b9SVasily Khoruzhick nvmem-cells = <&ths_calibration>; 89959f5e9b9SVasily Khoruzhick nvmem-cell-names = "calibration"; 90059f5e9b9SVasily Khoruzhick #thermal-sensor-cells = <1>; 90159f5e9b9SVasily Khoruzhick }; 90259f5e9b9SVasily Khoruzhick 9036bc37facSAndre Przywara uart0: serial@1c28000 { 9046bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9056bc37facSAndre Przywara reg = <0x01c28000 0x400>; 9066bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 9076bc37facSAndre Przywara reg-shift = <2>; 9086bc37facSAndre Przywara reg-io-width = <4>; 909494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 910494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 9116bc37facSAndre Przywara status = "disabled"; 9126bc37facSAndre Przywara }; 9136bc37facSAndre Przywara 9146bc37facSAndre Przywara uart1: serial@1c28400 { 9156bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9166bc37facSAndre Przywara reg = <0x01c28400 0x400>; 9176bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 9186bc37facSAndre Przywara reg-shift = <2>; 9196bc37facSAndre Przywara reg-io-width = <4>; 920494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 921494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 9226bc37facSAndre Przywara status = "disabled"; 9236bc37facSAndre Przywara }; 9246bc37facSAndre Przywara 9256bc37facSAndre Przywara uart2: serial@1c28800 { 9266bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9276bc37facSAndre Przywara reg = <0x01c28800 0x400>; 9286bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 9296bc37facSAndre Przywara reg-shift = <2>; 9306bc37facSAndre Przywara reg-io-width = <4>; 931494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 932494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 9336bc37facSAndre Przywara status = "disabled"; 9346bc37facSAndre Przywara }; 9356bc37facSAndre Przywara 9366bc37facSAndre Przywara uart3: serial@1c28c00 { 9376bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9386bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 9396bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 9406bc37facSAndre Przywara reg-shift = <2>; 9416bc37facSAndre Przywara reg-io-width = <4>; 942494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 943494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 9446bc37facSAndre Przywara status = "disabled"; 9456bc37facSAndre Przywara }; 9466bc37facSAndre Przywara 9476bc37facSAndre Przywara uart4: serial@1c29000 { 9486bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9496bc37facSAndre Przywara reg = <0x01c29000 0x400>; 9506bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 9516bc37facSAndre Przywara reg-shift = <2>; 9526bc37facSAndre Przywara reg-io-width = <4>; 953494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 954494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 9556bc37facSAndre Przywara status = "disabled"; 9566bc37facSAndre Przywara }; 9576bc37facSAndre Przywara 9586bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 9596bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9606bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 9616bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 962494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 963494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 96470f76289SJagan Teki pinctrl-names = "default"; 96570f76289SJagan Teki pinctrl-0 = <&i2c0_pins>; 9666bc37facSAndre Przywara status = "disabled"; 9676bc37facSAndre Przywara #address-cells = <1>; 9686bc37facSAndre Przywara #size-cells = <0>; 9696bc37facSAndre Przywara }; 9706bc37facSAndre Przywara 9716bc37facSAndre Przywara i2c1: i2c@1c2b000 { 9726bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9736bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 9746bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 975494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 976494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 97770f76289SJagan Teki pinctrl-names = "default"; 97870f76289SJagan Teki pinctrl-0 = <&i2c1_pins>; 9796bc37facSAndre Przywara status = "disabled"; 9806bc37facSAndre Przywara #address-cells = <1>; 9816bc37facSAndre Przywara #size-cells = <0>; 9826bc37facSAndre Przywara }; 9836bc37facSAndre Przywara 9846bc37facSAndre Przywara i2c2: i2c@1c2b400 { 9856bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9866bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 9876bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 988494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 989494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 99029b2c68bSOndrej Jirman pinctrl-names = "default"; 99129b2c68bSOndrej Jirman pinctrl-0 = <&i2c2_pins>; 9926bc37facSAndre Przywara status = "disabled"; 9936bc37facSAndre Przywara #address-cells = <1>; 9946bc37facSAndre Przywara #size-cells = <0>; 9956bc37facSAndre Przywara }; 9966bc37facSAndre Przywara 997d6c9da12SCorentin LABBE spi0: spi@1c68000 { 998b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 999b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 1000b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1001b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1002b518bb15SStefan Brüns clock-names = "ahb", "mod"; 100306c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 100406c1258aSStefan Brüns dma-names = "rx", "tx"; 1005b518bb15SStefan Brüns pinctrl-names = "default"; 1006b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 1007b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 1008b518bb15SStefan Brüns status = "disabled"; 1009b518bb15SStefan Brüns num-cs = <1>; 1010b518bb15SStefan Brüns #address-cells = <1>; 1011b518bb15SStefan Brüns #size-cells = <0>; 1012b518bb15SStefan Brüns }; 1013b518bb15SStefan Brüns 1014d6c9da12SCorentin LABBE spi1: spi@1c69000 { 1015b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 1016b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 1017b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1018b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1019b518bb15SStefan Brüns clock-names = "ahb", "mod"; 102006c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 102106c1258aSStefan Brüns dma-names = "rx", "tx"; 1022b518bb15SStefan Brüns pinctrl-names = "default"; 1023b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 1024b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 1025b518bb15SStefan Brüns status = "disabled"; 1026b518bb15SStefan Brüns num-cs = <1>; 1027b518bb15SStefan Brüns #address-cells = <1>; 1028b518bb15SStefan Brüns #size-cells = <0>; 1029b518bb15SStefan Brüns }; 1030b518bb15SStefan Brüns 103194f44288SCorentin Labbe emac: ethernet@1c30000 { 103294f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 103394f44288SCorentin Labbe syscon = <&syscon>; 103494f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 103594f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 103694f44288SCorentin Labbe interrupt-names = "macirq"; 103794f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 103894f44288SCorentin Labbe reset-names = "stmmaceth"; 103994f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 104094f44288SCorentin Labbe clock-names = "stmmaceth"; 104194f44288SCorentin Labbe status = "disabled"; 104294f44288SCorentin Labbe 104394f44288SCorentin Labbe mdio: mdio { 104416416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 104594f44288SCorentin Labbe #address-cells = <1>; 104694f44288SCorentin Labbe #size-cells = <0>; 104794f44288SCorentin Labbe }; 104894f44288SCorentin Labbe }; 104994f44288SCorentin Labbe 10506b683d76SJagan Teki mali: gpu@1c40000 { 10516b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 10526b683d76SJagan Teki reg = <0x01c40000 0x10000>; 10536b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 10546b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 10556b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 10566b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 10576b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 10586b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 10596b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 10606b683d76SJagan Teki interrupt-names = "gp", 10616b683d76SJagan Teki "gpmmu", 10626b683d76SJagan Teki "pp0", 10636b683d76SJagan Teki "ppmmu0", 10646b683d76SJagan Teki "pp1", 10656b683d76SJagan Teki "ppmmu1", 10666b683d76SJagan Teki "pmu"; 10676b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 10686b683d76SJagan Teki clock-names = "bus", "core"; 10696b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 10706b683d76SJagan Teki }; 10716b683d76SJagan Teki 10726bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 10736bc37facSAndre Przywara compatible = "arm,gic-400"; 10746bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 10756bc37facSAndre Przywara <0x01c82000 0x2000>, 10766bc37facSAndre Przywara <0x01c84000 0x2000>, 10776bc37facSAndre Przywara <0x01c86000 0x2000>; 10786bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 10796bc37facSAndre Przywara interrupt-controller; 10806bc37facSAndre Przywara #interrupt-cells = <3>; 10816bc37facSAndre Przywara }; 10826bc37facSAndre Przywara 1083b5df280bSAndre Przywara pwm: pwm@1c21400 { 1084b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1085b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1086b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 1087b5df280bSAndre Przywara clocks = <&osc24M>; 1088b5df280bSAndre Przywara pinctrl-names = "default"; 1089b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 1090b5df280bSAndre Przywara #pwm-cells = <3>; 1091b5df280bSAndre Przywara status = "disabled"; 1092b5df280bSAndre Przywara }; 1093b5df280bSAndre Przywara 1094fc7c2bfbSJernej Skrabec mbus: dram-controller@1c62000 { 1095fc7c2bfbSJernej Skrabec compatible = "allwinner,sun50i-a64-mbus"; 1096fc7c2bfbSJernej Skrabec reg = <0x01c62000 0x1000>; 1097fc7c2bfbSJernej Skrabec clocks = <&ccu 112>; 1098cff11101SOndrej Jirman #address-cells = <1>; 1099cff11101SOndrej Jirman #size-cells = <1>; 1100fc7c2bfbSJernej Skrabec dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1101fc7c2bfbSJernej Skrabec #interconnect-cells = <1>; 1102fc7c2bfbSJernej Skrabec }; 1103fc7c2bfbSJernej Skrabec 1104ff29f13eSJagan Teki csi: csi@1cb0000 { 1105ff29f13eSJagan Teki compatible = "allwinner,sun50i-a64-csi"; 1106ff29f13eSJagan Teki reg = <0x01cb0000 0x1000>; 1107ff29f13eSJagan Teki interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1108ff29f13eSJagan Teki clocks = <&ccu CLK_BUS_CSI>, 1109ff29f13eSJagan Teki <&ccu CLK_CSI_SCLK>, 1110ff29f13eSJagan Teki <&ccu CLK_DRAM_CSI>; 1111ff29f13eSJagan Teki clock-names = "bus", "mod", "ram"; 1112ff29f13eSJagan Teki resets = <&ccu RST_BUS_CSI>; 1113ff29f13eSJagan Teki pinctrl-names = "default"; 1114ff29f13eSJagan Teki pinctrl-0 = <&csi_pins>; 1115ff29f13eSJagan Teki status = "disabled"; 1116ff29f13eSJagan Teki }; 1117ff29f13eSJagan Teki 111816c8ff57SJagan Teki dsi: dsi@1ca0000 { 111916c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dsi"; 112016c8ff57SJagan Teki reg = <0x01ca0000 0x1000>; 112116c8ff57SJagan Teki interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 112216c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>; 112316c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 112416c8ff57SJagan Teki phys = <&dphy>; 112516c8ff57SJagan Teki phy-names = "dphy"; 112616c8ff57SJagan Teki status = "disabled"; 112716c8ff57SJagan Teki #address-cells = <1>; 112816c8ff57SJagan Teki #size-cells = <0>; 112916c8ff57SJagan Teki 113016c8ff57SJagan Teki port { 113116c8ff57SJagan Teki dsi_in_tcon0: endpoint { 113216c8ff57SJagan Teki remote-endpoint = <&tcon0_out_dsi>; 113316c8ff57SJagan Teki }; 113416c8ff57SJagan Teki }; 113516c8ff57SJagan Teki }; 113616c8ff57SJagan Teki 113716c8ff57SJagan Teki dphy: d-phy@1ca1000 { 113816c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dphy", 113916c8ff57SJagan Teki "allwinner,sun6i-a31-mipi-dphy"; 114016c8ff57SJagan Teki reg = <0x01ca1000 0x1000>; 114116c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>, 114216c8ff57SJagan Teki <&ccu CLK_DSI_DPHY>; 114316c8ff57SJagan Teki clock-names = "bus", "mod"; 114416c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 114516c8ff57SJagan Teki status = "disabled"; 114616c8ff57SJagan Teki #phy-cells = <0>; 114716c8ff57SJagan Teki }; 114816c8ff57SJagan Teki 1149dd00d78dSJernej Skrabec deinterlace: deinterlace@1e00000 { 1150dd00d78dSJernej Skrabec compatible = "allwinner,sun50i-a64-deinterlace", 1151dd00d78dSJernej Skrabec "allwinner,sun8i-h3-deinterlace"; 1152dd00d78dSJernej Skrabec reg = <0x01e00000 0x20000>; 1153dd00d78dSJernej Skrabec clocks = <&ccu CLK_BUS_DEINTERLACE>, 1154dd00d78dSJernej Skrabec <&ccu CLK_DEINTERLACE>, 1155dd00d78dSJernej Skrabec <&ccu CLK_DRAM_DEINTERLACE>; 1156dd00d78dSJernej Skrabec clock-names = "bus", "mod", "ram"; 1157dd00d78dSJernej Skrabec resets = <&ccu RST_BUS_DEINTERLACE>; 1158dd00d78dSJernej Skrabec interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1159dd00d78dSJernej Skrabec interconnects = <&mbus 9>; 1160dd00d78dSJernej Skrabec interconnect-names = "dma-mem"; 1161dd00d78dSJernej Skrabec }; 1162dd00d78dSJernej Skrabec 1163e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 1164e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 1165e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 1166e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 1167e85f28e0SJagan Teki reg-io-width = <1>; 1168e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1169e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1170e85f28e0SJagan Teki <&ccu CLK_HDMI>; 1171e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 1172e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 1173e85f28e0SJagan Teki reset-names = "ctrl"; 1174e85f28e0SJagan Teki phys = <&hdmi_phy>; 1175d40113fbSMaxime Ripard phy-names = "phy"; 1176e85f28e0SJagan Teki status = "disabled"; 1177e85f28e0SJagan Teki 1178e85f28e0SJagan Teki ports { 1179e85f28e0SJagan Teki #address-cells = <1>; 1180e85f28e0SJagan Teki #size-cells = <0>; 1181e85f28e0SJagan Teki 1182e85f28e0SJagan Teki hdmi_in: port@0 { 1183e85f28e0SJagan Teki reg = <0>; 1184e85f28e0SJagan Teki 1185e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 1186e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 1187e85f28e0SJagan Teki }; 1188e85f28e0SJagan Teki }; 1189e85f28e0SJagan Teki 1190e85f28e0SJagan Teki hdmi_out: port@1 { 1191e85f28e0SJagan Teki reg = <1>; 1192e85f28e0SJagan Teki }; 1193e85f28e0SJagan Teki }; 1194e85f28e0SJagan Teki }; 1195e85f28e0SJagan Teki 1196e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 1197e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 1198e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 1199e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1200b71818cbSChen-Yu Tsai <&ccu CLK_PLL_VIDEO0>; 1201e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 1202e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 1203e85f28e0SJagan Teki reset-names = "phy"; 1204e85f28e0SJagan Teki #phy-cells = <0>; 1205e85f28e0SJagan Teki }; 1206e85f28e0SJagan Teki 12076bc37facSAndre Przywara rtc: rtc@1f00000 { 120844ff3cafSChen-Yu Tsai compatible = "allwinner,sun50i-a64-rtc", 120944ff3cafSChen-Yu Tsai "allwinner,sun8i-h3-rtc"; 121044ff3cafSChen-Yu Tsai reg = <0x01f00000 0x400>; 12116bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 12126bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 121344ff3cafSChen-Yu Tsai clock-output-names = "osc32k", "osc32k-out", "iosc"; 1214e1a9a474SJagan Teki clocks = <&osc32k>; 1215e1a9a474SJagan Teki #clock-cells = <1>; 12166bc37facSAndre Przywara }; 1217791a9e00SIcenowy Zheng 1218535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 1219535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 1220535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 1221535ca508SIcenowy Zheng interrupt-controller; 1222535ca508SIcenowy Zheng #interrupt-cells = <2>; 1223535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 1224535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1225535ca508SIcenowy Zheng }; 1226535ca508SIcenowy Zheng 1227791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 1228791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 1229791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 1230b71818cbSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 1231b71818cbSChen-Yu Tsai <&ccu CLK_PLL_PERIPH0>; 1232f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 1233791a9e00SIcenowy Zheng #clock-cells = <1>; 1234791a9e00SIcenowy Zheng #reset-cells = <1>; 1235791a9e00SIcenowy Zheng }; 1236ec427905SIcenowy Zheng 1237ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 1238ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 1239ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 1240ec4a9540SVasily Khoruzhick status = "disabled"; 1241ec4a9540SVasily Khoruzhick }; 1242ec4a9540SVasily Khoruzhick 1243871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 1244871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 1245871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 1246871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 1247871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1248871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1249871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1250871b5352SIcenowy Zheng status = "disabled"; 1251871b5352SIcenowy Zheng #address-cells = <1>; 1252871b5352SIcenowy Zheng #size-cells = <0>; 1253871b5352SIcenowy Zheng }; 1254871b5352SIcenowy Zheng 125544a4f416SIgors Makejevs r_ir: ir@1f02000 { 125644a4f416SIgors Makejevs compatible = "allwinner,sun50i-a64-ir", 125744a4f416SIgors Makejevs "allwinner,sun6i-a31-ir"; 125844a4f416SIgors Makejevs reg = <0x01f02000 0x400>; 125944a4f416SIgors Makejevs clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 126044a4f416SIgors Makejevs clock-names = "apb", "ir"; 126144a4f416SIgors Makejevs resets = <&r_ccu RST_APB0_IR>; 126244a4f416SIgors Makejevs interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 126344a4f416SIgors Makejevs pinctrl-names = "default"; 126444a4f416SIgors Makejevs pinctrl-0 = <&r_ir_rx_pin>; 126544a4f416SIgors Makejevs status = "disabled"; 126644a4f416SIgors Makejevs }; 126744a4f416SIgors Makejevs 1268b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1269b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1270b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1271b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1272b5df280bSAndre Przywara clocks = <&osc24M>; 1273b5df280bSAndre Przywara pinctrl-names = "default"; 1274b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1275b5df280bSAndre Przywara #pwm-cells = <3>; 1276b5df280bSAndre Przywara status = "disabled"; 1277b5df280bSAndre Przywara }; 1278b5df280bSAndre Przywara 1279d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1280ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1281ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1282ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1283494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1284ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1285ec427905SIcenowy Zheng gpio-controller; 1286ec427905SIcenowy Zheng #gpio-cells = <3>; 1287ec427905SIcenowy Zheng interrupt-controller; 1288ec427905SIcenowy Zheng #interrupt-cells = <3>; 12893b38fdedSIcenowy Zheng 12901b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1291871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1292871b5352SIcenowy Zheng function = "s_i2c"; 1293871b5352SIcenowy Zheng }; 1294871b5352SIcenowy Zheng 129544a4f416SIgors Makejevs r_ir_rx_pin: r-ir-rx-pin { 129644a4f416SIgors Makejevs pins = "PL11"; 129744a4f416SIgors Makejevs function = "s_cir_rx"; 129844a4f416SIgors Makejevs }; 129944a4f416SIgors Makejevs 130054eac67bSMaxime Ripard r_pwm_pin: r-pwm-pin { 1301b5df280bSAndre Przywara pins = "PL10"; 1302b5df280bSAndre Przywara function = "s_pwm"; 1303b5df280bSAndre Przywara }; 1304b5df280bSAndre Przywara 130554eac67bSMaxime Ripard r_rsb_pins: r-rsb-pins { 13063b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 13073b38fdedSIcenowy Zheng function = "s_rsb"; 13083b38fdedSIcenowy Zheng }; 13093b38fdedSIcenowy Zheng }; 13103b38fdedSIcenowy Zheng 13113b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 13123b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 13133b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 13143b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 13153b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 13163b38fdedSIcenowy Zheng clock-frequency = <3000000>; 13173b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 13183b38fdedSIcenowy Zheng pinctrl-names = "default"; 13193b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 13203b38fdedSIcenowy Zheng status = "disabled"; 13213b38fdedSIcenowy Zheng #address-cells = <1>; 13223b38fdedSIcenowy Zheng #size-cells = <0>; 1323ec427905SIcenowy Zheng }; 1324d4185043SHarald Geyer 1325d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 1326d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 1327d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 1328d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 1329d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 13309e1975f0SMaxime Ripard clocks = <&osc24M>; 1331d4185043SHarald Geyer }; 13326bc37facSAndre Przywara }; 13336bc37facSAndre Przywara}; 1334