16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 46494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 476bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 48a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 496bc37facSAndre Przywara 506bc37facSAndre Przywara/ { 516bc37facSAndre Przywara interrupt-parent = <&gic>; 526bc37facSAndre Przywara #address-cells = <1>; 536bc37facSAndre Przywara #size-cells = <1>; 546bc37facSAndre Przywara 556bc37facSAndre Przywara cpus { 566bc37facSAndre Przywara #address-cells = <1>; 576bc37facSAndre Przywara #size-cells = <0>; 586bc37facSAndre Przywara 596bc37facSAndre Przywara cpu0: cpu@0 { 606bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 616bc37facSAndre Przywara device_type = "cpu"; 626bc37facSAndre Przywara reg = <0>; 636bc37facSAndre Przywara enable-method = "psci"; 646bc37facSAndre Przywara }; 656bc37facSAndre Przywara 666bc37facSAndre Przywara cpu1: cpu@1 { 676bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 686bc37facSAndre Przywara device_type = "cpu"; 696bc37facSAndre Przywara reg = <1>; 706bc37facSAndre Przywara enable-method = "psci"; 716bc37facSAndre Przywara }; 726bc37facSAndre Przywara 736bc37facSAndre Przywara cpu2: cpu@2 { 746bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 756bc37facSAndre Przywara device_type = "cpu"; 766bc37facSAndre Przywara reg = <2>; 776bc37facSAndre Przywara enable-method = "psci"; 786bc37facSAndre Przywara }; 796bc37facSAndre Przywara 806bc37facSAndre Przywara cpu3: cpu@3 { 816bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 826bc37facSAndre Przywara device_type = "cpu"; 836bc37facSAndre Przywara reg = <3>; 846bc37facSAndre Przywara enable-method = "psci"; 856bc37facSAndre Przywara }; 866bc37facSAndre Przywara }; 876bc37facSAndre Przywara 886bc37facSAndre Przywara osc24M: osc24M_clk { 896bc37facSAndre Przywara #clock-cells = <0>; 906bc37facSAndre Przywara compatible = "fixed-clock"; 916bc37facSAndre Przywara clock-frequency = <24000000>; 926bc37facSAndre Przywara clock-output-names = "osc24M"; 936bc37facSAndre Przywara }; 946bc37facSAndre Przywara 956bc37facSAndre Przywara osc32k: osc32k_clk { 966bc37facSAndre Przywara #clock-cells = <0>; 976bc37facSAndre Przywara compatible = "fixed-clock"; 986bc37facSAndre Przywara clock-frequency = <32768>; 996bc37facSAndre Przywara clock-output-names = "osc32k"; 1006bc37facSAndre Przywara }; 1016bc37facSAndre Przywara 102791a9e00SIcenowy Zheng iosc: internal-osc-clk { 103791a9e00SIcenowy Zheng #clock-cells = <0>; 104791a9e00SIcenowy Zheng compatible = "fixed-clock"; 105791a9e00SIcenowy Zheng clock-frequency = <16000000>; 106791a9e00SIcenowy Zheng clock-accuracy = <300000000>; 107791a9e00SIcenowy Zheng clock-output-names = "iosc"; 108791a9e00SIcenowy Zheng }; 109791a9e00SIcenowy Zheng 1106bc37facSAndre Przywara psci { 1116bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1126bc37facSAndre Przywara method = "smc"; 1136bc37facSAndre Przywara }; 1146bc37facSAndre Przywara 1156bc37facSAndre Przywara timer { 1166bc37facSAndre Przywara compatible = "arm,armv8-timer"; 1176bc37facSAndre Przywara interrupts = <GIC_PPI 13 1186bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1196bc37facSAndre Przywara <GIC_PPI 14 1206bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1216bc37facSAndre Przywara <GIC_PPI 11 1226bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1236bc37facSAndre Przywara <GIC_PPI 10 1246bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1256bc37facSAndre Przywara }; 1266bc37facSAndre Przywara 1276bc37facSAndre Przywara soc { 1286bc37facSAndre Przywara compatible = "simple-bus"; 1296bc37facSAndre Przywara #address-cells = <1>; 1306bc37facSAndre Przywara #size-cells = <1>; 1316bc37facSAndre Przywara ranges; 1326bc37facSAndre Przywara 13379b95360SCorentin Labbe syscon: syscon@1c00000 { 13479b95360SCorentin Labbe compatible = "allwinner,sun50i-a64-system-controller", 13579b95360SCorentin Labbe "syscon"; 13679b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 13779b95360SCorentin Labbe }; 13879b95360SCorentin Labbe 139f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 140f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 141f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 142f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 143f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 144f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 145f3dff347SAndre Przywara reset-names = "ahb"; 146f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 14722be992fSMaxime Ripard max-frequency = <150000000>; 148f3dff347SAndre Przywara status = "disabled"; 149f3dff347SAndre Przywara #address-cells = <1>; 150f3dff347SAndre Przywara #size-cells = <0>; 151f3dff347SAndre Przywara }; 152f3dff347SAndre Przywara 153f3dff347SAndre Przywara mmc1: mmc@1c10000 { 154f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 155f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 156f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 157f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 158f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 159f3dff347SAndre Przywara reset-names = "ahb"; 160f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 16122be992fSMaxime Ripard max-frequency = <150000000>; 162f3dff347SAndre Przywara status = "disabled"; 163f3dff347SAndre Przywara #address-cells = <1>; 164f3dff347SAndre Przywara #size-cells = <0>; 165f3dff347SAndre Przywara }; 166f3dff347SAndre Przywara 167f3dff347SAndre Przywara mmc2: mmc@1c11000 { 168f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 169f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 170f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 171f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 172f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 173f3dff347SAndre Przywara reset-names = "ahb"; 174f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 17522be992fSMaxime Ripard max-frequency = <200000000>; 176f3dff347SAndre Przywara status = "disabled"; 177f3dff347SAndre Przywara #address-cells = <1>; 178f3dff347SAndre Przywara #size-cells = <0>; 179f3dff347SAndre Przywara }; 180f3dff347SAndre Przywara 181d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 182972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 183972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 184972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 185972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 186972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 187972a3ecdSIcenowy Zheng interrupt-names = "mc"; 188972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 189972a3ecdSIcenowy Zheng phy-names = "usb"; 190972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 191972a3ecdSIcenowy Zheng status = "disabled"; 192972a3ecdSIcenowy Zheng }; 193972a3ecdSIcenowy Zheng 194d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 195a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 196a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 1970d984797SIcenowy Zheng <0x01c1a800 0x4>, 198a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 199a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 2000d984797SIcenowy Zheng "pmu0", 201a004ee35SIcenowy Zheng "pmu1"; 202a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 203a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 204a004ee35SIcenowy Zheng clock-names = "usb0_phy", 205a004ee35SIcenowy Zheng "usb1_phy"; 206a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 207a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 208a004ee35SIcenowy Zheng reset-names = "usb0_reset", 209a004ee35SIcenowy Zheng "usb1_reset"; 210a004ee35SIcenowy Zheng status = "disabled"; 211a004ee35SIcenowy Zheng #phy-cells = <1>; 212a004ee35SIcenowy Zheng }; 213a004ee35SIcenowy Zheng 214d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 215dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 216dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 217dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 218dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 219dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 220dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 221dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 222dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 223dc03a047SIcenowy Zheng status = "disabled"; 224dc03a047SIcenowy Zheng }; 225dc03a047SIcenowy Zheng 226d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 227dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 228dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 229dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 230dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 231dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 232dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 233dc03a047SIcenowy Zheng status = "disabled"; 234dc03a047SIcenowy Zheng }; 235dc03a047SIcenowy Zheng 236d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 237a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 238a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 239a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 240a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 241a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 242a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 243a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 244a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 245a004ee35SIcenowy Zheng phys = <&usbphy 1>; 246a004ee35SIcenowy Zheng phy-names = "usb"; 247a004ee35SIcenowy Zheng status = "disabled"; 248a004ee35SIcenowy Zheng }; 249a004ee35SIcenowy Zheng 250d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 251a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 252a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 253a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 254a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 255a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 256a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 257a004ee35SIcenowy Zheng phys = <&usbphy 1>; 258a004ee35SIcenowy Zheng phy-names = "usb"; 259a004ee35SIcenowy Zheng status = "disabled"; 260a004ee35SIcenowy Zheng }; 261a004ee35SIcenowy Zheng 262d6c9da12SCorentin LABBE ccu: clock@1c20000 { 2636bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 2646bc37facSAndre Przywara reg = <0x01c20000 0x400>; 2656bc37facSAndre Przywara clocks = <&osc24M>, <&osc32k>; 2666bc37facSAndre Przywara clock-names = "hosc", "losc"; 2676bc37facSAndre Przywara #clock-cells = <1>; 2686bc37facSAndre Przywara #reset-cells = <1>; 2696bc37facSAndre Przywara }; 2706bc37facSAndre Przywara 2716bc37facSAndre Przywara pio: pinctrl@1c20800 { 2726bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 2736bc37facSAndre Przywara reg = <0x01c20800 0x400>; 2746bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2756bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2766bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 277f98121f3SArnd Bergmann clocks = <&ccu 58>; 2786bc37facSAndre Przywara gpio-controller; 2796bc37facSAndre Przywara #gpio-cells = <3>; 2806bc37facSAndre Przywara interrupt-controller; 2816bc37facSAndre Przywara #interrupt-cells = <3>; 2826bc37facSAndre Przywara 2836bc37facSAndre Przywara i2c1_pins: i2c1_pins { 2846bc37facSAndre Przywara pins = "PH2", "PH3"; 2856bc37facSAndre Przywara function = "i2c1"; 2866bc37facSAndre Przywara }; 2876bc37facSAndre Przywara 288a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 289a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 290a3e8f492SMaxime Ripard "PF4", "PF5"; 291a3e8f492SMaxime Ripard function = "mmc0"; 292a3e8f492SMaxime Ripard drive-strength = <30>; 293a3e8f492SMaxime Ripard bias-pull-up; 294a3e8f492SMaxime Ripard }; 295a3e8f492SMaxime Ripard 296a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 297a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 298a3e8f492SMaxime Ripard "PG4", "PG5"; 299a3e8f492SMaxime Ripard function = "mmc1"; 300a3e8f492SMaxime Ripard drive-strength = <30>; 301a3e8f492SMaxime Ripard bias-pull-up; 302a3e8f492SMaxime Ripard }; 303a3e8f492SMaxime Ripard 304a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 305a3e8f492SMaxime Ripard pins = "PC1", "PC5", "PC6", "PC8", "PC9", 306a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 307a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 308a3e8f492SMaxime Ripard function = "mmc2"; 309a3e8f492SMaxime Ripard drive-strength = <30>; 310a3e8f492SMaxime Ripard bias-pull-up; 311a3e8f492SMaxime Ripard }; 312a3e8f492SMaxime Ripard 313e53f67e9SCorentin Labbe rmii_pins: rmii_pins { 314e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 315e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 316e53f67e9SCorentin Labbe function = "emac"; 317e53f67e9SCorentin Labbe drive-strength = <40>; 318e53f67e9SCorentin Labbe }; 319e53f67e9SCorentin Labbe 320e53f67e9SCorentin Labbe rgmii_pins: rgmii_pins { 321e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 322e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 323e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 324e53f67e9SCorentin Labbe function = "emac"; 325e53f67e9SCorentin Labbe drive-strength = <40>; 326e53f67e9SCorentin Labbe }; 327e53f67e9SCorentin Labbe 328b518bb15SStefan Brüns spi0_pins: spi0 { 329b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 330b518bb15SStefan Brüns function = "spi0"; 331b518bb15SStefan Brüns }; 332b518bb15SStefan Brüns 333b518bb15SStefan Brüns spi1_pins: spi1 { 334b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 335b518bb15SStefan Brüns function = "spi1"; 336b518bb15SStefan Brüns }; 337b518bb15SStefan Brüns 33892d378fbSCorentin LABBE uart0_pins_a: uart0 { 3396bc37facSAndre Przywara pins = "PB8", "PB9"; 3406bc37facSAndre Przywara function = "uart0"; 3416bc37facSAndre Przywara }; 342e7ba733dSAndre Przywara 343e7ba733dSAndre Przywara uart1_pins: uart1_pins { 344e7ba733dSAndre Przywara pins = "PG6", "PG7"; 345e7ba733dSAndre Przywara function = "uart1"; 346e7ba733dSAndre Przywara }; 347e7ba733dSAndre Przywara 348e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 349e7ba733dSAndre Przywara pins = "PG8", "PG9"; 350e7ba733dSAndre Przywara function = "uart1"; 351e7ba733dSAndre Przywara }; 35279825719SAndreas Färber 35379825719SAndreas Färber uart2_pins: uart2-pins { 35479825719SAndreas Färber pins = "PB0", "PB1"; 35579825719SAndreas Färber function = "uart2"; 35679825719SAndreas Färber }; 3572273aa16SAndreas Färber 3582273aa16SAndreas Färber uart3_pins: uart3-pins { 3592273aa16SAndreas Färber pins = "PD0", "PD1"; 3602273aa16SAndreas Färber function = "uart3"; 3612273aa16SAndreas Färber }; 3622273aa16SAndreas Färber 3632273aa16SAndreas Färber uart4_pins: uart4-pins { 3642273aa16SAndreas Färber pins = "PD2", "PD3"; 3652273aa16SAndreas Färber function = "uart4"; 3662273aa16SAndreas Färber }; 3672273aa16SAndreas Färber 3682273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 3692273aa16SAndreas Färber pins = "PD4", "PD5"; 3702273aa16SAndreas Färber function = "uart4"; 3712273aa16SAndreas Färber }; 3726bc37facSAndre Przywara }; 3736bc37facSAndre Przywara 3746bc37facSAndre Przywara uart0: serial@1c28000 { 3756bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3766bc37facSAndre Przywara reg = <0x01c28000 0x400>; 3776bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3786bc37facSAndre Przywara reg-shift = <2>; 3796bc37facSAndre Przywara reg-io-width = <4>; 380494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 381494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 3826bc37facSAndre Przywara status = "disabled"; 3836bc37facSAndre Przywara }; 3846bc37facSAndre Przywara 3856bc37facSAndre Przywara uart1: serial@1c28400 { 3866bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3876bc37facSAndre Przywara reg = <0x01c28400 0x400>; 3886bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 3896bc37facSAndre Przywara reg-shift = <2>; 3906bc37facSAndre Przywara reg-io-width = <4>; 391494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 392494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 3936bc37facSAndre Przywara status = "disabled"; 3946bc37facSAndre Przywara }; 3956bc37facSAndre Przywara 3966bc37facSAndre Przywara uart2: serial@1c28800 { 3976bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3986bc37facSAndre Przywara reg = <0x01c28800 0x400>; 3996bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 4006bc37facSAndre Przywara reg-shift = <2>; 4016bc37facSAndre Przywara reg-io-width = <4>; 402494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 403494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 4046bc37facSAndre Przywara status = "disabled"; 4056bc37facSAndre Przywara }; 4066bc37facSAndre Przywara 4076bc37facSAndre Przywara uart3: serial@1c28c00 { 4086bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 4096bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 4106bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 4116bc37facSAndre Przywara reg-shift = <2>; 4126bc37facSAndre Przywara reg-io-width = <4>; 413494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 414494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 4156bc37facSAndre Przywara status = "disabled"; 4166bc37facSAndre Przywara }; 4176bc37facSAndre Przywara 4186bc37facSAndre Przywara uart4: serial@1c29000 { 4196bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 4206bc37facSAndre Przywara reg = <0x01c29000 0x400>; 4216bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 4226bc37facSAndre Przywara reg-shift = <2>; 4236bc37facSAndre Przywara reg-io-width = <4>; 424494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 425494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 4266bc37facSAndre Przywara status = "disabled"; 4276bc37facSAndre Przywara }; 4286bc37facSAndre Przywara 4296bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 4306bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 4316bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 4326bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 433494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 434494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 4356bc37facSAndre Przywara status = "disabled"; 4366bc37facSAndre Przywara #address-cells = <1>; 4376bc37facSAndre Przywara #size-cells = <0>; 4386bc37facSAndre Przywara }; 4396bc37facSAndre Przywara 4406bc37facSAndre Przywara i2c1: i2c@1c2b000 { 4416bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 4426bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 4436bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 444494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 445494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 4466bc37facSAndre Przywara status = "disabled"; 4476bc37facSAndre Przywara #address-cells = <1>; 4486bc37facSAndre Przywara #size-cells = <0>; 4496bc37facSAndre Przywara }; 4506bc37facSAndre Przywara 4516bc37facSAndre Przywara i2c2: i2c@1c2b400 { 4526bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 4536bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 4546bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 455494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 456494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 4576bc37facSAndre Przywara status = "disabled"; 4586bc37facSAndre Przywara #address-cells = <1>; 4596bc37facSAndre Przywara #size-cells = <0>; 4606bc37facSAndre Przywara }; 4616bc37facSAndre Przywara 462b518bb15SStefan Brüns 463d6c9da12SCorentin LABBE spi0: spi@1c68000 { 464b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 465b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 466b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 467b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 468b518bb15SStefan Brüns clock-names = "ahb", "mod"; 469b518bb15SStefan Brüns pinctrl-names = "default"; 470b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 471b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 472b518bb15SStefan Brüns status = "disabled"; 473b518bb15SStefan Brüns num-cs = <1>; 474b518bb15SStefan Brüns #address-cells = <1>; 475b518bb15SStefan Brüns #size-cells = <0>; 476b518bb15SStefan Brüns }; 477b518bb15SStefan Brüns 478d6c9da12SCorentin LABBE spi1: spi@1c69000 { 479b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 480b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 481b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 482b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 483b518bb15SStefan Brüns clock-names = "ahb", "mod"; 484b518bb15SStefan Brüns pinctrl-names = "default"; 485b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 486b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 487b518bb15SStefan Brüns status = "disabled"; 488b518bb15SStefan Brüns num-cs = <1>; 489b518bb15SStefan Brüns #address-cells = <1>; 490b518bb15SStefan Brüns #size-cells = <0>; 491b518bb15SStefan Brüns }; 492b518bb15SStefan Brüns 4936bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 4946bc37facSAndre Przywara compatible = "arm,gic-400"; 4956bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 4966bc37facSAndre Przywara <0x01c82000 0x2000>, 4976bc37facSAndre Przywara <0x01c84000 0x2000>, 4986bc37facSAndre Przywara <0x01c86000 0x2000>; 4996bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 5006bc37facSAndre Przywara interrupt-controller; 5016bc37facSAndre Przywara #interrupt-cells = <3>; 5026bc37facSAndre Przywara }; 5036bc37facSAndre Przywara 5046bc37facSAndre Przywara rtc: rtc@1f00000 { 5056bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-rtc"; 5066bc37facSAndre Przywara reg = <0x01f00000 0x54>; 5076bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 5086bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 5096bc37facSAndre Przywara }; 510791a9e00SIcenowy Zheng 511535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 512535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 513535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 514535ca508SIcenowy Zheng interrupt-controller; 515535ca508SIcenowy Zheng #interrupt-cells = <2>; 516535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 517535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 518535ca508SIcenowy Zheng }; 519535ca508SIcenowy Zheng 520791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 521791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 522791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 523f74994a9SChen-Yu Tsai clocks = <&osc24M>, <&osc32k>, <&iosc>, 524f74994a9SChen-Yu Tsai <&ccu 11>; 525f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 526791a9e00SIcenowy Zheng #clock-cells = <1>; 527791a9e00SIcenowy Zheng #reset-cells = <1>; 528791a9e00SIcenowy Zheng }; 529ec427905SIcenowy Zheng 530d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 531ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 532ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 533ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 534494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 535ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 536ec427905SIcenowy Zheng gpio-controller; 537ec427905SIcenowy Zheng #gpio-cells = <3>; 538ec427905SIcenowy Zheng interrupt-controller; 539ec427905SIcenowy Zheng #interrupt-cells = <3>; 5403b38fdedSIcenowy Zheng 54192d378fbSCorentin LABBE r_rsb_pins: rsb { 5423b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 5433b38fdedSIcenowy Zheng function = "s_rsb"; 5443b38fdedSIcenowy Zheng }; 5453b38fdedSIcenowy Zheng }; 5463b38fdedSIcenowy Zheng 5473b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 5483b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 5493b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 5503b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 5513b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 5523b38fdedSIcenowy Zheng clock-frequency = <3000000>; 5533b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 5543b38fdedSIcenowy Zheng pinctrl-names = "default"; 5553b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 5563b38fdedSIcenowy Zheng status = "disabled"; 5573b38fdedSIcenowy Zheng #address-cells = <1>; 5583b38fdedSIcenowy Zheng #size-cells = <0>; 559ec427905SIcenowy Zheng }; 5606bc37facSAndre Przywara }; 5616bc37facSAndre Przywara}; 562