1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd.
3cabbaed7SClément Péron// based on the Allwinner H3 dtsi:
4cabbaed7SClément Péron//    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
56bc37facSAndre Przywara
6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h>
71b9dac68SSamuel Holland#include <dt-bindings/clock/sun6i-rtc.h>
82c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h>
9494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h>
106bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h>
11a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h>
122c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h>
13871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h>
1459f5e9b9SVasily Khoruzhick#include <dt-bindings/thermal/thermal.h>
156bc37facSAndre Przywara
166bc37facSAndre Przywara/ {
176bc37facSAndre Przywara	interrupt-parent = <&gic>;
186bc37facSAndre Przywara	#address-cells = <1>;
196bc37facSAndre Przywara	#size-cells = <1>;
206bc37facSAndre Przywara
21c1cff65fSHarald Geyer	chosen {
22c1cff65fSHarald Geyer		#address-cells = <1>;
23c1cff65fSHarald Geyer		#size-cells = <1>;
24c1cff65fSHarald Geyer		ranges;
25c1cff65fSHarald Geyer
26c1cff65fSHarald Geyer		simplefb_lcd: framebuffer-lcd {
27c1cff65fSHarald Geyer			compatible = "allwinner,simple-framebuffer",
28c1cff65fSHarald Geyer				     "simple-framebuffer";
29c1cff65fSHarald Geyer			allwinner,pipeline = "mixer0-lcd0";
30c1cff65fSHarald Geyer			clocks = <&ccu CLK_TCON0>,
312c796fc8SIcenowy Zheng				 <&display_clocks CLK_MIXER0>;
32c1cff65fSHarald Geyer			status = "disabled";
33c1cff65fSHarald Geyer		};
34fca63f58SIcenowy Zheng
35fca63f58SIcenowy Zheng		simplefb_hdmi: framebuffer-hdmi {
36fca63f58SIcenowy Zheng			compatible = "allwinner,simple-framebuffer",
37fca63f58SIcenowy Zheng				     "simple-framebuffer";
38fca63f58SIcenowy Zheng			allwinner,pipeline = "mixer1-lcd1-hdmi";
39fca63f58SIcenowy Zheng			clocks = <&display_clocks CLK_MIXER1>,
40fca63f58SIcenowy Zheng				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41fca63f58SIcenowy Zheng			status = "disabled";
42fca63f58SIcenowy Zheng		};
43c1cff65fSHarald Geyer	};
44c1cff65fSHarald Geyer
456bc37facSAndre Przywara	cpus {
466bc37facSAndre Przywara		#address-cells = <1>;
476bc37facSAndre Przywara		#size-cells = <0>;
486bc37facSAndre Przywara
496bc37facSAndre Przywara		cpu0: cpu@0 {
5031af04cdSRob Herring			compatible = "arm,cortex-a53";
516bc37facSAndre Przywara			device_type = "cpu";
526bc37facSAndre Przywara			reg = <0>;
536bc37facSAndre Przywara			enable-method = "psci";
5439defc81SAndre Przywara			next-level-cache = <&L2>;
557db1aa6fSAlexander Kochetkov			clocks = <&ccu CLK_CPUX>;
56f267eff7SVasily Khoruzhick			clock-names = "cpu";
57e1c3804aSVasily Khoruzhick			#cooling-cells = <2>;
586bc37facSAndre Przywara		};
596bc37facSAndre Przywara
606bc37facSAndre Przywara		cpu1: cpu@1 {
6131af04cdSRob Herring			compatible = "arm,cortex-a53";
626bc37facSAndre Przywara			device_type = "cpu";
636bc37facSAndre Przywara			reg = <1>;
646bc37facSAndre Przywara			enable-method = "psci";
6539defc81SAndre Przywara			next-level-cache = <&L2>;
667db1aa6fSAlexander Kochetkov			clocks = <&ccu CLK_CPUX>;
67f267eff7SVasily Khoruzhick			clock-names = "cpu";
68e1c3804aSVasily Khoruzhick			#cooling-cells = <2>;
696bc37facSAndre Przywara		};
706bc37facSAndre Przywara
716bc37facSAndre Przywara		cpu2: cpu@2 {
7231af04cdSRob Herring			compatible = "arm,cortex-a53";
736bc37facSAndre Przywara			device_type = "cpu";
746bc37facSAndre Przywara			reg = <2>;
756bc37facSAndre Przywara			enable-method = "psci";
7639defc81SAndre Przywara			next-level-cache = <&L2>;
777db1aa6fSAlexander Kochetkov			clocks = <&ccu CLK_CPUX>;
78f267eff7SVasily Khoruzhick			clock-names = "cpu";
79e1c3804aSVasily Khoruzhick			#cooling-cells = <2>;
806bc37facSAndre Przywara		};
816bc37facSAndre Przywara
826bc37facSAndre Przywara		cpu3: cpu@3 {
8331af04cdSRob Herring			compatible = "arm,cortex-a53";
846bc37facSAndre Przywara			device_type = "cpu";
856bc37facSAndre Przywara			reg = <3>;
866bc37facSAndre Przywara			enable-method = "psci";
8739defc81SAndre Przywara			next-level-cache = <&L2>;
887db1aa6fSAlexander Kochetkov			clocks = <&ccu CLK_CPUX>;
89f267eff7SVasily Khoruzhick			clock-names = "cpu";
90e1c3804aSVasily Khoruzhick			#cooling-cells = <2>;
9139defc81SAndre Przywara		};
9239defc81SAndre Przywara
9339defc81SAndre Przywara		L2: l2-cache {
9439defc81SAndre Przywara			compatible = "cache";
9539defc81SAndre Przywara			cache-level = <2>;
966bc37facSAndre Przywara		};
976bc37facSAndre Przywara	};
986bc37facSAndre Przywara
99e85f28e0SJagan Teki	de: display-engine {
100e85f28e0SJagan Teki		compatible = "allwinner,sun50i-a64-display-engine";
101e85f28e0SJagan Teki		allwinner,pipelines = <&mixer0>,
102e85f28e0SJagan Teki				      <&mixer1>;
103e85f28e0SJagan Teki		status = "disabled";
104e85f28e0SJagan Teki	};
105e85f28e0SJagan Teki
106e954a7afSJernej Skrabec	gpu_opp_table: opp-table-gpu {
107e954a7afSJernej Skrabec		compatible = "operating-points-v2";
108e954a7afSJernej Skrabec
109e954a7afSJernej Skrabec		opp-120000000 {
110e954a7afSJernej Skrabec			opp-hz = /bits/ 64 <120000000>;
111e954a7afSJernej Skrabec		};
112e954a7afSJernej Skrabec
113e954a7afSJernej Skrabec		opp-312000000 {
114e954a7afSJernej Skrabec			opp-hz = /bits/ 64 <312000000>;
115e954a7afSJernej Skrabec		};
116e954a7afSJernej Skrabec
117e954a7afSJernej Skrabec		opp-432000000 {
118e954a7afSJernej Skrabec			opp-hz = /bits/ 64 <432000000>;
119e954a7afSJernej Skrabec		};
120e954a7afSJernej Skrabec	};
121e954a7afSJernej Skrabec
1226bc37facSAndre Przywara	osc24M: osc24M_clk {
1236bc37facSAndre Przywara		#clock-cells = <0>;
1246bc37facSAndre Przywara		compatible = "fixed-clock";
1256bc37facSAndre Przywara		clock-frequency = <24000000>;
1266bc37facSAndre Przywara		clock-output-names = "osc24M";
1276bc37facSAndre Przywara	};
1286bc37facSAndre Przywara
1296bc37facSAndre Przywara	osc32k: osc32k_clk {
1306bc37facSAndre Przywara		#clock-cells = <0>;
1316bc37facSAndre Przywara		compatible = "fixed-clock";
1326bc37facSAndre Przywara		clock-frequency = <32768>;
13344ff3cafSChen-Yu Tsai		clock-output-names = "ext-osc32k";
134791a9e00SIcenowy Zheng	};
135791a9e00SIcenowy Zheng
13634a97fccSHarald Geyer	pmu {
13734a97fccSHarald Geyer		compatible = "arm,cortex-a53-pmu";
1386b832a14SAndre Przywara		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1396b832a14SAndre Przywara			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1406b832a14SAndre Przywara			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1416b832a14SAndre Przywara			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
14234a97fccSHarald Geyer		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
14334a97fccSHarald Geyer	};
14434a97fccSHarald Geyer
1456bc37facSAndre Przywara	psci {
1466bc37facSAndre Przywara		compatible = "arm,psci-0.2";
1476bc37facSAndre Przywara		method = "smc";
1486bc37facSAndre Przywara	};
1496bc37facSAndre Przywara
150ec4a9540SVasily Khoruzhick	sound: sound {
151984a51c5SSamuel Holland		#address-cells = <1>;
152984a51c5SSamuel Holland		#size-cells = <0>;
153ec4a9540SVasily Khoruzhick		compatible = "simple-audio-card";
154ec4a9540SVasily Khoruzhick		simple-audio-card,name = "sun50i-a64-audio";
155ec4a9540SVasily Khoruzhick		simple-audio-card,aux-devs = <&codec_analog>;
156ec4a9540SVasily Khoruzhick		simple-audio-card,routing =
157631e6a35SSamuel Holland				"Left DAC", "DACL",
158631e6a35SSamuel Holland				"Right DAC", "DACR",
159631e6a35SSamuel Holland				"ADCL", "Left ADC",
160631e6a35SSamuel Holland				"ADCR", "Right ADC";
161ec4a9540SVasily Khoruzhick		status = "disabled";
162ec4a9540SVasily Khoruzhick
163984a51c5SSamuel Holland		simple-audio-card,dai-link@0 {
164984a51c5SSamuel Holland			format = "i2s";
165984a51c5SSamuel Holland			frame-master = <&link0_cpu>;
166984a51c5SSamuel Holland			bitclock-master = <&link0_cpu>;
167984a51c5SSamuel Holland			mclk-fs = <128>;
168984a51c5SSamuel Holland
169984a51c5SSamuel Holland			link0_cpu: cpu {
170ec4a9540SVasily Khoruzhick				sound-dai = <&dai>;
171ec4a9540SVasily Khoruzhick			};
172ec4a9540SVasily Khoruzhick
173984a51c5SSamuel Holland			link0_codec: codec {
174e0cd8e01SSamuel Holland				sound-dai = <&codec 0>;
175ec4a9540SVasily Khoruzhick			};
176ec4a9540SVasily Khoruzhick		};
177984a51c5SSamuel Holland	};
178ec4a9540SVasily Khoruzhick
1796bc37facSAndre Przywara	timer {
1806bc37facSAndre Przywara		compatible = "arm,armv8-timer";
18155ec26d6SSamuel Holland		allwinner,erratum-unknown1;
182a371b1bdSSamuel Holland		arm,no-tick-in-suspend;
1836bc37facSAndre Przywara		interrupts = <GIC_PPI 13
1846bc37facSAndre Przywara			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
1856bc37facSAndre Przywara			     <GIC_PPI 14
1866bc37facSAndre Przywara			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
1876bc37facSAndre Przywara			     <GIC_PPI 11
1886bc37facSAndre Przywara			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
1896bc37facSAndre Przywara			     <GIC_PPI 10
1906bc37facSAndre Przywara			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1916bc37facSAndre Przywara	};
1926bc37facSAndre Przywara
19359f5e9b9SVasily Khoruzhick	thermal-zones {
19459f5e9b9SVasily Khoruzhick		cpu_thermal: cpu0-thermal {
19559f5e9b9SVasily Khoruzhick			/* milliseconds */
19659f5e9b9SVasily Khoruzhick			polling-delay-passive = <0>;
19759f5e9b9SVasily Khoruzhick			polling-delay = <0>;
19859f5e9b9SVasily Khoruzhick			thermal-sensors = <&ths 0>;
199e1c3804aSVasily Khoruzhick
200e1c3804aSVasily Khoruzhick			cooling-maps {
201e1c3804aSVasily Khoruzhick				map0 {
202e1c3804aSVasily Khoruzhick					trip = <&cpu_alert0>;
203e1c3804aSVasily Khoruzhick					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
204e1c3804aSVasily Khoruzhick							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
205e1c3804aSVasily Khoruzhick							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206e1c3804aSVasily Khoruzhick							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
207e1c3804aSVasily Khoruzhick				};
208e1c3804aSVasily Khoruzhick				map1 {
209e1c3804aSVasily Khoruzhick					trip = <&cpu_alert1>;
210e1c3804aSVasily Khoruzhick					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
211e1c3804aSVasily Khoruzhick							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
212e1c3804aSVasily Khoruzhick							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
213e1c3804aSVasily Khoruzhick							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
214e1c3804aSVasily Khoruzhick				};
215e1c3804aSVasily Khoruzhick			};
216e1c3804aSVasily Khoruzhick
217e1c3804aSVasily Khoruzhick			trips {
218e1c3804aSVasily Khoruzhick				cpu_alert0: cpu_alert0 {
219e1c3804aSVasily Khoruzhick					/* milliCelsius */
220e1c3804aSVasily Khoruzhick					temperature = <75000>;
221e1c3804aSVasily Khoruzhick					hysteresis = <2000>;
222e1c3804aSVasily Khoruzhick					type = "passive";
223e1c3804aSVasily Khoruzhick				};
224e1c3804aSVasily Khoruzhick
225e1c3804aSVasily Khoruzhick				cpu_alert1: cpu_alert1 {
226e1c3804aSVasily Khoruzhick					/* milliCelsius */
227e1c3804aSVasily Khoruzhick					temperature = <90000>;
228e1c3804aSVasily Khoruzhick					hysteresis = <2000>;
229e1c3804aSVasily Khoruzhick					type = "hot";
230e1c3804aSVasily Khoruzhick				};
231e1c3804aSVasily Khoruzhick
232e1c3804aSVasily Khoruzhick				cpu_crit: cpu_crit {
233e1c3804aSVasily Khoruzhick					/* milliCelsius */
234e1c3804aSVasily Khoruzhick					temperature = <110000>;
235e1c3804aSVasily Khoruzhick					hysteresis = <2000>;
236e1c3804aSVasily Khoruzhick					type = "critical";
237e1c3804aSVasily Khoruzhick				};
238e1c3804aSVasily Khoruzhick			};
23959f5e9b9SVasily Khoruzhick		};
24059f5e9b9SVasily Khoruzhick
24159f5e9b9SVasily Khoruzhick		gpu0_thermal: gpu0-thermal {
24259f5e9b9SVasily Khoruzhick			/* milliseconds */
24359f5e9b9SVasily Khoruzhick			polling-delay-passive = <0>;
24459f5e9b9SVasily Khoruzhick			polling-delay = <0>;
24559f5e9b9SVasily Khoruzhick			thermal-sensors = <&ths 1>;
24659f5e9b9SVasily Khoruzhick		};
24759f5e9b9SVasily Khoruzhick
24859f5e9b9SVasily Khoruzhick		gpu1_thermal: gpu1-thermal {
24959f5e9b9SVasily Khoruzhick			/* milliseconds */
25059f5e9b9SVasily Khoruzhick			polling-delay-passive = <0>;
25159f5e9b9SVasily Khoruzhick			polling-delay = <0>;
25259f5e9b9SVasily Khoruzhick			thermal-sensors = <&ths 2>;
25359f5e9b9SVasily Khoruzhick		};
25459f5e9b9SVasily Khoruzhick	};
25559f5e9b9SVasily Khoruzhick
2566bc37facSAndre Przywara	soc {
2576bc37facSAndre Przywara		compatible = "simple-bus";
2586bc37facSAndre Przywara		#address-cells = <1>;
2596bc37facSAndre Przywara		#size-cells = <1>;
2606bc37facSAndre Przywara		ranges;
2616bc37facSAndre Przywara
262275b6317SMaxime Ripard		bus@1000000 {
2632c796fc8SIcenowy Zheng			compatible = "allwinner,sun50i-a64-de2";
2642c796fc8SIcenowy Zheng			reg = <0x1000000 0x400000>;
2652c796fc8SIcenowy Zheng			allwinner,sram = <&de2_sram 1>;
2662c796fc8SIcenowy Zheng			#address-cells = <1>;
2672c796fc8SIcenowy Zheng			#size-cells = <1>;
2682c796fc8SIcenowy Zheng			ranges = <0 0x1000000 0x400000>;
2692c796fc8SIcenowy Zheng
2702c796fc8SIcenowy Zheng			display_clocks: clock@0 {
2712c796fc8SIcenowy Zheng				compatible = "allwinner,sun50i-a64-de2-clk";
2723e9a1a8bSJernej Skrabec				reg = <0x0 0x10000>;
2735ea40f71SMaxime Ripard				clocks = <&ccu CLK_BUS_DE>,
2745ea40f71SMaxime Ripard					 <&ccu CLK_DE>;
2755ea40f71SMaxime Ripard				clock-names = "bus",
2765ea40f71SMaxime Ripard					      "mod";
2772c796fc8SIcenowy Zheng				resets = <&ccu RST_BUS_DE>;
2782c796fc8SIcenowy Zheng				#clock-cells = <1>;
2792c796fc8SIcenowy Zheng				#reset-cells = <1>;
2802c796fc8SIcenowy Zheng			};
281e85f28e0SJagan Teki
282048cdfceSJernej Skrabec			rotate: rotate@20000 {
283048cdfceSJernej Skrabec				compatible = "allwinner,sun50i-a64-de2-rotate",
284048cdfceSJernej Skrabec					     "allwinner,sun8i-a83t-de2-rotate";
285048cdfceSJernej Skrabec				reg = <0x20000 0x10000>;
286048cdfceSJernej Skrabec				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
287048cdfceSJernej Skrabec				clocks = <&display_clocks CLK_BUS_ROT>,
288048cdfceSJernej Skrabec					 <&display_clocks CLK_ROT>;
289048cdfceSJernej Skrabec				clock-names = "bus",
290048cdfceSJernej Skrabec					      "mod";
291048cdfceSJernej Skrabec				resets = <&display_clocks RST_ROT>;
292048cdfceSJernej Skrabec			};
293048cdfceSJernej Skrabec
294e85f28e0SJagan Teki			mixer0: mixer@100000 {
295e85f28e0SJagan Teki				compatible = "allwinner,sun50i-a64-de2-mixer-0";
296e85f28e0SJagan Teki				reg = <0x100000 0x100000>;
297e85f28e0SJagan Teki				clocks = <&display_clocks CLK_BUS_MIXER0>,
298e85f28e0SJagan Teki					 <&display_clocks CLK_MIXER0>;
299e85f28e0SJagan Teki				clock-names = "bus",
300e85f28e0SJagan Teki					      "mod";
301e85f28e0SJagan Teki				resets = <&display_clocks RST_MIXER0>;
302e85f28e0SJagan Teki
303e85f28e0SJagan Teki				ports {
304e85f28e0SJagan Teki					#address-cells = <1>;
305e85f28e0SJagan Teki					#size-cells = <0>;
306e85f28e0SJagan Teki
307e85f28e0SJagan Teki					mixer0_out: port@1 {
308a7f7047fSMaxime Ripard						#address-cells = <1>;
309a7f7047fSMaxime Ripard						#size-cells = <0>;
310e85f28e0SJagan Teki						reg = <1>;
311e85f28e0SJagan Teki
312a7f7047fSMaxime Ripard						mixer0_out_tcon0: endpoint@0 {
313a7f7047fSMaxime Ripard							reg = <0>;
314e85f28e0SJagan Teki							remote-endpoint = <&tcon0_in_mixer0>;
315e85f28e0SJagan Teki						};
316a7f7047fSMaxime Ripard
317a7f7047fSMaxime Ripard						mixer0_out_tcon1: endpoint@1 {
318a7f7047fSMaxime Ripard							reg = <1>;
319a7f7047fSMaxime Ripard							remote-endpoint = <&tcon1_in_mixer0>;
320a7f7047fSMaxime Ripard						};
321e85f28e0SJagan Teki					};
322e85f28e0SJagan Teki				};
323e85f28e0SJagan Teki			};
324e85f28e0SJagan Teki
325e85f28e0SJagan Teki			mixer1: mixer@200000 {
326e85f28e0SJagan Teki				compatible = "allwinner,sun50i-a64-de2-mixer-1";
327e85f28e0SJagan Teki				reg = <0x200000 0x100000>;
328e85f28e0SJagan Teki				clocks = <&display_clocks CLK_BUS_MIXER1>,
329e85f28e0SJagan Teki					 <&display_clocks CLK_MIXER1>;
330e85f28e0SJagan Teki				clock-names = "bus",
331e85f28e0SJagan Teki					      "mod";
332e85f28e0SJagan Teki				resets = <&display_clocks RST_MIXER1>;
333e85f28e0SJagan Teki
334e85f28e0SJagan Teki				ports {
335e85f28e0SJagan Teki					#address-cells = <1>;
336e85f28e0SJagan Teki					#size-cells = <0>;
337e85f28e0SJagan Teki
338e85f28e0SJagan Teki					mixer1_out: port@1 {
339d41a43a0SMaxime Ripard						#address-cells = <1>;
340d41a43a0SMaxime Ripard						#size-cells = <0>;
341e85f28e0SJagan Teki						reg = <1>;
342e85f28e0SJagan Teki
343a7f7047fSMaxime Ripard						mixer1_out_tcon0: endpoint@0 {
344a7f7047fSMaxime Ripard							reg = <0>;
345a7f7047fSMaxime Ripard							remote-endpoint = <&tcon0_in_mixer1>;
346a7f7047fSMaxime Ripard						};
347a7f7047fSMaxime Ripard
348a7f7047fSMaxime Ripard						mixer1_out_tcon1: endpoint@1 {
349a7f7047fSMaxime Ripard							reg = <1>;
350e85f28e0SJagan Teki							remote-endpoint = <&tcon1_in_mixer1>;
351e85f28e0SJagan Teki						};
352e85f28e0SJagan Teki					};
353e85f28e0SJagan Teki				};
354e85f28e0SJagan Teki			};
3552c796fc8SIcenowy Zheng		};
3562c796fc8SIcenowy Zheng
35779b95360SCorentin Labbe		syscon: syscon@1c00000 {
3581f1f5183SIcenowy Zheng			compatible = "allwinner,sun50i-a64-system-control";
35979b95360SCorentin Labbe			reg = <0x01c00000 0x1000>;
3601f1f5183SIcenowy Zheng			#address-cells = <1>;
3611f1f5183SIcenowy Zheng			#size-cells = <1>;
3621f1f5183SIcenowy Zheng			ranges;
3631f1f5183SIcenowy Zheng
3641f1f5183SIcenowy Zheng			sram_c: sram@18000 {
3651f1f5183SIcenowy Zheng				compatible = "mmio-sram";
3661f1f5183SIcenowy Zheng				reg = <0x00018000 0x28000>;
3671f1f5183SIcenowy Zheng				#address-cells = <1>;
3681f1f5183SIcenowy Zheng				#size-cells = <1>;
3691f1f5183SIcenowy Zheng				ranges = <0 0x00018000 0x28000>;
3701f1f5183SIcenowy Zheng
3711f1f5183SIcenowy Zheng				de2_sram: sram-section@0 {
3721f1f5183SIcenowy Zheng					compatible = "allwinner,sun50i-a64-sram-c";
3731f1f5183SIcenowy Zheng					reg = <0x0000 0x28000>;
3741f1f5183SIcenowy Zheng				};
3751f1f5183SIcenowy Zheng			};
376106deea8SPaul Kocialkowski
377106deea8SPaul Kocialkowski			sram_c1: sram@1d00000 {
378106deea8SPaul Kocialkowski				compatible = "mmio-sram";
379106deea8SPaul Kocialkowski				reg = <0x01d00000 0x40000>;
380106deea8SPaul Kocialkowski				#address-cells = <1>;
381106deea8SPaul Kocialkowski				#size-cells = <1>;
382106deea8SPaul Kocialkowski				ranges = <0 0x01d00000 0x40000>;
383106deea8SPaul Kocialkowski
384106deea8SPaul Kocialkowski				ve_sram: sram-section@0 {
385106deea8SPaul Kocialkowski					compatible = "allwinner,sun50i-a64-sram-c1",
386106deea8SPaul Kocialkowski						     "allwinner,sun4i-a10-sram-c1";
387106deea8SPaul Kocialkowski					reg = <0x000000 0x40000>;
388106deea8SPaul Kocialkowski				};
389106deea8SPaul Kocialkowski			};
39079b95360SCorentin Labbe		};
39179b95360SCorentin Labbe
392c32637e0SStefan Brüns		dma: dma-controller@1c02000 {
393c32637e0SStefan Brüns			compatible = "allwinner,sun50i-a64-dma";
394c32637e0SStefan Brüns			reg = <0x01c02000 0x1000>;
395c32637e0SStefan Brüns			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
396c32637e0SStefan Brüns			clocks = <&ccu CLK_BUS_DMA>;
397c32637e0SStefan Brüns			dma-channels = <8>;
398c32637e0SStefan Brüns			dma-requests = <27>;
399c32637e0SStefan Brüns			resets = <&ccu RST_BUS_DMA>;
400c32637e0SStefan Brüns			#dma-cells = <1>;
401c32637e0SStefan Brüns		};
402c32637e0SStefan Brüns
403e85f28e0SJagan Teki		tcon0: lcd-controller@1c0c000 {
404e85f28e0SJagan Teki			compatible = "allwinner,sun50i-a64-tcon-lcd",
405e85f28e0SJagan Teki				     "allwinner,sun8i-a83t-tcon-lcd";
406e85f28e0SJagan Teki			reg = <0x01c0c000 0x1000>;
407e85f28e0SJagan Teki			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
408e85f28e0SJagan Teki			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
409e85f28e0SJagan Teki			clock-names = "ahb", "tcon-ch0";
410e85f28e0SJagan Teki			clock-output-names = "tcon-pixel-clock";
41126c609d5SMaxime Ripard			#clock-cells = <0>;
412e85f28e0SJagan Teki			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
413e85f28e0SJagan Teki			reset-names = "lcd", "lvds";
414e85f28e0SJagan Teki
415e85f28e0SJagan Teki			ports {
416e85f28e0SJagan Teki				#address-cells = <1>;
417e85f28e0SJagan Teki				#size-cells = <0>;
418e85f28e0SJagan Teki
419e85f28e0SJagan Teki				tcon0_in: port@0 {
420e85f28e0SJagan Teki					#address-cells = <1>;
421e85f28e0SJagan Teki					#size-cells = <0>;
422e85f28e0SJagan Teki					reg = <0>;
423e85f28e0SJagan Teki
424e85f28e0SJagan Teki					tcon0_in_mixer0: endpoint@0 {
425e85f28e0SJagan Teki						reg = <0>;
426e85f28e0SJagan Teki						remote-endpoint = <&mixer0_out_tcon0>;
427e85f28e0SJagan Teki					};
428a7f7047fSMaxime Ripard
429a7f7047fSMaxime Ripard					tcon0_in_mixer1: endpoint@1 {
430a7f7047fSMaxime Ripard						reg = <1>;
431d41a43a0SMaxime Ripard						remote-endpoint = <&mixer1_out_tcon0>;
432a7f7047fSMaxime Ripard					};
433e85f28e0SJagan Teki				};
434e85f28e0SJagan Teki
435e85f28e0SJagan Teki				tcon0_out: port@1 {
436e85f28e0SJagan Teki					#address-cells = <1>;
437e85f28e0SJagan Teki					#size-cells = <0>;
438e85f28e0SJagan Teki					reg = <1>;
43916c8ff57SJagan Teki
44016c8ff57SJagan Teki					tcon0_out_dsi: endpoint@1 {
44116c8ff57SJagan Teki						reg = <1>;
44216c8ff57SJagan Teki						remote-endpoint = <&dsi_in_tcon0>;
44316c8ff57SJagan Teki						allwinner,tcon-channel = <1>;
44416c8ff57SJagan Teki					};
445e85f28e0SJagan Teki				};
446e85f28e0SJagan Teki			};
447e85f28e0SJagan Teki		};
448e85f28e0SJagan Teki
449e85f28e0SJagan Teki		tcon1: lcd-controller@1c0d000 {
450e85f28e0SJagan Teki			compatible = "allwinner,sun50i-a64-tcon-tv",
451e85f28e0SJagan Teki				     "allwinner,sun8i-a83t-tcon-tv";
452e85f28e0SJagan Teki			reg = <0x01c0d000 0x1000>;
453e85f28e0SJagan Teki			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
454e85f28e0SJagan Teki			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
455e85f28e0SJagan Teki			clock-names = "ahb", "tcon-ch1";
456e85f28e0SJagan Teki			resets = <&ccu RST_BUS_TCON1>;
457e85f28e0SJagan Teki			reset-names = "lcd";
458e85f28e0SJagan Teki
459e85f28e0SJagan Teki			ports {
460e85f28e0SJagan Teki				#address-cells = <1>;
461e85f28e0SJagan Teki				#size-cells = <0>;
462e85f28e0SJagan Teki
463e85f28e0SJagan Teki				tcon1_in: port@0 {
464a7f7047fSMaxime Ripard					#address-cells = <1>;
465a7f7047fSMaxime Ripard					#size-cells = <0>;
466e85f28e0SJagan Teki					reg = <0>;
467e85f28e0SJagan Teki
468a7f7047fSMaxime Ripard					tcon1_in_mixer0: endpoint@0 {
469a7f7047fSMaxime Ripard						reg = <0>;
470a7f7047fSMaxime Ripard						remote-endpoint = <&mixer0_out_tcon1>;
471a7f7047fSMaxime Ripard					};
472a7f7047fSMaxime Ripard
473a7f7047fSMaxime Ripard					tcon1_in_mixer1: endpoint@1 {
474a7f7047fSMaxime Ripard						reg = <1>;
475e85f28e0SJagan Teki						remote-endpoint = <&mixer1_out_tcon1>;
476e85f28e0SJagan Teki					};
477e85f28e0SJagan Teki				};
478e85f28e0SJagan Teki
479e85f28e0SJagan Teki				tcon1_out: port@1 {
480e85f28e0SJagan Teki					#address-cells = <1>;
481e85f28e0SJagan Teki					#size-cells = <0>;
482e85f28e0SJagan Teki					reg = <1>;
483e85f28e0SJagan Teki
484e85f28e0SJagan Teki					tcon1_out_hdmi: endpoint@1 {
485e85f28e0SJagan Teki						reg = <1>;
486e85f28e0SJagan Teki						remote-endpoint = <&hdmi_in_tcon1>;
487e85f28e0SJagan Teki					};
488e85f28e0SJagan Teki				};
489e85f28e0SJagan Teki			};
490e85f28e0SJagan Teki		};
491e85f28e0SJagan Teki
492d60ce247SPaul Kocialkowski		video-codec@1c0e000 {
4934ab88516SPaul Kocialkowski			compatible = "allwinner,sun50i-a64-video-engine";
494d60ce247SPaul Kocialkowski			reg = <0x01c0e000 0x1000>;
495d60ce247SPaul Kocialkowski			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
496d60ce247SPaul Kocialkowski				 <&ccu CLK_DRAM_VE>;
497d60ce247SPaul Kocialkowski			clock-names = "ahb", "mod", "ram";
498d60ce247SPaul Kocialkowski			resets = <&ccu RST_BUS_VE>;
499d60ce247SPaul Kocialkowski			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
500d60ce247SPaul Kocialkowski			allwinner,sram = <&ve_sram 1>;
501d60ce247SPaul Kocialkowski		};
502d60ce247SPaul Kocialkowski
503f3dff347SAndre Przywara		mmc0: mmc@1c0f000 {
504f3dff347SAndre Przywara			compatible = "allwinner,sun50i-a64-mmc";
505f3dff347SAndre Przywara			reg = <0x01c0f000 0x1000>;
506f3dff347SAndre Przywara			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
507f3dff347SAndre Przywara			clock-names = "ahb", "mmc";
508f3dff347SAndre Przywara			resets = <&ccu RST_BUS_MMC0>;
509f3dff347SAndre Przywara			reset-names = "ahb";
510f3dff347SAndre Przywara			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
51122be992fSMaxime Ripard			max-frequency = <150000000>;
512f3dff347SAndre Przywara			status = "disabled";
513f3dff347SAndre Przywara			#address-cells = <1>;
514f3dff347SAndre Przywara			#size-cells = <0>;
515f3dff347SAndre Przywara		};
516f3dff347SAndre Przywara
517f3dff347SAndre Przywara		mmc1: mmc@1c10000 {
518f3dff347SAndre Przywara			compatible = "allwinner,sun50i-a64-mmc";
519f3dff347SAndre Przywara			reg = <0x01c10000 0x1000>;
520f3dff347SAndre Przywara			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
521f3dff347SAndre Przywara			clock-names = "ahb", "mmc";
522f3dff347SAndre Przywara			resets = <&ccu RST_BUS_MMC1>;
523f3dff347SAndre Przywara			reset-names = "ahb";
524f3dff347SAndre Przywara			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
52522be992fSMaxime Ripard			max-frequency = <150000000>;
526f3dff347SAndre Przywara			status = "disabled";
527f3dff347SAndre Przywara			#address-cells = <1>;
528f3dff347SAndre Przywara			#size-cells = <0>;
529f3dff347SAndre Przywara		};
530f3dff347SAndre Przywara
531f3dff347SAndre Przywara		mmc2: mmc@1c11000 {
532f3dff347SAndre Przywara			compatible = "allwinner,sun50i-a64-emmc";
533f3dff347SAndre Przywara			reg = <0x01c11000 0x1000>;
534f3dff347SAndre Przywara			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
535f3dff347SAndre Przywara			clock-names = "ahb", "mmc";
536f3dff347SAndre Przywara			resets = <&ccu RST_BUS_MMC2>;
537f3dff347SAndre Przywara			reset-names = "ahb";
538f3dff347SAndre Przywara			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
539948c657cSAndre Przywara			max-frequency = <150000000>;
540f3dff347SAndre Przywara			status = "disabled";
541f3dff347SAndre Przywara			#address-cells = <1>;
542f3dff347SAndre Przywara			#size-cells = <0>;
543f3dff347SAndre Przywara		};
544f3dff347SAndre Przywara
545ac947b17SEmmanuel Vadot		sid: eeprom@1c14000 {
546ac947b17SEmmanuel Vadot			compatible = "allwinner,sun50i-a64-sid";
547ac947b17SEmmanuel Vadot			reg = <0x1c14000 0x400>;
54859f5e9b9SVasily Khoruzhick			#address-cells = <1>;
54959f5e9b9SVasily Khoruzhick			#size-cells = <1>;
55059f5e9b9SVasily Khoruzhick
55159f5e9b9SVasily Khoruzhick			ths_calibration: thermal-sensor-calibration@34 {
55259f5e9b9SVasily Khoruzhick				reg = <0x34 0x8>;
55359f5e9b9SVasily Khoruzhick			};
554ac947b17SEmmanuel Vadot		};
555ac947b17SEmmanuel Vadot
5560f5fc158SCorentin Labbe		crypto: crypto@1c15000 {
5570f5fc158SCorentin Labbe			compatible = "allwinner,sun50i-a64-crypto";
5580f5fc158SCorentin Labbe			reg = <0x01c15000 0x1000>;
5590f5fc158SCorentin Labbe			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5600f5fc158SCorentin Labbe			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
5610f5fc158SCorentin Labbe			clock-names = "bus", "mod";
5620f5fc158SCorentin Labbe			resets = <&ccu RST_BUS_CE>;
5630f5fc158SCorentin Labbe		};
5640f5fc158SCorentin Labbe
5653e3f39a7SSamuel Holland		msgbox: mailbox@1c17000 {
5663e3f39a7SSamuel Holland			compatible = "allwinner,sun50i-a64-msgbox",
5673e3f39a7SSamuel Holland				     "allwinner,sun6i-a31-msgbox";
5683e3f39a7SSamuel Holland			reg = <0x01c17000 0x1000>;
5693e3f39a7SSamuel Holland			clocks = <&ccu CLK_BUS_MSGBOX>;
5703e3f39a7SSamuel Holland			resets = <&ccu RST_BUS_MSGBOX>;
5713e3f39a7SSamuel Holland			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
5723e3f39a7SSamuel Holland			#mbox-cells = <1>;
5733e3f39a7SSamuel Holland		};
5743e3f39a7SSamuel Holland
575d6c9da12SCorentin LABBE		usb_otg: usb@1c19000 {
576972a3ecdSIcenowy Zheng			compatible = "allwinner,sun8i-a33-musb";
577972a3ecdSIcenowy Zheng			reg = <0x01c19000 0x0400>;
578972a3ecdSIcenowy Zheng			clocks = <&ccu CLK_BUS_OTG>;
579972a3ecdSIcenowy Zheng			resets = <&ccu RST_BUS_OTG>;
580972a3ecdSIcenowy Zheng			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
581972a3ecdSIcenowy Zheng			interrupt-names = "mc";
582972a3ecdSIcenowy Zheng			phys = <&usbphy 0>;
583972a3ecdSIcenowy Zheng			phy-names = "usb";
584972a3ecdSIcenowy Zheng			extcon = <&usbphy 0>;
5850973c06bSMaxime Ripard			dr_mode = "otg";
586972a3ecdSIcenowy Zheng			status = "disabled";
587972a3ecdSIcenowy Zheng		};
588972a3ecdSIcenowy Zheng
589d6c9da12SCorentin LABBE		usbphy: phy@1c19400 {
590a004ee35SIcenowy Zheng			compatible = "allwinner,sun50i-a64-usb-phy";
591a004ee35SIcenowy Zheng			reg = <0x01c19400 0x14>,
5920d984797SIcenowy Zheng			      <0x01c1a800 0x4>,
593a004ee35SIcenowy Zheng			      <0x01c1b800 0x4>;
594a004ee35SIcenowy Zheng			reg-names = "phy_ctrl",
5950d984797SIcenowy Zheng				    "pmu0",
596a004ee35SIcenowy Zheng				    "pmu1";
597a004ee35SIcenowy Zheng			clocks = <&ccu CLK_USB_PHY0>,
598a004ee35SIcenowy Zheng				 <&ccu CLK_USB_PHY1>;
599a004ee35SIcenowy Zheng			clock-names = "usb0_phy",
600a004ee35SIcenowy Zheng				      "usb1_phy";
601a004ee35SIcenowy Zheng			resets = <&ccu RST_USB_PHY0>,
602a004ee35SIcenowy Zheng				 <&ccu RST_USB_PHY1>;
603a004ee35SIcenowy Zheng			reset-names = "usb0_reset",
604a004ee35SIcenowy Zheng				      "usb1_reset";
605a004ee35SIcenowy Zheng			status = "disabled";
606a004ee35SIcenowy Zheng			#phy-cells = <1>;
607a004ee35SIcenowy Zheng		};
608a004ee35SIcenowy Zheng
609d6c9da12SCorentin LABBE		ehci0: usb@1c1a000 {
610dc03a047SIcenowy Zheng			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
611dc03a047SIcenowy Zheng			reg = <0x01c1a000 0x100>;
612dc03a047SIcenowy Zheng			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
613dc03a047SIcenowy Zheng			clocks = <&ccu CLK_BUS_OHCI0>,
614dc03a047SIcenowy Zheng				 <&ccu CLK_BUS_EHCI0>,
615dc03a047SIcenowy Zheng				 <&ccu CLK_USB_OHCI0>;
616dc03a047SIcenowy Zheng			resets = <&ccu RST_BUS_OHCI0>,
617dc03a047SIcenowy Zheng				 <&ccu RST_BUS_EHCI0>;
618cc725707SAndre Przywara			phys = <&usbphy 0>;
619cc725707SAndre Przywara			phy-names = "usb";
620dc03a047SIcenowy Zheng			status = "disabled";
621dc03a047SIcenowy Zheng		};
622dc03a047SIcenowy Zheng
623d6c9da12SCorentin LABBE		ohci0: usb@1c1a400 {
624dc03a047SIcenowy Zheng			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
625dc03a047SIcenowy Zheng			reg = <0x01c1a400 0x100>;
626dc03a047SIcenowy Zheng			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
627dc03a047SIcenowy Zheng			clocks = <&ccu CLK_BUS_OHCI0>,
628dc03a047SIcenowy Zheng				 <&ccu CLK_USB_OHCI0>;
629dc03a047SIcenowy Zheng			resets = <&ccu RST_BUS_OHCI0>;
630cc725707SAndre Przywara			phys = <&usbphy 0>;
631cc725707SAndre Przywara			phy-names = "usb";
632dc03a047SIcenowy Zheng			status = "disabled";
633dc03a047SIcenowy Zheng		};
634dc03a047SIcenowy Zheng
635d6c9da12SCorentin LABBE		ehci1: usb@1c1b000 {
636a004ee35SIcenowy Zheng			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
637a004ee35SIcenowy Zheng			reg = <0x01c1b000 0x100>;
638a004ee35SIcenowy Zheng			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
639a004ee35SIcenowy Zheng			clocks = <&ccu CLK_BUS_OHCI1>,
640a004ee35SIcenowy Zheng				 <&ccu CLK_BUS_EHCI1>,
641a004ee35SIcenowy Zheng				 <&ccu CLK_USB_OHCI1>;
642a004ee35SIcenowy Zheng			resets = <&ccu RST_BUS_OHCI1>,
643a004ee35SIcenowy Zheng				 <&ccu RST_BUS_EHCI1>;
644a004ee35SIcenowy Zheng			phys = <&usbphy 1>;
645e6064cf4SMaxime Ripard			phy-names = "usb";
646a004ee35SIcenowy Zheng			status = "disabled";
647a004ee35SIcenowy Zheng		};
648a004ee35SIcenowy Zheng
649d6c9da12SCorentin LABBE		ohci1: usb@1c1b400 {
650a004ee35SIcenowy Zheng			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
651a004ee35SIcenowy Zheng			reg = <0x01c1b400 0x100>;
652a004ee35SIcenowy Zheng			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
653a004ee35SIcenowy Zheng			clocks = <&ccu CLK_BUS_OHCI1>,
654a004ee35SIcenowy Zheng				 <&ccu CLK_USB_OHCI1>;
655a004ee35SIcenowy Zheng			resets = <&ccu RST_BUS_OHCI1>;
656a004ee35SIcenowy Zheng			phys = <&usbphy 1>;
657e6064cf4SMaxime Ripard			phy-names = "usb";
658a004ee35SIcenowy Zheng			status = "disabled";
659a004ee35SIcenowy Zheng		};
660a004ee35SIcenowy Zheng
661d6c9da12SCorentin LABBE		ccu: clock@1c20000 {
6626bc37facSAndre Przywara			compatible = "allwinner,sun50i-a64-ccu";
6636bc37facSAndre Przywara			reg = <0x01c20000 0x400>;
6641b9dac68SSamuel Holland			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
6656bc37facSAndre Przywara			clock-names = "hosc", "losc";
6666bc37facSAndre Przywara			#clock-cells = <1>;
6676bc37facSAndre Przywara			#reset-cells = <1>;
6686bc37facSAndre Przywara		};
6696bc37facSAndre Przywara
6706bc37facSAndre Przywara		pio: pinctrl@1c20800 {
6716bc37facSAndre Przywara			compatible = "allwinner,sun50i-a64-pinctrl";
6726bc37facSAndre Przywara			reg = <0x01c20800 0x400>;
673189bef23SSamuel Holland			interrupt-parent = <&r_intc>;
6746bc37facSAndre Przywara			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
6756bc37facSAndre Przywara				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
6766bc37facSAndre Przywara				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
6771b9dac68SSamuel Holland			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
6781b9dac68SSamuel Holland				 <&rtc CLK_OSC32K>;
679562bf196SMaxime Ripard			clock-names = "apb", "hosc", "losc";
6806bc37facSAndre Przywara			gpio-controller;
6816bc37facSAndre Przywara			#gpio-cells = <3>;
6826bc37facSAndre Przywara			interrupt-controller;
6836bc37facSAndre Przywara			#interrupt-cells = <3>;
6846bc37facSAndre Przywara
68509e0a7eaSSamuel Holland			/omit-if-no-ref/
68609e0a7eaSSamuel Holland			aif2_pins: aif2-pins {
68709e0a7eaSSamuel Holland				pins = "PB4", "PB5", "PB6", "PB7";
68809e0a7eaSSamuel Holland				function = "aif2";
68909e0a7eaSSamuel Holland			};
69009e0a7eaSSamuel Holland
69109e0a7eaSSamuel Holland			/omit-if-no-ref/
69209e0a7eaSSamuel Holland			aif3_pins: aif3-pins {
69309e0a7eaSSamuel Holland				pins = "PG10", "PG11", "PG12", "PG13";
69409e0a7eaSSamuel Holland				function = "aif3";
69509e0a7eaSSamuel Holland			};
69609e0a7eaSSamuel Holland
697ff29f13eSJagan Teki			csi_pins: csi-pins {
698ff29f13eSJagan Teki				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
699ff29f13eSJagan Teki				       "PE7", "PE8", "PE9", "PE10", "PE11";
700ff29f13eSJagan Teki				function = "csi";
701ff29f13eSJagan Teki			};
702ff29f13eSJagan Teki
703f7056b28SJagan Teki			/omit-if-no-ref/
704f7056b28SJagan Teki			csi_mclk_pin: csi-mclk-pin {
705f7056b28SJagan Teki				pins = "PE1";
706f7056b28SJagan Teki				function = "csi";
707f7056b28SJagan Teki			};
708f7056b28SJagan Teki
70954eac67bSMaxime Ripard			i2c0_pins: i2c0-pins {
71011239fe6SHarald Geyer				pins = "PH0", "PH1";
71111239fe6SHarald Geyer				function = "i2c0";
71211239fe6SHarald Geyer			};
71311239fe6SHarald Geyer
71454eac67bSMaxime Ripard			i2c1_pins: i2c1-pins {
7156bc37facSAndre Przywara				pins = "PH2", "PH3";
7166bc37facSAndre Przywara				function = "i2c1";
7176bc37facSAndre Przywara			};
7186bc37facSAndre Przywara
71929b2c68bSOndrej Jirman			i2c2_pins: i2c2-pins {
72029b2c68bSOndrej Jirman				pins = "PE14", "PE15";
72129b2c68bSOndrej Jirman				function = "i2c2";
72229b2c68bSOndrej Jirman			};
72329b2c68bSOndrej Jirman
724c478a12eSIcenowy Zheng			/omit-if-no-ref/
725c478a12eSIcenowy Zheng			lcd_rgb666_pins: lcd-rgb666-pins {
726c478a12eSIcenowy Zheng				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
727c478a12eSIcenowy Zheng				       "PD5", "PD6", "PD7", "PD8", "PD9",
728c478a12eSIcenowy Zheng				       "PD10", "PD11", "PD12", "PD13",
729c478a12eSIcenowy Zheng				       "PD14", "PD15", "PD16", "PD17",
730c478a12eSIcenowy Zheng				       "PD18", "PD19", "PD20", "PD21";
731c478a12eSIcenowy Zheng				function = "lcd0";
732c478a12eSIcenowy Zheng			};
733c478a12eSIcenowy Zheng
734a3e8f492SMaxime Ripard			mmc0_pins: mmc0-pins {
735a3e8f492SMaxime Ripard				pins = "PF0", "PF1", "PF2", "PF3",
736a3e8f492SMaxime Ripard				       "PF4", "PF5";
737a3e8f492SMaxime Ripard				function = "mmc0";
738a3e8f492SMaxime Ripard				drive-strength = <30>;
739a3e8f492SMaxime Ripard				bias-pull-up;
740a3e8f492SMaxime Ripard			};
741a3e8f492SMaxime Ripard
742a3e8f492SMaxime Ripard			mmc1_pins: mmc1-pins {
743a3e8f492SMaxime Ripard				pins = "PG0", "PG1", "PG2", "PG3",
744a3e8f492SMaxime Ripard				       "PG4", "PG5";
745a3e8f492SMaxime Ripard				function = "mmc1";
746a3e8f492SMaxime Ripard				drive-strength = <30>;
747a3e8f492SMaxime Ripard				bias-pull-up;
748a3e8f492SMaxime Ripard			};
749a3e8f492SMaxime Ripard
750a3e8f492SMaxime Ripard			mmc2_pins: mmc2-pins {
751fa59dd2eSChen-Yu Tsai				pins = "PC5", "PC6", "PC8", "PC9",
752a3e8f492SMaxime Ripard				       "PC10","PC11", "PC12", "PC13",
753a3e8f492SMaxime Ripard				       "PC14", "PC15", "PC16";
754a3e8f492SMaxime Ripard				function = "mmc2";
755a3e8f492SMaxime Ripard				drive-strength = <30>;
756a3e8f492SMaxime Ripard				bias-pull-up;
757a3e8f492SMaxime Ripard			};
758a3e8f492SMaxime Ripard
759fa59dd2eSChen-Yu Tsai			mmc2_ds_pin: mmc2-ds-pin {
760fa59dd2eSChen-Yu Tsai				pins = "PC1";
761fa59dd2eSChen-Yu Tsai				function = "mmc2";
762fa59dd2eSChen-Yu Tsai				drive-strength = <30>;
763fa59dd2eSChen-Yu Tsai				bias-pull-up;
764fa59dd2eSChen-Yu Tsai			};
765fa59dd2eSChen-Yu Tsai
76654eac67bSMaxime Ripard			pwm_pin: pwm-pin {
767b5df280bSAndre Przywara				pins = "PD22";
768b5df280bSAndre Przywara				function = "pwm";
769b5df280bSAndre Przywara			};
770b5df280bSAndre Przywara
77154eac67bSMaxime Ripard			rmii_pins: rmii-pins {
772e53f67e9SCorentin Labbe				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
773e53f67e9SCorentin Labbe				       "PD18", "PD19", "PD20", "PD22", "PD23";
774e53f67e9SCorentin Labbe				function = "emac";
775e53f67e9SCorentin Labbe				drive-strength = <40>;
776e53f67e9SCorentin Labbe			};
777e53f67e9SCorentin Labbe
77854eac67bSMaxime Ripard			rgmii_pins: rgmii-pins {
779e53f67e9SCorentin Labbe				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
780e53f67e9SCorentin Labbe				       "PD13", "PD15", "PD16", "PD17", "PD18",
781e53f67e9SCorentin Labbe				       "PD19", "PD20", "PD21", "PD22", "PD23";
782e53f67e9SCorentin Labbe				function = "emac";
783e53f67e9SCorentin Labbe				drive-strength = <40>;
784e53f67e9SCorentin Labbe			};
785e53f67e9SCorentin Labbe
78654eac67bSMaxime Ripard			spdif_tx_pin: spdif-tx-pin {
787b399d2acSMarcus Cooper				pins = "PH8";
788b399d2acSMarcus Cooper				function = "spdif";
789b399d2acSMarcus Cooper			};
790b399d2acSMarcus Cooper
79154eac67bSMaxime Ripard			spi0_pins: spi0-pins {
792b518bb15SStefan Brüns				pins = "PC0", "PC1", "PC2", "PC3";
793b518bb15SStefan Brüns				function = "spi0";
794b518bb15SStefan Brüns			};
795b518bb15SStefan Brüns
79654eac67bSMaxime Ripard			spi1_pins: spi1-pins {
797b518bb15SStefan Brüns				pins = "PD0", "PD1", "PD2", "PD3";
798b518bb15SStefan Brüns				function = "spi1";
799b518bb15SStefan Brüns			};
800b518bb15SStefan Brüns
801d91ebb95SChen-Yu Tsai			uart0_pb_pins: uart0-pb-pins {
8026bc37facSAndre Przywara				pins = "PB8", "PB9";
8036bc37facSAndre Przywara				function = "uart0";
8046bc37facSAndre Przywara			};
805e7ba733dSAndre Przywara
80654eac67bSMaxime Ripard			uart1_pins: uart1-pins {
807e7ba733dSAndre Przywara				pins = "PG6", "PG7";
808e7ba733dSAndre Przywara				function = "uart1";
809e7ba733dSAndre Przywara			};
810e7ba733dSAndre Przywara
81154eac67bSMaxime Ripard			uart1_rts_cts_pins: uart1-rts-cts-pins {
812e7ba733dSAndre Przywara				pins = "PG8", "PG9";
813e7ba733dSAndre Przywara				function = "uart1";
814e7ba733dSAndre Przywara			};
81579825719SAndreas Färber
81679825719SAndreas Färber			uart2_pins: uart2-pins {
81779825719SAndreas Färber				pins = "PB0", "PB1";
81879825719SAndreas Färber				function = "uart2";
81979825719SAndreas Färber			};
8202273aa16SAndreas Färber
8212273aa16SAndreas Färber			uart3_pins: uart3-pins {
8222273aa16SAndreas Färber				pins = "PD0", "PD1";
8232273aa16SAndreas Färber				function = "uart3";
8242273aa16SAndreas Färber			};
8252273aa16SAndreas Färber
8262273aa16SAndreas Färber			uart4_pins: uart4-pins {
8272273aa16SAndreas Färber				pins = "PD2", "PD3";
8282273aa16SAndreas Färber				function = "uart4";
8292273aa16SAndreas Färber			};
8302273aa16SAndreas Färber
8312273aa16SAndreas Färber			uart4_rts_cts_pins: uart4-rts-cts-pins {
8322273aa16SAndreas Färber				pins = "PD4", "PD5";
8332273aa16SAndreas Färber				function = "uart4";
8342273aa16SAndreas Färber			};
8356bc37facSAndre Przywara		};
8366bc37facSAndre Przywara
83712bcaacaSSamuel Holland		timer@1c20c00 {
83812bcaacaSSamuel Holland			compatible = "allwinner,sun50i-a64-timer",
83912bcaacaSSamuel Holland				     "allwinner,sun8i-a23-timer";
84012bcaacaSSamuel Holland			reg = <0x01c20c00 0xa0>;
84112bcaacaSSamuel Holland			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
84212bcaacaSSamuel Holland				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
84312bcaacaSSamuel Holland			clocks = <&osc24M>;
84412bcaacaSSamuel Holland		};
84512bcaacaSSamuel Holland
846af97dd55SSamuel Holland		wdt0: watchdog@1c20ca0 {
847af97dd55SSamuel Holland			compatible = "allwinner,sun50i-a64-wdt",
848af97dd55SSamuel Holland				     "allwinner,sun6i-a31-wdt";
849af97dd55SSamuel Holland			reg = <0x01c20ca0 0x20>;
850af97dd55SSamuel Holland			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
851af97dd55SSamuel Holland			clocks = <&osc24M>;
852af97dd55SSamuel Holland		};
853af97dd55SSamuel Holland
854b399d2acSMarcus Cooper		spdif: spdif@1c21000 {
855b399d2acSMarcus Cooper			#sound-dai-cells = <0>;
856b399d2acSMarcus Cooper			compatible = "allwinner,sun50i-a64-spdif",
857b399d2acSMarcus Cooper				     "allwinner,sun8i-h3-spdif";
858b399d2acSMarcus Cooper			reg = <0x01c21000 0x400>;
859b399d2acSMarcus Cooper			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
860b399d2acSMarcus Cooper			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
861b399d2acSMarcus Cooper			resets = <&ccu RST_BUS_SPDIF>;
862b399d2acSMarcus Cooper			clock-names = "apb", "spdif";
863b399d2acSMarcus Cooper			dmas = <&dma 2>;
864b399d2acSMarcus Cooper			dma-names = "tx";
865b399d2acSMarcus Cooper			pinctrl-names = "default";
866b399d2acSMarcus Cooper			pinctrl-0 = <&spdif_tx_pin>;
867b399d2acSMarcus Cooper			status = "disabled";
868b399d2acSMarcus Cooper		};
869b399d2acSMarcus Cooper
87084204fb6SLuca Weiss		lradc: lradc@1c21800 {
87184204fb6SLuca Weiss			compatible = "allwinner,sun50i-a64-lradc",
87284204fb6SLuca Weiss				     "allwinner,sun8i-a83t-r-lradc";
87384204fb6SLuca Weiss			reg = <0x01c21800 0x400>;
874189bef23SSamuel Holland			interrupt-parent = <&r_intc>;
87584204fb6SLuca Weiss			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
87684204fb6SLuca Weiss			status = "disabled";
87784204fb6SLuca Weiss		};
87884204fb6SLuca Weiss
8791c92c009SMarcus Cooper		i2s0: i2s@1c22000 {
8801c92c009SMarcus Cooper			#sound-dai-cells = <0>;
8811c92c009SMarcus Cooper			compatible = "allwinner,sun50i-a64-i2s",
8821c92c009SMarcus Cooper				     "allwinner,sun8i-h3-i2s";
8831c92c009SMarcus Cooper			reg = <0x01c22000 0x400>;
8841c92c009SMarcus Cooper			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
8851c92c009SMarcus Cooper			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
8861c92c009SMarcus Cooper			clock-names = "apb", "mod";
8871c92c009SMarcus Cooper			resets = <&ccu RST_BUS_I2S0>;
8881c92c009SMarcus Cooper			dma-names = "rx", "tx";
8891c92c009SMarcus Cooper			dmas = <&dma 3>, <&dma 3>;
8901c92c009SMarcus Cooper			status = "disabled";
8911c92c009SMarcus Cooper		};
8921c92c009SMarcus Cooper
8931c92c009SMarcus Cooper		i2s1: i2s@1c22400 {
8941c92c009SMarcus Cooper			#sound-dai-cells = <0>;
8951c92c009SMarcus Cooper			compatible = "allwinner,sun50i-a64-i2s",
8961c92c009SMarcus Cooper				     "allwinner,sun8i-h3-i2s";
8971c92c009SMarcus Cooper			reg = <0x01c22400 0x400>;
8981c92c009SMarcus Cooper			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
8991c92c009SMarcus Cooper			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
9001c92c009SMarcus Cooper			clock-names = "apb", "mod";
9011c92c009SMarcus Cooper			resets = <&ccu RST_BUS_I2S1>;
9021c92c009SMarcus Cooper			dma-names = "rx", "tx";
9031c92c009SMarcus Cooper			dmas = <&dma 4>, <&dma 4>;
9041c92c009SMarcus Cooper			status = "disabled";
9051c92c009SMarcus Cooper		};
9061c92c009SMarcus Cooper
907796c994eSMarcus Cooper		i2s2: i2s@1c22800 {
908796c994eSMarcus Cooper			#sound-dai-cells = <0>;
909796c994eSMarcus Cooper			compatible = "allwinner,sun50i-a64-i2s",
910796c994eSMarcus Cooper				     "allwinner,sun8i-h3-i2s";
911796c994eSMarcus Cooper			reg = <0x01c22800 0x400>;
912796c994eSMarcus Cooper			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
913796c994eSMarcus Cooper			clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
914796c994eSMarcus Cooper			clock-names = "apb", "mod";
915796c994eSMarcus Cooper			resets = <&ccu RST_BUS_I2S2>;
916796c994eSMarcus Cooper			dma-names = "rx", "tx";
917796c994eSMarcus Cooper			dmas = <&dma 27>, <&dma 27>;
918796c994eSMarcus Cooper			status = "disabled";
919796c994eSMarcus Cooper		};
920796c994eSMarcus Cooper
921ec4a9540SVasily Khoruzhick		dai: dai@1c22c00 {
922ec4a9540SVasily Khoruzhick			#sound-dai-cells = <0>;
923ec4a9540SVasily Khoruzhick			compatible = "allwinner,sun50i-a64-codec-i2s";
924ec4a9540SVasily Khoruzhick			reg = <0x01c22c00 0x200>;
925ec4a9540SVasily Khoruzhick			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
926ec4a9540SVasily Khoruzhick			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
927ec4a9540SVasily Khoruzhick			clock-names = "apb", "mod";
928ec4a9540SVasily Khoruzhick			resets = <&ccu RST_BUS_CODEC>;
929ec4a9540SVasily Khoruzhick			dmas = <&dma 15>, <&dma 15>;
930ec4a9540SVasily Khoruzhick			dma-names = "rx", "tx";
931ec4a9540SVasily Khoruzhick			status = "disabled";
932ec4a9540SVasily Khoruzhick		};
933ec4a9540SVasily Khoruzhick
934ec4a9540SVasily Khoruzhick		codec: codec@1c22e00 {
935e0cd8e01SSamuel Holland			#sound-dai-cells = <1>;
936db9c6ad2SSamuel Holland			compatible = "allwinner,sun50i-a64-codec",
937db9c6ad2SSamuel Holland				     "allwinner,sun8i-a33-codec";
938ec4a9540SVasily Khoruzhick			reg = <0x01c22e00 0x600>;
939ec4a9540SVasily Khoruzhick			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
940ec4a9540SVasily Khoruzhick			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
941ec4a9540SVasily Khoruzhick			clock-names = "bus", "mod";
942ec4a9540SVasily Khoruzhick			status = "disabled";
943ec4a9540SVasily Khoruzhick		};
944ec4a9540SVasily Khoruzhick
94559f5e9b9SVasily Khoruzhick		ths: thermal-sensor@1c25000 {
94659f5e9b9SVasily Khoruzhick			compatible = "allwinner,sun50i-a64-ths";
94759f5e9b9SVasily Khoruzhick			reg = <0x01c25000 0x100>;
94859f5e9b9SVasily Khoruzhick			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
94959f5e9b9SVasily Khoruzhick			clock-names = "bus", "mod";
95059f5e9b9SVasily Khoruzhick			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
95159f5e9b9SVasily Khoruzhick			resets = <&ccu RST_BUS_THS>;
95259f5e9b9SVasily Khoruzhick			nvmem-cells = <&ths_calibration>;
95359f5e9b9SVasily Khoruzhick			nvmem-cell-names = "calibration";
95459f5e9b9SVasily Khoruzhick			#thermal-sensor-cells = <1>;
95559f5e9b9SVasily Khoruzhick		};
95659f5e9b9SVasily Khoruzhick
9576bc37facSAndre Przywara		uart0: serial@1c28000 {
9586bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
9596bc37facSAndre Przywara			reg = <0x01c28000 0x400>;
9606bc37facSAndre Przywara			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
9616bc37facSAndre Przywara			reg-shift = <2>;
9626bc37facSAndre Przywara			reg-io-width = <4>;
963494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART0>;
964494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART0>;
9656bc37facSAndre Przywara			status = "disabled";
9666bc37facSAndre Przywara		};
9676bc37facSAndre Przywara
9686bc37facSAndre Przywara		uart1: serial@1c28400 {
9696bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
9706bc37facSAndre Przywara			reg = <0x01c28400 0x400>;
9716bc37facSAndre Przywara			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
9726bc37facSAndre Przywara			reg-shift = <2>;
9736bc37facSAndre Przywara			reg-io-width = <4>;
974494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART1>;
975494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART1>;
9766bc37facSAndre Przywara			status = "disabled";
9776bc37facSAndre Przywara		};
9786bc37facSAndre Przywara
9796bc37facSAndre Przywara		uart2: serial@1c28800 {
9806bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
9816bc37facSAndre Przywara			reg = <0x01c28800 0x400>;
9826bc37facSAndre Przywara			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
9836bc37facSAndre Przywara			reg-shift = <2>;
9846bc37facSAndre Przywara			reg-io-width = <4>;
985494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART2>;
986494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART2>;
9876bc37facSAndre Przywara			status = "disabled";
9886bc37facSAndre Przywara		};
9896bc37facSAndre Przywara
9906bc37facSAndre Przywara		uart3: serial@1c28c00 {
9916bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
9926bc37facSAndre Przywara			reg = <0x01c28c00 0x400>;
9936bc37facSAndre Przywara			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
9946bc37facSAndre Przywara			reg-shift = <2>;
9956bc37facSAndre Przywara			reg-io-width = <4>;
996494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART3>;
997494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART3>;
9986bc37facSAndre Przywara			status = "disabled";
9996bc37facSAndre Przywara		};
10006bc37facSAndre Przywara
10016bc37facSAndre Przywara		uart4: serial@1c29000 {
10026bc37facSAndre Przywara			compatible = "snps,dw-apb-uart";
10036bc37facSAndre Przywara			reg = <0x01c29000 0x400>;
10046bc37facSAndre Przywara			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
10056bc37facSAndre Przywara			reg-shift = <2>;
10066bc37facSAndre Przywara			reg-io-width = <4>;
1007494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_UART4>;
1008494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_UART4>;
10096bc37facSAndre Przywara			status = "disabled";
10106bc37facSAndre Przywara		};
10116bc37facSAndre Przywara
10126bc37facSAndre Przywara		i2c0: i2c@1c2ac00 {
10136bc37facSAndre Przywara			compatible = "allwinner,sun6i-a31-i2c";
10146bc37facSAndre Przywara			reg = <0x01c2ac00 0x400>;
10156bc37facSAndre Przywara			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1016494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_I2C0>;
1017494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_I2C0>;
101870f76289SJagan Teki			pinctrl-names = "default";
101970f76289SJagan Teki			pinctrl-0 = <&i2c0_pins>;
10206bc37facSAndre Przywara			status = "disabled";
10216bc37facSAndre Przywara			#address-cells = <1>;
10226bc37facSAndre Przywara			#size-cells = <0>;
10236bc37facSAndre Przywara		};
10246bc37facSAndre Przywara
10256bc37facSAndre Przywara		i2c1: i2c@1c2b000 {
10266bc37facSAndre Przywara			compatible = "allwinner,sun6i-a31-i2c";
10276bc37facSAndre Przywara			reg = <0x01c2b000 0x400>;
10286bc37facSAndre Przywara			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1029494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_I2C1>;
1030494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_I2C1>;
103170f76289SJagan Teki			pinctrl-names = "default";
103270f76289SJagan Teki			pinctrl-0 = <&i2c1_pins>;
10336bc37facSAndre Przywara			status = "disabled";
10346bc37facSAndre Przywara			#address-cells = <1>;
10356bc37facSAndre Przywara			#size-cells = <0>;
10366bc37facSAndre Przywara		};
10376bc37facSAndre Przywara
10386bc37facSAndre Przywara		i2c2: i2c@1c2b400 {
10396bc37facSAndre Przywara			compatible = "allwinner,sun6i-a31-i2c";
10406bc37facSAndre Przywara			reg = <0x01c2b400 0x400>;
10416bc37facSAndre Przywara			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1042494d8a2cSChen-Yu Tsai			clocks = <&ccu CLK_BUS_I2C2>;
1043494d8a2cSChen-Yu Tsai			resets = <&ccu RST_BUS_I2C2>;
104429b2c68bSOndrej Jirman			pinctrl-names = "default";
104529b2c68bSOndrej Jirman			pinctrl-0 = <&i2c2_pins>;
10466bc37facSAndre Przywara			status = "disabled";
10476bc37facSAndre Przywara			#address-cells = <1>;
10486bc37facSAndre Przywara			#size-cells = <0>;
10496bc37facSAndre Przywara		};
10506bc37facSAndre Przywara
1051d6c9da12SCorentin LABBE		spi0: spi@1c68000 {
1052b518bb15SStefan Brüns			compatible = "allwinner,sun8i-h3-spi";
1053b518bb15SStefan Brüns			reg = <0x01c68000 0x1000>;
1054b518bb15SStefan Brüns			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1055b518bb15SStefan Brüns			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1056b518bb15SStefan Brüns			clock-names = "ahb", "mod";
105706c1258aSStefan Brüns			dmas = <&dma 23>, <&dma 23>;
105806c1258aSStefan Brüns			dma-names = "rx", "tx";
1059b518bb15SStefan Brüns			pinctrl-names = "default";
1060b518bb15SStefan Brüns			pinctrl-0 = <&spi0_pins>;
1061b518bb15SStefan Brüns			resets = <&ccu RST_BUS_SPI0>;
1062b518bb15SStefan Brüns			status = "disabled";
1063b518bb15SStefan Brüns			num-cs = <1>;
1064b518bb15SStefan Brüns			#address-cells = <1>;
1065b518bb15SStefan Brüns			#size-cells = <0>;
1066b518bb15SStefan Brüns		};
1067b518bb15SStefan Brüns
1068d6c9da12SCorentin LABBE		spi1: spi@1c69000 {
1069b518bb15SStefan Brüns			compatible = "allwinner,sun8i-h3-spi";
1070b518bb15SStefan Brüns			reg = <0x01c69000 0x1000>;
1071b518bb15SStefan Brüns			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1072b518bb15SStefan Brüns			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1073b518bb15SStefan Brüns			clock-names = "ahb", "mod";
107406c1258aSStefan Brüns			dmas = <&dma 24>, <&dma 24>;
107506c1258aSStefan Brüns			dma-names = "rx", "tx";
1076b518bb15SStefan Brüns			pinctrl-names = "default";
1077b518bb15SStefan Brüns			pinctrl-0 = <&spi1_pins>;
1078b518bb15SStefan Brüns			resets = <&ccu RST_BUS_SPI1>;
1079b518bb15SStefan Brüns			status = "disabled";
1080b518bb15SStefan Brüns			num-cs = <1>;
1081b518bb15SStefan Brüns			#address-cells = <1>;
1082b518bb15SStefan Brüns			#size-cells = <0>;
1083b518bb15SStefan Brüns		};
1084b518bb15SStefan Brüns
108594f44288SCorentin Labbe		emac: ethernet@1c30000 {
108694f44288SCorentin Labbe			compatible = "allwinner,sun50i-a64-emac";
108794f44288SCorentin Labbe			syscon = <&syscon>;
108894f44288SCorentin Labbe			reg = <0x01c30000 0x10000>;
108994f44288SCorentin Labbe			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
109094f44288SCorentin Labbe			interrupt-names = "macirq";
109194f44288SCorentin Labbe			resets = <&ccu RST_BUS_EMAC>;
109294f44288SCorentin Labbe			reset-names = "stmmaceth";
109394f44288SCorentin Labbe			clocks = <&ccu CLK_BUS_EMAC>;
109494f44288SCorentin Labbe			clock-names = "stmmaceth";
109594f44288SCorentin Labbe			status = "disabled";
109694f44288SCorentin Labbe
109794f44288SCorentin Labbe			mdio: mdio {
109816416084SCorentin Labbe				compatible = "snps,dwmac-mdio";
109994f44288SCorentin Labbe				#address-cells = <1>;
110094f44288SCorentin Labbe				#size-cells = <0>;
110194f44288SCorentin Labbe			};
110294f44288SCorentin Labbe		};
110394f44288SCorentin Labbe
11046b683d76SJagan Teki		mali: gpu@1c40000 {
11056b683d76SJagan Teki			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
11066b683d76SJagan Teki			reg = <0x01c40000 0x10000>;
11076b683d76SJagan Teki			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
11086b683d76SJagan Teki				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
11096b683d76SJagan Teki				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
11106b683d76SJagan Teki				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
11116b683d76SJagan Teki				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
11126b683d76SJagan Teki				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
11136b683d76SJagan Teki				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
11146b683d76SJagan Teki			interrupt-names = "gp",
11156b683d76SJagan Teki					  "gpmmu",
11166b683d76SJagan Teki					  "pp0",
11176b683d76SJagan Teki					  "ppmmu0",
11186b683d76SJagan Teki					  "pp1",
11196b683d76SJagan Teki					  "ppmmu1",
11206b683d76SJagan Teki					  "pmu";
11216b683d76SJagan Teki			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
11226b683d76SJagan Teki			clock-names = "bus", "core";
11236b683d76SJagan Teki			resets = <&ccu RST_BUS_GPU>;
1124e954a7afSJernej Skrabec			operating-points-v2 = <&gpu_opp_table>;
11256b683d76SJagan Teki		};
11266b683d76SJagan Teki
11276bc37facSAndre Przywara		gic: interrupt-controller@1c81000 {
11286bc37facSAndre Przywara			compatible = "arm,gic-400";
11296bc37facSAndre Przywara			reg = <0x01c81000 0x1000>,
11306bc37facSAndre Przywara			      <0x01c82000 0x2000>,
11316bc37facSAndre Przywara			      <0x01c84000 0x2000>,
11326bc37facSAndre Przywara			      <0x01c86000 0x2000>;
11336bc37facSAndre Przywara			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
11346bc37facSAndre Przywara			interrupt-controller;
11356bc37facSAndre Przywara			#interrupt-cells = <3>;
11366bc37facSAndre Przywara		};
11376bc37facSAndre Przywara
1138b5df280bSAndre Przywara		pwm: pwm@1c21400 {
1139b5df280bSAndre Przywara			compatible = "allwinner,sun50i-a64-pwm",
1140b5df280bSAndre Przywara				     "allwinner,sun5i-a13-pwm";
1141b5df280bSAndre Przywara			reg = <0x01c21400 0x400>;
1142b5df280bSAndre Przywara			clocks = <&osc24M>;
1143b5df280bSAndre Przywara			pinctrl-names = "default";
1144b5df280bSAndre Przywara			pinctrl-0 = <&pwm_pin>;
1145b5df280bSAndre Przywara			#pwm-cells = <3>;
1146b5df280bSAndre Przywara			status = "disabled";
1147b5df280bSAndre Przywara		};
1148b5df280bSAndre Przywara
1149fc7c2bfbSJernej Skrabec		mbus: dram-controller@1c62000 {
1150fc7c2bfbSJernej Skrabec			compatible = "allwinner,sun50i-a64-mbus";
115100b9773bSSamuel Holland			reg = <0x01c62000 0x1000>,
115200b9773bSSamuel Holland			      <0x01c63000 0x1000>;
115300b9773bSSamuel Holland			reg-names = "mbus", "dram";
115400b9773bSSamuel Holland			clocks = <&ccu CLK_MBUS>,
115500b9773bSSamuel Holland				 <&ccu CLK_DRAM>,
115600b9773bSSamuel Holland				 <&ccu CLK_BUS_DRAM>;
115700b9773bSSamuel Holland			clock-names = "mbus", "dram", "bus";
115800b9773bSSamuel Holland			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1159cff11101SOndrej Jirman			#address-cells = <1>;
1160cff11101SOndrej Jirman			#size-cells = <1>;
1161fc7c2bfbSJernej Skrabec			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1162fc7c2bfbSJernej Skrabec			#interconnect-cells = <1>;
1163fc7c2bfbSJernej Skrabec		};
1164fc7c2bfbSJernej Skrabec
1165ff29f13eSJagan Teki		csi: csi@1cb0000 {
1166ff29f13eSJagan Teki			compatible = "allwinner,sun50i-a64-csi";
1167ff29f13eSJagan Teki			reg = <0x01cb0000 0x1000>;
1168ff29f13eSJagan Teki			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1169ff29f13eSJagan Teki			clocks = <&ccu CLK_BUS_CSI>,
1170ff29f13eSJagan Teki				 <&ccu CLK_CSI_SCLK>,
1171ff29f13eSJagan Teki				 <&ccu CLK_DRAM_CSI>;
1172ff29f13eSJagan Teki			clock-names = "bus", "mod", "ram";
1173ff29f13eSJagan Teki			resets = <&ccu RST_BUS_CSI>;
1174ff29f13eSJagan Teki			pinctrl-names = "default";
1175ff29f13eSJagan Teki			pinctrl-0 = <&csi_pins>;
1176ff29f13eSJagan Teki			status = "disabled";
1177ff29f13eSJagan Teki		};
1178ff29f13eSJagan Teki
117916c8ff57SJagan Teki		dsi: dsi@1ca0000 {
118016c8ff57SJagan Teki			compatible = "allwinner,sun50i-a64-mipi-dsi";
118116c8ff57SJagan Teki			reg = <0x01ca0000 0x1000>;
118216c8ff57SJagan Teki			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
118316c8ff57SJagan Teki			clocks = <&ccu CLK_BUS_MIPI_DSI>;
118416c8ff57SJagan Teki			resets = <&ccu RST_BUS_MIPI_DSI>;
118516c8ff57SJagan Teki			phys = <&dphy>;
118616c8ff57SJagan Teki			phy-names = "dphy";
118716c8ff57SJagan Teki			status = "disabled";
118816c8ff57SJagan Teki			#address-cells = <1>;
118916c8ff57SJagan Teki			#size-cells = <0>;
119016c8ff57SJagan Teki
119116c8ff57SJagan Teki			port {
119216c8ff57SJagan Teki				dsi_in_tcon0: endpoint {
119316c8ff57SJagan Teki					remote-endpoint = <&tcon0_out_dsi>;
119416c8ff57SJagan Teki				};
119516c8ff57SJagan Teki			};
119616c8ff57SJagan Teki		};
119716c8ff57SJagan Teki
119816c8ff57SJagan Teki		dphy: d-phy@1ca1000 {
119916c8ff57SJagan Teki			compatible = "allwinner,sun50i-a64-mipi-dphy",
120016c8ff57SJagan Teki				     "allwinner,sun6i-a31-mipi-dphy";
120116c8ff57SJagan Teki			reg = <0x01ca1000 0x1000>;
1202*862ee64bSSamuel Holland			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
120316c8ff57SJagan Teki			clocks = <&ccu CLK_BUS_MIPI_DSI>,
120416c8ff57SJagan Teki				 <&ccu CLK_DSI_DPHY>;
120516c8ff57SJagan Teki			clock-names = "bus", "mod";
120616c8ff57SJagan Teki			resets = <&ccu RST_BUS_MIPI_DSI>;
120716c8ff57SJagan Teki			status = "disabled";
120816c8ff57SJagan Teki			#phy-cells = <0>;
120916c8ff57SJagan Teki		};
121016c8ff57SJagan Teki
1211dd00d78dSJernej Skrabec		deinterlace: deinterlace@1e00000 {
1212dd00d78dSJernej Skrabec			compatible = "allwinner,sun50i-a64-deinterlace",
1213dd00d78dSJernej Skrabec				     "allwinner,sun8i-h3-deinterlace";
1214dd00d78dSJernej Skrabec			reg = <0x01e00000 0x20000>;
1215dd00d78dSJernej Skrabec			clocks = <&ccu CLK_BUS_DEINTERLACE>,
1216dd00d78dSJernej Skrabec				 <&ccu CLK_DEINTERLACE>,
1217dd00d78dSJernej Skrabec				 <&ccu CLK_DRAM_DEINTERLACE>;
1218dd00d78dSJernej Skrabec			clock-names = "bus", "mod", "ram";
1219dd00d78dSJernej Skrabec			resets = <&ccu RST_BUS_DEINTERLACE>;
1220dd00d78dSJernej Skrabec			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1221dd00d78dSJernej Skrabec			interconnects = <&mbus 9>;
1222dd00d78dSJernej Skrabec			interconnect-names = "dma-mem";
1223dd00d78dSJernej Skrabec		};
1224dd00d78dSJernej Skrabec
1225e85f28e0SJagan Teki		hdmi: hdmi@1ee0000 {
1226e85f28e0SJagan Teki			compatible = "allwinner,sun50i-a64-dw-hdmi",
1227e85f28e0SJagan Teki				     "allwinner,sun8i-a83t-dw-hdmi";
1228e85f28e0SJagan Teki			reg = <0x01ee0000 0x10000>;
1229e85f28e0SJagan Teki			reg-io-width = <1>;
1230e85f28e0SJagan Teki			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1231e85f28e0SJagan Teki			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
12321b9dac68SSamuel Holland				 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
12333047444dSJernej Skrabec			clock-names = "iahb", "isfr", "tmds", "cec";
1234e85f28e0SJagan Teki			resets = <&ccu RST_BUS_HDMI1>;
1235e85f28e0SJagan Teki			reset-names = "ctrl";
1236e85f28e0SJagan Teki			phys = <&hdmi_phy>;
1237d40113fbSMaxime Ripard			phy-names = "phy";
1238e85f28e0SJagan Teki			status = "disabled";
1239e85f28e0SJagan Teki
1240e85f28e0SJagan Teki			ports {
1241e85f28e0SJagan Teki				#address-cells = <1>;
1242e85f28e0SJagan Teki				#size-cells = <0>;
1243e85f28e0SJagan Teki
1244e85f28e0SJagan Teki				hdmi_in: port@0 {
1245e85f28e0SJagan Teki					reg = <0>;
1246e85f28e0SJagan Teki
1247e85f28e0SJagan Teki					hdmi_in_tcon1: endpoint {
1248e85f28e0SJagan Teki						remote-endpoint = <&tcon1_out_hdmi>;
1249e85f28e0SJagan Teki					};
1250e85f28e0SJagan Teki				};
1251e85f28e0SJagan Teki
1252e85f28e0SJagan Teki				hdmi_out: port@1 {
1253e85f28e0SJagan Teki					reg = <1>;
1254e85f28e0SJagan Teki				};
1255e85f28e0SJagan Teki			};
1256e85f28e0SJagan Teki		};
1257e85f28e0SJagan Teki
1258e85f28e0SJagan Teki		hdmi_phy: hdmi-phy@1ef0000 {
1259e85f28e0SJagan Teki			compatible = "allwinner,sun50i-a64-hdmi-phy";
1260e85f28e0SJagan Teki			reg = <0x01ef0000 0x10000>;
1261e85f28e0SJagan Teki			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1262b71818cbSChen-Yu Tsai				 <&ccu CLK_PLL_VIDEO0>;
1263e85f28e0SJagan Teki			clock-names = "bus", "mod", "pll-0";
1264e85f28e0SJagan Teki			resets = <&ccu RST_BUS_HDMI0>;
1265e85f28e0SJagan Teki			reset-names = "phy";
1266e85f28e0SJagan Teki			#phy-cells = <0>;
1267e85f28e0SJagan Teki		};
1268e85f28e0SJagan Teki
12696bc37facSAndre Przywara		rtc: rtc@1f00000 {
127044ff3cafSChen-Yu Tsai			compatible = "allwinner,sun50i-a64-rtc",
127144ff3cafSChen-Yu Tsai				     "allwinner,sun8i-h3-rtc";
127244ff3cafSChen-Yu Tsai			reg = <0x01f00000 0x400>;
1273189bef23SSamuel Holland			interrupt-parent = <&r_intc>;
12746bc37facSAndre Przywara			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
12756bc37facSAndre Przywara				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
127644ff3cafSChen-Yu Tsai			clock-output-names = "osc32k", "osc32k-out", "iosc";
1277e1a9a474SJagan Teki			clocks = <&osc32k>;
1278e1a9a474SJagan Teki			#clock-cells = <1>;
12796bc37facSAndre Przywara		};
1280791a9e00SIcenowy Zheng
1281535ca508SIcenowy Zheng		r_intc: interrupt-controller@1f00c00 {
1282535ca508SIcenowy Zheng			compatible = "allwinner,sun50i-a64-r-intc",
1283535ca508SIcenowy Zheng				     "allwinner,sun6i-a31-r-intc";
1284535ca508SIcenowy Zheng			interrupt-controller;
128573088dfeSSamuel Holland			#interrupt-cells = <3>;
1286535ca508SIcenowy Zheng			reg = <0x01f00c00 0x400>;
1287535ca508SIcenowy Zheng			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1288535ca508SIcenowy Zheng		};
1289535ca508SIcenowy Zheng
1290791a9e00SIcenowy Zheng		r_ccu: clock@1f01400 {
1291791a9e00SIcenowy Zheng			compatible = "allwinner,sun50i-a64-r-ccu";
1292791a9e00SIcenowy Zheng			reg = <0x01f01400 0x100>;
12931b9dac68SSamuel Holland			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
1294b71818cbSChen-Yu Tsai				 <&ccu CLK_PLL_PERIPH0>;
1295f74994a9SChen-Yu Tsai			clock-names = "hosc", "losc", "iosc", "pll-periph";
1296791a9e00SIcenowy Zheng			#clock-cells = <1>;
1297791a9e00SIcenowy Zheng			#reset-cells = <1>;
1298791a9e00SIcenowy Zheng		};
1299ec427905SIcenowy Zheng
1300ec4a9540SVasily Khoruzhick		codec_analog: codec-analog@1f015c0 {
1301ec4a9540SVasily Khoruzhick			compatible = "allwinner,sun50i-a64-codec-analog";
1302ec4a9540SVasily Khoruzhick			reg = <0x01f015c0 0x4>;
1303ec4a9540SVasily Khoruzhick			status = "disabled";
1304ec4a9540SVasily Khoruzhick		};
1305ec4a9540SVasily Khoruzhick
1306871b5352SIcenowy Zheng		r_i2c: i2c@1f02400 {
1307871b5352SIcenowy Zheng			compatible = "allwinner,sun50i-a64-i2c",
1308871b5352SIcenowy Zheng				     "allwinner,sun6i-a31-i2c";
1309871b5352SIcenowy Zheng			reg = <0x01f02400 0x400>;
1310871b5352SIcenowy Zheng			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1311871b5352SIcenowy Zheng			clocks = <&r_ccu CLK_APB0_I2C>;
1312871b5352SIcenowy Zheng			resets = <&r_ccu RST_APB0_I2C>;
1313871b5352SIcenowy Zheng			status = "disabled";
1314871b5352SIcenowy Zheng			#address-cells = <1>;
1315871b5352SIcenowy Zheng			#size-cells = <0>;
1316871b5352SIcenowy Zheng		};
1317871b5352SIcenowy Zheng
131844a4f416SIgors Makejevs		r_ir: ir@1f02000 {
131944a4f416SIgors Makejevs			compatible = "allwinner,sun50i-a64-ir",
132044a4f416SIgors Makejevs				     "allwinner,sun6i-a31-ir";
132144a4f416SIgors Makejevs			reg = <0x01f02000 0x400>;
132244a4f416SIgors Makejevs			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
132344a4f416SIgors Makejevs			clock-names = "apb", "ir";
132444a4f416SIgors Makejevs			resets = <&r_ccu RST_APB0_IR>;
132544a4f416SIgors Makejevs			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
132644a4f416SIgors Makejevs			pinctrl-names = "default";
132744a4f416SIgors Makejevs			pinctrl-0 = <&r_ir_rx_pin>;
132844a4f416SIgors Makejevs			status = "disabled";
132944a4f416SIgors Makejevs		};
133044a4f416SIgors Makejevs
1331b5df280bSAndre Przywara		r_pwm: pwm@1f03800 {
1332b5df280bSAndre Przywara			compatible = "allwinner,sun50i-a64-pwm",
1333b5df280bSAndre Przywara				     "allwinner,sun5i-a13-pwm";
1334b5df280bSAndre Przywara			reg = <0x01f03800 0x400>;
1335b5df280bSAndre Przywara			clocks = <&osc24M>;
1336b5df280bSAndre Przywara			pinctrl-names = "default";
1337b5df280bSAndre Przywara			pinctrl-0 = <&r_pwm_pin>;
1338b5df280bSAndre Przywara			#pwm-cells = <3>;
1339b5df280bSAndre Przywara			status = "disabled";
1340b5df280bSAndre Przywara		};
1341b5df280bSAndre Przywara
1342d6c9da12SCorentin LABBE		r_pio: pinctrl@1f02c00 {
1343ec427905SIcenowy Zheng			compatible = "allwinner,sun50i-a64-r-pinctrl";
1344ec427905SIcenowy Zheng			reg = <0x01f02c00 0x400>;
1345189bef23SSamuel Holland			interrupt-parent = <&r_intc>;
1346ec427905SIcenowy Zheng			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1347494d8a2cSChen-Yu Tsai			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1348ec427905SIcenowy Zheng			clock-names = "apb", "hosc", "losc";
1349ec427905SIcenowy Zheng			gpio-controller;
1350ec427905SIcenowy Zheng			#gpio-cells = <3>;
1351ec427905SIcenowy Zheng			interrupt-controller;
1352ec427905SIcenowy Zheng			#interrupt-cells = <3>;
13533b38fdedSIcenowy Zheng
13541b6ff1cbSChen-Yu Tsai			r_i2c_pl89_pins: r-i2c-pl89-pins {
1355871b5352SIcenowy Zheng				pins = "PL8", "PL9";
1356871b5352SIcenowy Zheng				function = "s_i2c";
1357871b5352SIcenowy Zheng			};
1358871b5352SIcenowy Zheng
135944a4f416SIgors Makejevs			r_ir_rx_pin: r-ir-rx-pin {
136044a4f416SIgors Makejevs				pins = "PL11";
136144a4f416SIgors Makejevs				function = "s_cir_rx";
136244a4f416SIgors Makejevs			};
136344a4f416SIgors Makejevs
136454eac67bSMaxime Ripard			r_pwm_pin: r-pwm-pin {
1365b5df280bSAndre Przywara				pins = "PL10";
1366b5df280bSAndre Przywara				function = "s_pwm";
1367b5df280bSAndre Przywara			};
1368b5df280bSAndre Przywara
136954eac67bSMaxime Ripard			r_rsb_pins: r-rsb-pins {
13703b38fdedSIcenowy Zheng				pins = "PL0", "PL1";
13713b38fdedSIcenowy Zheng				function = "s_rsb";
13723b38fdedSIcenowy Zheng			};
13733b38fdedSIcenowy Zheng		};
13743b38fdedSIcenowy Zheng
13753b38fdedSIcenowy Zheng		r_rsb: rsb@1f03400 {
13763b38fdedSIcenowy Zheng			compatible = "allwinner,sun8i-a23-rsb";
13773b38fdedSIcenowy Zheng			reg = <0x01f03400 0x400>;
13783b38fdedSIcenowy Zheng			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
13793b38fdedSIcenowy Zheng			clocks = <&r_ccu 6>;
13803b38fdedSIcenowy Zheng			clock-frequency = <3000000>;
13813b38fdedSIcenowy Zheng			resets = <&r_ccu 2>;
13823b38fdedSIcenowy Zheng			pinctrl-names = "default";
13833b38fdedSIcenowy Zheng			pinctrl-0 = <&r_rsb_pins>;
13843b38fdedSIcenowy Zheng			status = "disabled";
13853b38fdedSIcenowy Zheng			#address-cells = <1>;
13863b38fdedSIcenowy Zheng			#size-cells = <0>;
1387ec427905SIcenowy Zheng		};
13886bc37facSAndre Przywara	};
13896bc37facSAndre Przywara};
1390