1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd. 3cabbaed7SClément Péron// based on the Allwinner H3 dtsi: 4cabbaed7SClément Péron// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara 6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 72c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 8494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 96bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 10a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 112c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 12871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 1359f5e9b9SVasily Khoruzhick#include <dt-bindings/thermal/thermal.h> 146bc37facSAndre Przywara 156bc37facSAndre Przywara/ { 166bc37facSAndre Przywara interrupt-parent = <&gic>; 176bc37facSAndre Przywara #address-cells = <1>; 186bc37facSAndre Przywara #size-cells = <1>; 196bc37facSAndre Przywara 20c1cff65fSHarald Geyer chosen { 21c1cff65fSHarald Geyer #address-cells = <1>; 22c1cff65fSHarald Geyer #size-cells = <1>; 23c1cff65fSHarald Geyer ranges; 24c1cff65fSHarald Geyer 25c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 26c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 27c1cff65fSHarald Geyer "simple-framebuffer"; 28c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 29c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 302c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 31c1cff65fSHarald Geyer status = "disabled"; 32c1cff65fSHarald Geyer }; 33fca63f58SIcenowy Zheng 34fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 35fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 36fca63f58SIcenowy Zheng "simple-framebuffer"; 37fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 38fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 39fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40fca63f58SIcenowy Zheng status = "disabled"; 41fca63f58SIcenowy Zheng }; 42c1cff65fSHarald Geyer }; 43c1cff65fSHarald Geyer 446bc37facSAndre Przywara cpus { 456bc37facSAndre Przywara #address-cells = <1>; 466bc37facSAndre Przywara #size-cells = <0>; 476bc37facSAndre Przywara 486bc37facSAndre Przywara cpu0: cpu@0 { 4931af04cdSRob Herring compatible = "arm,cortex-a53"; 506bc37facSAndre Przywara device_type = "cpu"; 516bc37facSAndre Przywara reg = <0>; 526bc37facSAndre Przywara enable-method = "psci"; 5339defc81SAndre Przywara next-level-cache = <&L2>; 547db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 55f267eff7SVasily Khoruzhick clock-names = "cpu"; 56e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 576bc37facSAndre Przywara }; 586bc37facSAndre Przywara 596bc37facSAndre Przywara cpu1: cpu@1 { 6031af04cdSRob Herring compatible = "arm,cortex-a53"; 616bc37facSAndre Przywara device_type = "cpu"; 626bc37facSAndre Przywara reg = <1>; 636bc37facSAndre Przywara enable-method = "psci"; 6439defc81SAndre Przywara next-level-cache = <&L2>; 657db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 66f267eff7SVasily Khoruzhick clock-names = "cpu"; 67e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 686bc37facSAndre Przywara }; 696bc37facSAndre Przywara 706bc37facSAndre Przywara cpu2: cpu@2 { 7131af04cdSRob Herring compatible = "arm,cortex-a53"; 726bc37facSAndre Przywara device_type = "cpu"; 736bc37facSAndre Przywara reg = <2>; 746bc37facSAndre Przywara enable-method = "psci"; 7539defc81SAndre Przywara next-level-cache = <&L2>; 767db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 77f267eff7SVasily Khoruzhick clock-names = "cpu"; 78e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 796bc37facSAndre Przywara }; 806bc37facSAndre Przywara 816bc37facSAndre Przywara cpu3: cpu@3 { 8231af04cdSRob Herring compatible = "arm,cortex-a53"; 836bc37facSAndre Przywara device_type = "cpu"; 846bc37facSAndre Przywara reg = <3>; 856bc37facSAndre Przywara enable-method = "psci"; 8639defc81SAndre Przywara next-level-cache = <&L2>; 877db1aa6fSAlexander Kochetkov clocks = <&ccu CLK_CPUX>; 88f267eff7SVasily Khoruzhick clock-names = "cpu"; 89e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 9039defc81SAndre Przywara }; 9139defc81SAndre Przywara 9239defc81SAndre Przywara L2: l2-cache { 9339defc81SAndre Przywara compatible = "cache"; 9439defc81SAndre Przywara cache-level = <2>; 956bc37facSAndre Przywara }; 966bc37facSAndre Przywara }; 976bc37facSAndre Przywara 98e85f28e0SJagan Teki de: display-engine { 99e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 100e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 101e85f28e0SJagan Teki <&mixer1>; 102e85f28e0SJagan Teki status = "disabled"; 103e85f28e0SJagan Teki }; 104e85f28e0SJagan Teki 1056bc37facSAndre Przywara osc24M: osc24M_clk { 1066bc37facSAndre Przywara #clock-cells = <0>; 1076bc37facSAndre Przywara compatible = "fixed-clock"; 1086bc37facSAndre Przywara clock-frequency = <24000000>; 1096bc37facSAndre Przywara clock-output-names = "osc24M"; 1106bc37facSAndre Przywara }; 1116bc37facSAndre Przywara 1126bc37facSAndre Przywara osc32k: osc32k_clk { 1136bc37facSAndre Przywara #clock-cells = <0>; 1146bc37facSAndre Przywara compatible = "fixed-clock"; 1156bc37facSAndre Przywara clock-frequency = <32768>; 11644ff3cafSChen-Yu Tsai clock-output-names = "ext-osc32k"; 117791a9e00SIcenowy Zheng }; 118791a9e00SIcenowy Zheng 11934a97fccSHarald Geyer pmu { 12034a97fccSHarald Geyer compatible = "arm,cortex-a53-pmu"; 1216b832a14SAndre Przywara interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1226b832a14SAndre Przywara <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1236b832a14SAndre Przywara <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1246b832a14SAndre Przywara <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 12534a97fccSHarald Geyer interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 12634a97fccSHarald Geyer }; 12734a97fccSHarald Geyer 1286bc37facSAndre Przywara psci { 1296bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1306bc37facSAndre Przywara method = "smc"; 1316bc37facSAndre Przywara }; 1326bc37facSAndre Przywara 133ec4a9540SVasily Khoruzhick sound: sound { 134ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 135ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 136ec4a9540SVasily Khoruzhick simple-audio-card,format = "i2s"; 137ec4a9540SVasily Khoruzhick simple-audio-card,frame-master = <&cpudai>; 138ec4a9540SVasily Khoruzhick simple-audio-card,bitclock-master = <&cpudai>; 139ec4a9540SVasily Khoruzhick simple-audio-card,mclk-fs = <128>; 140ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 141ec4a9540SVasily Khoruzhick simple-audio-card,routing = 142ec4a9540SVasily Khoruzhick "Left DAC", "AIF1 Slot 0 Left", 143ec4a9540SVasily Khoruzhick "Right DAC", "AIF1 Slot 0 Right", 144ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Left ADC", "Left ADC", 145ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Right ADC", "Right ADC"; 146ec4a9540SVasily Khoruzhick status = "disabled"; 147ec4a9540SVasily Khoruzhick 148ec4a9540SVasily Khoruzhick cpudai: simple-audio-card,cpu { 149ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 150ec4a9540SVasily Khoruzhick }; 151ec4a9540SVasily Khoruzhick 152ec4a9540SVasily Khoruzhick link_codec: simple-audio-card,codec { 153ec4a9540SVasily Khoruzhick sound-dai = <&codec>; 154ec4a9540SVasily Khoruzhick }; 155ec4a9540SVasily Khoruzhick }; 156ec4a9540SVasily Khoruzhick 1576bc37facSAndre Przywara timer { 1586bc37facSAndre Przywara compatible = "arm,armv8-timer"; 15955ec26d6SSamuel Holland allwinner,erratum-unknown1; 1606bc37facSAndre Przywara interrupts = <GIC_PPI 13 1616bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1626bc37facSAndre Przywara <GIC_PPI 14 1636bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1646bc37facSAndre Przywara <GIC_PPI 11 1656bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1666bc37facSAndre Przywara <GIC_PPI 10 1676bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1686bc37facSAndre Przywara }; 1696bc37facSAndre Przywara 17059f5e9b9SVasily Khoruzhick thermal-zones { 17159f5e9b9SVasily Khoruzhick cpu_thermal: cpu0-thermal { 17259f5e9b9SVasily Khoruzhick /* milliseconds */ 17359f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 17459f5e9b9SVasily Khoruzhick polling-delay = <0>; 17559f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 0>; 176e1c3804aSVasily Khoruzhick 177e1c3804aSVasily Khoruzhick cooling-maps { 178e1c3804aSVasily Khoruzhick map0 { 179e1c3804aSVasily Khoruzhick trip = <&cpu_alert0>; 180e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 181e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 182e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 183e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 184e1c3804aSVasily Khoruzhick }; 185e1c3804aSVasily Khoruzhick map1 { 186e1c3804aSVasily Khoruzhick trip = <&cpu_alert1>; 187e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 188e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 189e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 190e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 191e1c3804aSVasily Khoruzhick }; 192e1c3804aSVasily Khoruzhick }; 193e1c3804aSVasily Khoruzhick 194e1c3804aSVasily Khoruzhick trips { 195e1c3804aSVasily Khoruzhick cpu_alert0: cpu_alert0 { 196e1c3804aSVasily Khoruzhick /* milliCelsius */ 197e1c3804aSVasily Khoruzhick temperature = <75000>; 198e1c3804aSVasily Khoruzhick hysteresis = <2000>; 199e1c3804aSVasily Khoruzhick type = "passive"; 200e1c3804aSVasily Khoruzhick }; 201e1c3804aSVasily Khoruzhick 202e1c3804aSVasily Khoruzhick cpu_alert1: cpu_alert1 { 203e1c3804aSVasily Khoruzhick /* milliCelsius */ 204e1c3804aSVasily Khoruzhick temperature = <90000>; 205e1c3804aSVasily Khoruzhick hysteresis = <2000>; 206e1c3804aSVasily Khoruzhick type = "hot"; 207e1c3804aSVasily Khoruzhick }; 208e1c3804aSVasily Khoruzhick 209e1c3804aSVasily Khoruzhick cpu_crit: cpu_crit { 210e1c3804aSVasily Khoruzhick /* milliCelsius */ 211e1c3804aSVasily Khoruzhick temperature = <110000>; 212e1c3804aSVasily Khoruzhick hysteresis = <2000>; 213e1c3804aSVasily Khoruzhick type = "critical"; 214e1c3804aSVasily Khoruzhick }; 215e1c3804aSVasily Khoruzhick }; 21659f5e9b9SVasily Khoruzhick }; 21759f5e9b9SVasily Khoruzhick 21859f5e9b9SVasily Khoruzhick gpu0_thermal: gpu0-thermal { 21959f5e9b9SVasily Khoruzhick /* milliseconds */ 22059f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 22159f5e9b9SVasily Khoruzhick polling-delay = <0>; 22259f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 1>; 22359f5e9b9SVasily Khoruzhick }; 22459f5e9b9SVasily Khoruzhick 22559f5e9b9SVasily Khoruzhick gpu1_thermal: gpu1-thermal { 22659f5e9b9SVasily Khoruzhick /* milliseconds */ 22759f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 22859f5e9b9SVasily Khoruzhick polling-delay = <0>; 22959f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 2>; 23059f5e9b9SVasily Khoruzhick }; 23159f5e9b9SVasily Khoruzhick }; 23259f5e9b9SVasily Khoruzhick 2336bc37facSAndre Przywara soc { 2346bc37facSAndre Przywara compatible = "simple-bus"; 2356bc37facSAndre Przywara #address-cells = <1>; 2366bc37facSAndre Przywara #size-cells = <1>; 2376bc37facSAndre Przywara ranges; 2386bc37facSAndre Przywara 239275b6317SMaxime Ripard bus@1000000 { 2402c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 2412c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 2422c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 2432c796fc8SIcenowy Zheng #address-cells = <1>; 2442c796fc8SIcenowy Zheng #size-cells = <1>; 2452c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 2462c796fc8SIcenowy Zheng 2472c796fc8SIcenowy Zheng display_clocks: clock@0 { 2482c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 2493e9a1a8bSJernej Skrabec reg = <0x0 0x10000>; 2505ea40f71SMaxime Ripard clocks = <&ccu CLK_BUS_DE>, 2515ea40f71SMaxime Ripard <&ccu CLK_DE>; 2525ea40f71SMaxime Ripard clock-names = "bus", 2535ea40f71SMaxime Ripard "mod"; 2542c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 2552c796fc8SIcenowy Zheng #clock-cells = <1>; 2562c796fc8SIcenowy Zheng #reset-cells = <1>; 2572c796fc8SIcenowy Zheng }; 258e85f28e0SJagan Teki 259048cdfceSJernej Skrabec rotate: rotate@20000 { 260048cdfceSJernej Skrabec compatible = "allwinner,sun50i-a64-de2-rotate", 261048cdfceSJernej Skrabec "allwinner,sun8i-a83t-de2-rotate"; 262048cdfceSJernej Skrabec reg = <0x20000 0x10000>; 263048cdfceSJernej Skrabec interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 264048cdfceSJernej Skrabec clocks = <&display_clocks CLK_BUS_ROT>, 265048cdfceSJernej Skrabec <&display_clocks CLK_ROT>; 266048cdfceSJernej Skrabec clock-names = "bus", 267048cdfceSJernej Skrabec "mod"; 268048cdfceSJernej Skrabec resets = <&display_clocks RST_ROT>; 269048cdfceSJernej Skrabec }; 270048cdfceSJernej Skrabec 271e85f28e0SJagan Teki mixer0: mixer@100000 { 272e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 273e85f28e0SJagan Teki reg = <0x100000 0x100000>; 274e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 275e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 276e85f28e0SJagan Teki clock-names = "bus", 277e85f28e0SJagan Teki "mod"; 278e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 279e85f28e0SJagan Teki 280e85f28e0SJagan Teki ports { 281e85f28e0SJagan Teki #address-cells = <1>; 282e85f28e0SJagan Teki #size-cells = <0>; 283e85f28e0SJagan Teki 284e85f28e0SJagan Teki mixer0_out: port@1 { 285a7f7047fSMaxime Ripard #address-cells = <1>; 286a7f7047fSMaxime Ripard #size-cells = <0>; 287e85f28e0SJagan Teki reg = <1>; 288e85f28e0SJagan Teki 289a7f7047fSMaxime Ripard mixer0_out_tcon0: endpoint@0 { 290a7f7047fSMaxime Ripard reg = <0>; 291e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 292e85f28e0SJagan Teki }; 293a7f7047fSMaxime Ripard 294a7f7047fSMaxime Ripard mixer0_out_tcon1: endpoint@1 { 295a7f7047fSMaxime Ripard reg = <1>; 296a7f7047fSMaxime Ripard remote-endpoint = <&tcon1_in_mixer0>; 297a7f7047fSMaxime Ripard }; 298e85f28e0SJagan Teki }; 299e85f28e0SJagan Teki }; 300e85f28e0SJagan Teki }; 301e85f28e0SJagan Teki 302e85f28e0SJagan Teki mixer1: mixer@200000 { 303e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 304e85f28e0SJagan Teki reg = <0x200000 0x100000>; 305e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 306e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 307e85f28e0SJagan Teki clock-names = "bus", 308e85f28e0SJagan Teki "mod"; 309e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 310e85f28e0SJagan Teki 311e85f28e0SJagan Teki ports { 312e85f28e0SJagan Teki #address-cells = <1>; 313e85f28e0SJagan Teki #size-cells = <0>; 314e85f28e0SJagan Teki 315e85f28e0SJagan Teki mixer1_out: port@1 { 316d41a43a0SMaxime Ripard #address-cells = <1>; 317d41a43a0SMaxime Ripard #size-cells = <0>; 318e85f28e0SJagan Teki reg = <1>; 319e85f28e0SJagan Teki 320a7f7047fSMaxime Ripard mixer1_out_tcon0: endpoint@0 { 321a7f7047fSMaxime Ripard reg = <0>; 322a7f7047fSMaxime Ripard remote-endpoint = <&tcon0_in_mixer1>; 323a7f7047fSMaxime Ripard }; 324a7f7047fSMaxime Ripard 325a7f7047fSMaxime Ripard mixer1_out_tcon1: endpoint@1 { 326a7f7047fSMaxime Ripard reg = <1>; 327e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 328e85f28e0SJagan Teki }; 329e85f28e0SJagan Teki }; 330e85f28e0SJagan Teki }; 331e85f28e0SJagan Teki }; 3322c796fc8SIcenowy Zheng }; 3332c796fc8SIcenowy Zheng 33479b95360SCorentin Labbe syscon: syscon@1c00000 { 3351f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 33679b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 3371f1f5183SIcenowy Zheng #address-cells = <1>; 3381f1f5183SIcenowy Zheng #size-cells = <1>; 3391f1f5183SIcenowy Zheng ranges; 3401f1f5183SIcenowy Zheng 3411f1f5183SIcenowy Zheng sram_c: sram@18000 { 3421f1f5183SIcenowy Zheng compatible = "mmio-sram"; 3431f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 3441f1f5183SIcenowy Zheng #address-cells = <1>; 3451f1f5183SIcenowy Zheng #size-cells = <1>; 3461f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 3471f1f5183SIcenowy Zheng 3481f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 3491f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 3501f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 3511f1f5183SIcenowy Zheng }; 3521f1f5183SIcenowy Zheng }; 353106deea8SPaul Kocialkowski 354106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 355106deea8SPaul Kocialkowski compatible = "mmio-sram"; 356106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 357106deea8SPaul Kocialkowski #address-cells = <1>; 358106deea8SPaul Kocialkowski #size-cells = <1>; 359106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 360106deea8SPaul Kocialkowski 361106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 362106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 363106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 364106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 365106deea8SPaul Kocialkowski }; 366106deea8SPaul Kocialkowski }; 36779b95360SCorentin Labbe }; 36879b95360SCorentin Labbe 369c32637e0SStefan Brüns dma: dma-controller@1c02000 { 370c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 371c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 372c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 373c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 374c32637e0SStefan Brüns dma-channels = <8>; 375c32637e0SStefan Brüns dma-requests = <27>; 376c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 377c32637e0SStefan Brüns #dma-cells = <1>; 378c32637e0SStefan Brüns }; 379c32637e0SStefan Brüns 380e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 381e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 382e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 383e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 384e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 385e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 386e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 387e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 38826c609d5SMaxime Ripard #clock-cells = <0>; 389e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 390e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 391e85f28e0SJagan Teki 392e85f28e0SJagan Teki ports { 393e85f28e0SJagan Teki #address-cells = <1>; 394e85f28e0SJagan Teki #size-cells = <0>; 395e85f28e0SJagan Teki 396e85f28e0SJagan Teki tcon0_in: port@0 { 397e85f28e0SJagan Teki #address-cells = <1>; 398e85f28e0SJagan Teki #size-cells = <0>; 399e85f28e0SJagan Teki reg = <0>; 400e85f28e0SJagan Teki 401e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 402e85f28e0SJagan Teki reg = <0>; 403e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 404e85f28e0SJagan Teki }; 405a7f7047fSMaxime Ripard 406a7f7047fSMaxime Ripard tcon0_in_mixer1: endpoint@1 { 407a7f7047fSMaxime Ripard reg = <1>; 408d41a43a0SMaxime Ripard remote-endpoint = <&mixer1_out_tcon0>; 409a7f7047fSMaxime Ripard }; 410e85f28e0SJagan Teki }; 411e85f28e0SJagan Teki 412e85f28e0SJagan Teki tcon0_out: port@1 { 413e85f28e0SJagan Teki #address-cells = <1>; 414e85f28e0SJagan Teki #size-cells = <0>; 415e85f28e0SJagan Teki reg = <1>; 41616c8ff57SJagan Teki 41716c8ff57SJagan Teki tcon0_out_dsi: endpoint@1 { 41816c8ff57SJagan Teki reg = <1>; 41916c8ff57SJagan Teki remote-endpoint = <&dsi_in_tcon0>; 42016c8ff57SJagan Teki allwinner,tcon-channel = <1>; 42116c8ff57SJagan Teki }; 422e85f28e0SJagan Teki }; 423e85f28e0SJagan Teki }; 424e85f28e0SJagan Teki }; 425e85f28e0SJagan Teki 426e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 427e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 428e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 429e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 430e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 431e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 432e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 433e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 434e85f28e0SJagan Teki reset-names = "lcd"; 435e85f28e0SJagan Teki 436e85f28e0SJagan Teki ports { 437e85f28e0SJagan Teki #address-cells = <1>; 438e85f28e0SJagan Teki #size-cells = <0>; 439e85f28e0SJagan Teki 440e85f28e0SJagan Teki tcon1_in: port@0 { 441a7f7047fSMaxime Ripard #address-cells = <1>; 442a7f7047fSMaxime Ripard #size-cells = <0>; 443e85f28e0SJagan Teki reg = <0>; 444e85f28e0SJagan Teki 445a7f7047fSMaxime Ripard tcon1_in_mixer0: endpoint@0 { 446a7f7047fSMaxime Ripard reg = <0>; 447a7f7047fSMaxime Ripard remote-endpoint = <&mixer0_out_tcon1>; 448a7f7047fSMaxime Ripard }; 449a7f7047fSMaxime Ripard 450a7f7047fSMaxime Ripard tcon1_in_mixer1: endpoint@1 { 451a7f7047fSMaxime Ripard reg = <1>; 452e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 453e85f28e0SJagan Teki }; 454e85f28e0SJagan Teki }; 455e85f28e0SJagan Teki 456e85f28e0SJagan Teki tcon1_out: port@1 { 457e85f28e0SJagan Teki #address-cells = <1>; 458e85f28e0SJagan Teki #size-cells = <0>; 459e85f28e0SJagan Teki reg = <1>; 460e85f28e0SJagan Teki 461e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 462e85f28e0SJagan Teki reg = <1>; 463e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 464e85f28e0SJagan Teki }; 465e85f28e0SJagan Teki }; 466e85f28e0SJagan Teki }; 467e85f28e0SJagan Teki }; 468e85f28e0SJagan Teki 469d60ce247SPaul Kocialkowski video-codec@1c0e000 { 4704ab88516SPaul Kocialkowski compatible = "allwinner,sun50i-a64-video-engine"; 471d60ce247SPaul Kocialkowski reg = <0x01c0e000 0x1000>; 472d60ce247SPaul Kocialkowski clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 473d60ce247SPaul Kocialkowski <&ccu CLK_DRAM_VE>; 474d60ce247SPaul Kocialkowski clock-names = "ahb", "mod", "ram"; 475d60ce247SPaul Kocialkowski resets = <&ccu RST_BUS_VE>; 476d60ce247SPaul Kocialkowski interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 477d60ce247SPaul Kocialkowski allwinner,sram = <&ve_sram 1>; 478d60ce247SPaul Kocialkowski }; 479d60ce247SPaul Kocialkowski 480f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 481f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 482f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 483f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 484f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 485f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 486f3dff347SAndre Przywara reset-names = "ahb"; 487f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 48822be992fSMaxime Ripard max-frequency = <150000000>; 489f3dff347SAndre Przywara status = "disabled"; 490f3dff347SAndre Przywara #address-cells = <1>; 491f3dff347SAndre Przywara #size-cells = <0>; 492f3dff347SAndre Przywara }; 493f3dff347SAndre Przywara 494f3dff347SAndre Przywara mmc1: mmc@1c10000 { 495f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 496f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 497f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 498f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 499f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 500f3dff347SAndre Przywara reset-names = "ahb"; 501f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 50222be992fSMaxime Ripard max-frequency = <150000000>; 503f3dff347SAndre Przywara status = "disabled"; 504f3dff347SAndre Przywara #address-cells = <1>; 505f3dff347SAndre Przywara #size-cells = <0>; 506f3dff347SAndre Przywara }; 507f3dff347SAndre Przywara 508f3dff347SAndre Przywara mmc2: mmc@1c11000 { 509f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 510f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 511f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 512f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 513f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 514f3dff347SAndre Przywara reset-names = "ahb"; 515f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 51622be992fSMaxime Ripard max-frequency = <200000000>; 517f3dff347SAndre Przywara status = "disabled"; 518f3dff347SAndre Przywara #address-cells = <1>; 519f3dff347SAndre Przywara #size-cells = <0>; 520f3dff347SAndre Przywara }; 521f3dff347SAndre Przywara 522ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 523ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 524ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 52559f5e9b9SVasily Khoruzhick #address-cells = <1>; 52659f5e9b9SVasily Khoruzhick #size-cells = <1>; 52759f5e9b9SVasily Khoruzhick 52859f5e9b9SVasily Khoruzhick ths_calibration: thermal-sensor-calibration@34 { 52959f5e9b9SVasily Khoruzhick reg = <0x34 0x8>; 53059f5e9b9SVasily Khoruzhick }; 531ac947b17SEmmanuel Vadot }; 532ac947b17SEmmanuel Vadot 5330f5fc158SCorentin Labbe crypto: crypto@1c15000 { 5340f5fc158SCorentin Labbe compatible = "allwinner,sun50i-a64-crypto"; 5350f5fc158SCorentin Labbe reg = <0x01c15000 0x1000>; 5360f5fc158SCorentin Labbe interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 5370f5fc158SCorentin Labbe clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 5380f5fc158SCorentin Labbe clock-names = "bus", "mod"; 5390f5fc158SCorentin Labbe resets = <&ccu RST_BUS_CE>; 5400f5fc158SCorentin Labbe }; 5410f5fc158SCorentin Labbe 5423e3f39a7SSamuel Holland msgbox: mailbox@1c17000 { 5433e3f39a7SSamuel Holland compatible = "allwinner,sun50i-a64-msgbox", 5443e3f39a7SSamuel Holland "allwinner,sun6i-a31-msgbox"; 5453e3f39a7SSamuel Holland reg = <0x01c17000 0x1000>; 5463e3f39a7SSamuel Holland clocks = <&ccu CLK_BUS_MSGBOX>; 5473e3f39a7SSamuel Holland resets = <&ccu RST_BUS_MSGBOX>; 5483e3f39a7SSamuel Holland interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 5493e3f39a7SSamuel Holland #mbox-cells = <1>; 5503e3f39a7SSamuel Holland }; 5513e3f39a7SSamuel Holland 552d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 553972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 554972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 555972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 556972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 557972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 558972a3ecdSIcenowy Zheng interrupt-names = "mc"; 559972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 560972a3ecdSIcenowy Zheng phy-names = "usb"; 561972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 5620973c06bSMaxime Ripard dr_mode = "otg"; 563972a3ecdSIcenowy Zheng status = "disabled"; 564972a3ecdSIcenowy Zheng }; 565972a3ecdSIcenowy Zheng 566d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 567a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 568a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 5690d984797SIcenowy Zheng <0x01c1a800 0x4>, 570a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 571a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 5720d984797SIcenowy Zheng "pmu0", 573a004ee35SIcenowy Zheng "pmu1"; 574a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 575a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 576a004ee35SIcenowy Zheng clock-names = "usb0_phy", 577a004ee35SIcenowy Zheng "usb1_phy"; 578a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 579a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 580a004ee35SIcenowy Zheng reset-names = "usb0_reset", 581a004ee35SIcenowy Zheng "usb1_reset"; 582a004ee35SIcenowy Zheng status = "disabled"; 583a004ee35SIcenowy Zheng #phy-cells = <1>; 584a004ee35SIcenowy Zheng }; 585a004ee35SIcenowy Zheng 586d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 587dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 588dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 589dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 590dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 591dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 592dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 593dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 594dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 595dc03a047SIcenowy Zheng status = "disabled"; 596dc03a047SIcenowy Zheng }; 597dc03a047SIcenowy Zheng 598d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 599dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 600dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 601dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 602dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 603dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 604dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 605dc03a047SIcenowy Zheng status = "disabled"; 606dc03a047SIcenowy Zheng }; 607dc03a047SIcenowy Zheng 608d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 609a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 610a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 611a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 612a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 613a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 614a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 615a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 616a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 617a004ee35SIcenowy Zheng phys = <&usbphy 1>; 618e6064cf4SMaxime Ripard phy-names = "usb"; 619a004ee35SIcenowy Zheng status = "disabled"; 620a004ee35SIcenowy Zheng }; 621a004ee35SIcenowy Zheng 622d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 623a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 624a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 625a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 626a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 627a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 628a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 629a004ee35SIcenowy Zheng phys = <&usbphy 1>; 630e6064cf4SMaxime Ripard phy-names = "usb"; 631a004ee35SIcenowy Zheng status = "disabled"; 632a004ee35SIcenowy Zheng }; 633a004ee35SIcenowy Zheng 634d6c9da12SCorentin LABBE ccu: clock@1c20000 { 6356bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 6366bc37facSAndre Przywara reg = <0x01c20000 0x400>; 63744ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>; 6386bc37facSAndre Przywara clock-names = "hosc", "losc"; 6396bc37facSAndre Przywara #clock-cells = <1>; 6406bc37facSAndre Przywara #reset-cells = <1>; 6416bc37facSAndre Przywara }; 6426bc37facSAndre Przywara 6436bc37facSAndre Przywara pio: pinctrl@1c20800 { 6446bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 6456bc37facSAndre Przywara reg = <0x01c20800 0x400>; 6466bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 6476bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 6486bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 649b71818cbSChen-Yu Tsai clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 650562bf196SMaxime Ripard clock-names = "apb", "hosc", "losc"; 6516bc37facSAndre Przywara gpio-controller; 6526bc37facSAndre Przywara #gpio-cells = <3>; 6536bc37facSAndre Przywara interrupt-controller; 6546bc37facSAndre Przywara #interrupt-cells = <3>; 6556bc37facSAndre Przywara 656ff29f13eSJagan Teki csi_pins: csi-pins { 657ff29f13eSJagan Teki pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 658ff29f13eSJagan Teki "PE7", "PE8", "PE9", "PE10", "PE11"; 659ff29f13eSJagan Teki function = "csi"; 660ff29f13eSJagan Teki }; 661ff29f13eSJagan Teki 662f7056b28SJagan Teki /omit-if-no-ref/ 663f7056b28SJagan Teki csi_mclk_pin: csi-mclk-pin { 664f7056b28SJagan Teki pins = "PE1"; 665f7056b28SJagan Teki function = "csi"; 666f7056b28SJagan Teki }; 667f7056b28SJagan Teki 66854eac67bSMaxime Ripard i2c0_pins: i2c0-pins { 66911239fe6SHarald Geyer pins = "PH0", "PH1"; 67011239fe6SHarald Geyer function = "i2c0"; 67111239fe6SHarald Geyer }; 67211239fe6SHarald Geyer 67354eac67bSMaxime Ripard i2c1_pins: i2c1-pins { 6746bc37facSAndre Przywara pins = "PH2", "PH3"; 6756bc37facSAndre Przywara function = "i2c1"; 6766bc37facSAndre Przywara }; 6776bc37facSAndre Przywara 67829b2c68bSOndrej Jirman i2c2_pins: i2c2-pins { 67929b2c68bSOndrej Jirman pins = "PE14", "PE15"; 68029b2c68bSOndrej Jirman function = "i2c2"; 68129b2c68bSOndrej Jirman }; 68229b2c68bSOndrej Jirman 683c478a12eSIcenowy Zheng /omit-if-no-ref/ 684c478a12eSIcenowy Zheng lcd_rgb666_pins: lcd-rgb666-pins { 685c478a12eSIcenowy Zheng pins = "PD0", "PD1", "PD2", "PD3", "PD4", 686c478a12eSIcenowy Zheng "PD5", "PD6", "PD7", "PD8", "PD9", 687c478a12eSIcenowy Zheng "PD10", "PD11", "PD12", "PD13", 688c478a12eSIcenowy Zheng "PD14", "PD15", "PD16", "PD17", 689c478a12eSIcenowy Zheng "PD18", "PD19", "PD20", "PD21"; 690c478a12eSIcenowy Zheng function = "lcd0"; 691c478a12eSIcenowy Zheng }; 692c478a12eSIcenowy Zheng 693a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 694a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 695a3e8f492SMaxime Ripard "PF4", "PF5"; 696a3e8f492SMaxime Ripard function = "mmc0"; 697a3e8f492SMaxime Ripard drive-strength = <30>; 698a3e8f492SMaxime Ripard bias-pull-up; 699a3e8f492SMaxime Ripard }; 700a3e8f492SMaxime Ripard 701a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 702a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 703a3e8f492SMaxime Ripard "PG4", "PG5"; 704a3e8f492SMaxime Ripard function = "mmc1"; 705a3e8f492SMaxime Ripard drive-strength = <30>; 706a3e8f492SMaxime Ripard bias-pull-up; 707a3e8f492SMaxime Ripard }; 708a3e8f492SMaxime Ripard 709a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 710fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 711a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 712a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 713a3e8f492SMaxime Ripard function = "mmc2"; 714a3e8f492SMaxime Ripard drive-strength = <30>; 715a3e8f492SMaxime Ripard bias-pull-up; 716a3e8f492SMaxime Ripard }; 717a3e8f492SMaxime Ripard 718fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 719fa59dd2eSChen-Yu Tsai pins = "PC1"; 720fa59dd2eSChen-Yu Tsai function = "mmc2"; 721fa59dd2eSChen-Yu Tsai drive-strength = <30>; 722fa59dd2eSChen-Yu Tsai bias-pull-up; 723fa59dd2eSChen-Yu Tsai }; 724fa59dd2eSChen-Yu Tsai 72554eac67bSMaxime Ripard pwm_pin: pwm-pin { 726b5df280bSAndre Przywara pins = "PD22"; 727b5df280bSAndre Przywara function = "pwm"; 728b5df280bSAndre Przywara }; 729b5df280bSAndre Przywara 73054eac67bSMaxime Ripard rmii_pins: rmii-pins { 731e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 732e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 733e53f67e9SCorentin Labbe function = "emac"; 734e53f67e9SCorentin Labbe drive-strength = <40>; 735e53f67e9SCorentin Labbe }; 736e53f67e9SCorentin Labbe 73754eac67bSMaxime Ripard rgmii_pins: rgmii-pins { 738e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 739e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 740e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 741e53f67e9SCorentin Labbe function = "emac"; 742e53f67e9SCorentin Labbe drive-strength = <40>; 743e53f67e9SCorentin Labbe }; 744e53f67e9SCorentin Labbe 74554eac67bSMaxime Ripard spdif_tx_pin: spdif-tx-pin { 746b399d2acSMarcus Cooper pins = "PH8"; 747b399d2acSMarcus Cooper function = "spdif"; 748b399d2acSMarcus Cooper }; 749b399d2acSMarcus Cooper 75054eac67bSMaxime Ripard spi0_pins: spi0-pins { 751b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 752b518bb15SStefan Brüns function = "spi0"; 753b518bb15SStefan Brüns }; 754b518bb15SStefan Brüns 75554eac67bSMaxime Ripard spi1_pins: spi1-pins { 756b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 757b518bb15SStefan Brüns function = "spi1"; 758b518bb15SStefan Brüns }; 759b518bb15SStefan Brüns 760d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 7616bc37facSAndre Przywara pins = "PB8", "PB9"; 7626bc37facSAndre Przywara function = "uart0"; 7636bc37facSAndre Przywara }; 764e7ba733dSAndre Przywara 76554eac67bSMaxime Ripard uart1_pins: uart1-pins { 766e7ba733dSAndre Przywara pins = "PG6", "PG7"; 767e7ba733dSAndre Przywara function = "uart1"; 768e7ba733dSAndre Przywara }; 769e7ba733dSAndre Przywara 77054eac67bSMaxime Ripard uart1_rts_cts_pins: uart1-rts-cts-pins { 771e7ba733dSAndre Przywara pins = "PG8", "PG9"; 772e7ba733dSAndre Przywara function = "uart1"; 773e7ba733dSAndre Przywara }; 77479825719SAndreas Färber 77579825719SAndreas Färber uart2_pins: uart2-pins { 77679825719SAndreas Färber pins = "PB0", "PB1"; 77779825719SAndreas Färber function = "uart2"; 77879825719SAndreas Färber }; 7792273aa16SAndreas Färber 7802273aa16SAndreas Färber uart3_pins: uart3-pins { 7812273aa16SAndreas Färber pins = "PD0", "PD1"; 7822273aa16SAndreas Färber function = "uart3"; 7832273aa16SAndreas Färber }; 7842273aa16SAndreas Färber 7852273aa16SAndreas Färber uart4_pins: uart4-pins { 7862273aa16SAndreas Färber pins = "PD2", "PD3"; 7872273aa16SAndreas Färber function = "uart4"; 7882273aa16SAndreas Färber }; 7892273aa16SAndreas Färber 7902273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 7912273aa16SAndreas Färber pins = "PD4", "PD5"; 7922273aa16SAndreas Färber function = "uart4"; 7932273aa16SAndreas Färber }; 7946bc37facSAndre Przywara }; 7956bc37facSAndre Przywara 796b399d2acSMarcus Cooper spdif: spdif@1c21000 { 797b399d2acSMarcus Cooper #sound-dai-cells = <0>; 798b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 799b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 800b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 801b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 802b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 803b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 804b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 805b399d2acSMarcus Cooper dmas = <&dma 2>; 806b399d2acSMarcus Cooper dma-names = "tx"; 807b399d2acSMarcus Cooper pinctrl-names = "default"; 808b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 809b399d2acSMarcus Cooper status = "disabled"; 810b399d2acSMarcus Cooper }; 811b399d2acSMarcus Cooper 81284204fb6SLuca Weiss lradc: lradc@1c21800 { 81384204fb6SLuca Weiss compatible = "allwinner,sun50i-a64-lradc", 81484204fb6SLuca Weiss "allwinner,sun8i-a83t-r-lradc"; 81584204fb6SLuca Weiss reg = <0x01c21800 0x400>; 81684204fb6SLuca Weiss interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 81784204fb6SLuca Weiss status = "disabled"; 81884204fb6SLuca Weiss }; 81984204fb6SLuca Weiss 8201c92c009SMarcus Cooper i2s0: i2s@1c22000 { 8211c92c009SMarcus Cooper #sound-dai-cells = <0>; 8221c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8231c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8241c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 8251c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8261c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 8271c92c009SMarcus Cooper clock-names = "apb", "mod"; 8281c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 8291c92c009SMarcus Cooper dma-names = "rx", "tx"; 8301c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 8311c92c009SMarcus Cooper status = "disabled"; 8321c92c009SMarcus Cooper }; 8331c92c009SMarcus Cooper 8341c92c009SMarcus Cooper i2s1: i2s@1c22400 { 8351c92c009SMarcus Cooper #sound-dai-cells = <0>; 8361c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8371c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8381c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 8391c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8401c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 8411c92c009SMarcus Cooper clock-names = "apb", "mod"; 8421c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 8431c92c009SMarcus Cooper dma-names = "rx", "tx"; 8441c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 8451c92c009SMarcus Cooper status = "disabled"; 8461c92c009SMarcus Cooper }; 8471c92c009SMarcus Cooper 848ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 849ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 850ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 851ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 852ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 853ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 854ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 855ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 856ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 857ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 858ec4a9540SVasily Khoruzhick status = "disabled"; 859ec4a9540SVasily Khoruzhick }; 860ec4a9540SVasily Khoruzhick 861ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 862ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 863ec4a9540SVasily Khoruzhick compatible = "allwinner,sun8i-a33-codec"; 864ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 865ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 866ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 867ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 868ec4a9540SVasily Khoruzhick status = "disabled"; 869ec4a9540SVasily Khoruzhick }; 870ec4a9540SVasily Khoruzhick 87159f5e9b9SVasily Khoruzhick ths: thermal-sensor@1c25000 { 87259f5e9b9SVasily Khoruzhick compatible = "allwinner,sun50i-a64-ths"; 87359f5e9b9SVasily Khoruzhick reg = <0x01c25000 0x100>; 87459f5e9b9SVasily Khoruzhick clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 87559f5e9b9SVasily Khoruzhick clock-names = "bus", "mod"; 87659f5e9b9SVasily Khoruzhick interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 87759f5e9b9SVasily Khoruzhick resets = <&ccu RST_BUS_THS>; 87859f5e9b9SVasily Khoruzhick nvmem-cells = <&ths_calibration>; 87959f5e9b9SVasily Khoruzhick nvmem-cell-names = "calibration"; 88059f5e9b9SVasily Khoruzhick #thermal-sensor-cells = <1>; 88159f5e9b9SVasily Khoruzhick }; 88259f5e9b9SVasily Khoruzhick 8836bc37facSAndre Przywara uart0: serial@1c28000 { 8846bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8856bc37facSAndre Przywara reg = <0x01c28000 0x400>; 8866bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8876bc37facSAndre Przywara reg-shift = <2>; 8886bc37facSAndre Przywara reg-io-width = <4>; 889494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 890494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 8916bc37facSAndre Przywara status = "disabled"; 8926bc37facSAndre Przywara }; 8936bc37facSAndre Przywara 8946bc37facSAndre Przywara uart1: serial@1c28400 { 8956bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8966bc37facSAndre Przywara reg = <0x01c28400 0x400>; 8976bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 8986bc37facSAndre Przywara reg-shift = <2>; 8996bc37facSAndre Przywara reg-io-width = <4>; 900494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 901494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 9026bc37facSAndre Przywara status = "disabled"; 9036bc37facSAndre Przywara }; 9046bc37facSAndre Przywara 9056bc37facSAndre Przywara uart2: serial@1c28800 { 9066bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9076bc37facSAndre Przywara reg = <0x01c28800 0x400>; 9086bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 9096bc37facSAndre Przywara reg-shift = <2>; 9106bc37facSAndre Przywara reg-io-width = <4>; 911494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 912494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 9136bc37facSAndre Przywara status = "disabled"; 9146bc37facSAndre Przywara }; 9156bc37facSAndre Przywara 9166bc37facSAndre Przywara uart3: serial@1c28c00 { 9176bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9186bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 9196bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 9206bc37facSAndre Przywara reg-shift = <2>; 9216bc37facSAndre Przywara reg-io-width = <4>; 922494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 923494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 9246bc37facSAndre Przywara status = "disabled"; 9256bc37facSAndre Przywara }; 9266bc37facSAndre Przywara 9276bc37facSAndre Przywara uart4: serial@1c29000 { 9286bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9296bc37facSAndre Przywara reg = <0x01c29000 0x400>; 9306bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 9316bc37facSAndre Przywara reg-shift = <2>; 9326bc37facSAndre Przywara reg-io-width = <4>; 933494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 934494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 9356bc37facSAndre Przywara status = "disabled"; 9366bc37facSAndre Przywara }; 9376bc37facSAndre Przywara 9386bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 9396bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9406bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 9416bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 942494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 943494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 94470f76289SJagan Teki pinctrl-names = "default"; 94570f76289SJagan Teki pinctrl-0 = <&i2c0_pins>; 9466bc37facSAndre Przywara status = "disabled"; 9476bc37facSAndre Przywara #address-cells = <1>; 9486bc37facSAndre Przywara #size-cells = <0>; 9496bc37facSAndre Przywara }; 9506bc37facSAndre Przywara 9516bc37facSAndre Przywara i2c1: i2c@1c2b000 { 9526bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9536bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 9546bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 955494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 956494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 95770f76289SJagan Teki pinctrl-names = "default"; 95870f76289SJagan Teki pinctrl-0 = <&i2c1_pins>; 9596bc37facSAndre Przywara status = "disabled"; 9606bc37facSAndre Przywara #address-cells = <1>; 9616bc37facSAndre Przywara #size-cells = <0>; 9626bc37facSAndre Przywara }; 9636bc37facSAndre Przywara 9646bc37facSAndre Przywara i2c2: i2c@1c2b400 { 9656bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9666bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 9676bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 968494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 969494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 97029b2c68bSOndrej Jirman pinctrl-names = "default"; 97129b2c68bSOndrej Jirman pinctrl-0 = <&i2c2_pins>; 9726bc37facSAndre Przywara status = "disabled"; 9736bc37facSAndre Przywara #address-cells = <1>; 9746bc37facSAndre Przywara #size-cells = <0>; 9756bc37facSAndre Przywara }; 9766bc37facSAndre Przywara 977d6c9da12SCorentin LABBE spi0: spi@1c68000 { 978b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 979b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 980b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 981b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 982b518bb15SStefan Brüns clock-names = "ahb", "mod"; 98306c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 98406c1258aSStefan Brüns dma-names = "rx", "tx"; 985b518bb15SStefan Brüns pinctrl-names = "default"; 986b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 987b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 988b518bb15SStefan Brüns status = "disabled"; 989b518bb15SStefan Brüns num-cs = <1>; 990b518bb15SStefan Brüns #address-cells = <1>; 991b518bb15SStefan Brüns #size-cells = <0>; 992b518bb15SStefan Brüns }; 993b518bb15SStefan Brüns 994d6c9da12SCorentin LABBE spi1: spi@1c69000 { 995b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 996b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 997b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 998b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 999b518bb15SStefan Brüns clock-names = "ahb", "mod"; 100006c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 100106c1258aSStefan Brüns dma-names = "rx", "tx"; 1002b518bb15SStefan Brüns pinctrl-names = "default"; 1003b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 1004b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 1005b518bb15SStefan Brüns status = "disabled"; 1006b518bb15SStefan Brüns num-cs = <1>; 1007b518bb15SStefan Brüns #address-cells = <1>; 1008b518bb15SStefan Brüns #size-cells = <0>; 1009b518bb15SStefan Brüns }; 1010b518bb15SStefan Brüns 101194f44288SCorentin Labbe emac: ethernet@1c30000 { 101294f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 101394f44288SCorentin Labbe syscon = <&syscon>; 101494f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 101594f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 101694f44288SCorentin Labbe interrupt-names = "macirq"; 101794f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 101894f44288SCorentin Labbe reset-names = "stmmaceth"; 101994f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 102094f44288SCorentin Labbe clock-names = "stmmaceth"; 102194f44288SCorentin Labbe status = "disabled"; 102294f44288SCorentin Labbe 102394f44288SCorentin Labbe mdio: mdio { 102416416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 102594f44288SCorentin Labbe #address-cells = <1>; 102694f44288SCorentin Labbe #size-cells = <0>; 102794f44288SCorentin Labbe }; 102894f44288SCorentin Labbe }; 102994f44288SCorentin Labbe 10306b683d76SJagan Teki mali: gpu@1c40000 { 10316b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 10326b683d76SJagan Teki reg = <0x01c40000 0x10000>; 10336b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 10346b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 10356b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 10366b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 10376b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 10386b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 10396b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 10406b683d76SJagan Teki interrupt-names = "gp", 10416b683d76SJagan Teki "gpmmu", 10426b683d76SJagan Teki "pp0", 10436b683d76SJagan Teki "ppmmu0", 10446b683d76SJagan Teki "pp1", 10456b683d76SJagan Teki "ppmmu1", 10466b683d76SJagan Teki "pmu"; 10476b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 10486b683d76SJagan Teki clock-names = "bus", "core"; 10496b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 10506b683d76SJagan Teki }; 10516b683d76SJagan Teki 10526bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 10536bc37facSAndre Przywara compatible = "arm,gic-400"; 10546bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 10556bc37facSAndre Przywara <0x01c82000 0x2000>, 10566bc37facSAndre Przywara <0x01c84000 0x2000>, 10576bc37facSAndre Przywara <0x01c86000 0x2000>; 10586bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 10596bc37facSAndre Przywara interrupt-controller; 10606bc37facSAndre Przywara #interrupt-cells = <3>; 10616bc37facSAndre Przywara }; 10626bc37facSAndre Przywara 1063b5df280bSAndre Przywara pwm: pwm@1c21400 { 1064b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1065b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1066b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 1067b5df280bSAndre Przywara clocks = <&osc24M>; 1068b5df280bSAndre Przywara pinctrl-names = "default"; 1069b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 1070b5df280bSAndre Przywara #pwm-cells = <3>; 1071b5df280bSAndre Przywara status = "disabled"; 1072b5df280bSAndre Przywara }; 1073b5df280bSAndre Przywara 1074fc7c2bfbSJernej Skrabec mbus: dram-controller@1c62000 { 1075fc7c2bfbSJernej Skrabec compatible = "allwinner,sun50i-a64-mbus"; 1076fc7c2bfbSJernej Skrabec reg = <0x01c62000 0x1000>; 1077fc7c2bfbSJernej Skrabec clocks = <&ccu 112>; 1078cff11101SOndrej Jirman #address-cells = <1>; 1079cff11101SOndrej Jirman #size-cells = <1>; 1080fc7c2bfbSJernej Skrabec dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1081fc7c2bfbSJernej Skrabec #interconnect-cells = <1>; 1082fc7c2bfbSJernej Skrabec }; 1083fc7c2bfbSJernej Skrabec 1084ff29f13eSJagan Teki csi: csi@1cb0000 { 1085ff29f13eSJagan Teki compatible = "allwinner,sun50i-a64-csi"; 1086ff29f13eSJagan Teki reg = <0x01cb0000 0x1000>; 1087ff29f13eSJagan Teki interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1088ff29f13eSJagan Teki clocks = <&ccu CLK_BUS_CSI>, 1089ff29f13eSJagan Teki <&ccu CLK_CSI_SCLK>, 1090ff29f13eSJagan Teki <&ccu CLK_DRAM_CSI>; 1091ff29f13eSJagan Teki clock-names = "bus", "mod", "ram"; 1092ff29f13eSJagan Teki resets = <&ccu RST_BUS_CSI>; 1093ff29f13eSJagan Teki pinctrl-names = "default"; 1094ff29f13eSJagan Teki pinctrl-0 = <&csi_pins>; 1095ff29f13eSJagan Teki status = "disabled"; 1096ff29f13eSJagan Teki }; 1097ff29f13eSJagan Teki 109816c8ff57SJagan Teki dsi: dsi@1ca0000 { 109916c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dsi"; 110016c8ff57SJagan Teki reg = <0x01ca0000 0x1000>; 110116c8ff57SJagan Teki interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 110216c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>; 110316c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 110416c8ff57SJagan Teki phys = <&dphy>; 110516c8ff57SJagan Teki phy-names = "dphy"; 110616c8ff57SJagan Teki status = "disabled"; 110716c8ff57SJagan Teki #address-cells = <1>; 110816c8ff57SJagan Teki #size-cells = <0>; 110916c8ff57SJagan Teki 111016c8ff57SJagan Teki port { 111116c8ff57SJagan Teki dsi_in_tcon0: endpoint { 111216c8ff57SJagan Teki remote-endpoint = <&tcon0_out_dsi>; 111316c8ff57SJagan Teki }; 111416c8ff57SJagan Teki }; 111516c8ff57SJagan Teki }; 111616c8ff57SJagan Teki 111716c8ff57SJagan Teki dphy: d-phy@1ca1000 { 111816c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dphy", 111916c8ff57SJagan Teki "allwinner,sun6i-a31-mipi-dphy"; 112016c8ff57SJagan Teki reg = <0x01ca1000 0x1000>; 112116c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>, 112216c8ff57SJagan Teki <&ccu CLK_DSI_DPHY>; 112316c8ff57SJagan Teki clock-names = "bus", "mod"; 112416c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 112516c8ff57SJagan Teki status = "disabled"; 112616c8ff57SJagan Teki #phy-cells = <0>; 112716c8ff57SJagan Teki }; 112816c8ff57SJagan Teki 1129dd00d78dSJernej Skrabec deinterlace: deinterlace@1e00000 { 1130dd00d78dSJernej Skrabec compatible = "allwinner,sun50i-a64-deinterlace", 1131dd00d78dSJernej Skrabec "allwinner,sun8i-h3-deinterlace"; 1132dd00d78dSJernej Skrabec reg = <0x01e00000 0x20000>; 1133dd00d78dSJernej Skrabec clocks = <&ccu CLK_BUS_DEINTERLACE>, 1134dd00d78dSJernej Skrabec <&ccu CLK_DEINTERLACE>, 1135dd00d78dSJernej Skrabec <&ccu CLK_DRAM_DEINTERLACE>; 1136dd00d78dSJernej Skrabec clock-names = "bus", "mod", "ram"; 1137dd00d78dSJernej Skrabec resets = <&ccu RST_BUS_DEINTERLACE>; 1138dd00d78dSJernej Skrabec interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1139dd00d78dSJernej Skrabec interconnects = <&mbus 9>; 1140dd00d78dSJernej Skrabec interconnect-names = "dma-mem"; 1141dd00d78dSJernej Skrabec }; 1142dd00d78dSJernej Skrabec 1143e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 1144e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 1145e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 1146e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 1147e85f28e0SJagan Teki reg-io-width = <1>; 1148e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1149e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1150e85f28e0SJagan Teki <&ccu CLK_HDMI>; 1151e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 1152e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 1153e85f28e0SJagan Teki reset-names = "ctrl"; 1154e85f28e0SJagan Teki phys = <&hdmi_phy>; 1155d40113fbSMaxime Ripard phy-names = "phy"; 1156e85f28e0SJagan Teki status = "disabled"; 1157e85f28e0SJagan Teki 1158e85f28e0SJagan Teki ports { 1159e85f28e0SJagan Teki #address-cells = <1>; 1160e85f28e0SJagan Teki #size-cells = <0>; 1161e85f28e0SJagan Teki 1162e85f28e0SJagan Teki hdmi_in: port@0 { 1163e85f28e0SJagan Teki reg = <0>; 1164e85f28e0SJagan Teki 1165e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 1166e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 1167e85f28e0SJagan Teki }; 1168e85f28e0SJagan Teki }; 1169e85f28e0SJagan Teki 1170e85f28e0SJagan Teki hdmi_out: port@1 { 1171e85f28e0SJagan Teki reg = <1>; 1172e85f28e0SJagan Teki }; 1173e85f28e0SJagan Teki }; 1174e85f28e0SJagan Teki }; 1175e85f28e0SJagan Teki 1176e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 1177e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 1178e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 1179e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1180b71818cbSChen-Yu Tsai <&ccu CLK_PLL_VIDEO0>; 1181e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 1182e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 1183e85f28e0SJagan Teki reset-names = "phy"; 1184e85f28e0SJagan Teki #phy-cells = <0>; 1185e85f28e0SJagan Teki }; 1186e85f28e0SJagan Teki 11876bc37facSAndre Przywara rtc: rtc@1f00000 { 118844ff3cafSChen-Yu Tsai compatible = "allwinner,sun50i-a64-rtc", 118944ff3cafSChen-Yu Tsai "allwinner,sun8i-h3-rtc"; 119044ff3cafSChen-Yu Tsai reg = <0x01f00000 0x400>; 11916bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 11926bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 119344ff3cafSChen-Yu Tsai clock-output-names = "osc32k", "osc32k-out", "iosc"; 1194e1a9a474SJagan Teki clocks = <&osc32k>; 1195e1a9a474SJagan Teki #clock-cells = <1>; 11966bc37facSAndre Przywara }; 1197791a9e00SIcenowy Zheng 1198535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 1199535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 1200535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 1201535ca508SIcenowy Zheng interrupt-controller; 1202535ca508SIcenowy Zheng #interrupt-cells = <2>; 1203535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 1204535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1205535ca508SIcenowy Zheng }; 1206535ca508SIcenowy Zheng 1207791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 1208791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 1209791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 1210b71818cbSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 1211b71818cbSChen-Yu Tsai <&ccu CLK_PLL_PERIPH0>; 1212f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 1213791a9e00SIcenowy Zheng #clock-cells = <1>; 1214791a9e00SIcenowy Zheng #reset-cells = <1>; 1215791a9e00SIcenowy Zheng }; 1216ec427905SIcenowy Zheng 1217ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 1218ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 1219ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 1220ec4a9540SVasily Khoruzhick status = "disabled"; 1221ec4a9540SVasily Khoruzhick }; 1222ec4a9540SVasily Khoruzhick 1223871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 1224871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 1225871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 1226871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 1227871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1228871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1229871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1230871b5352SIcenowy Zheng status = "disabled"; 1231871b5352SIcenowy Zheng #address-cells = <1>; 1232871b5352SIcenowy Zheng #size-cells = <0>; 1233871b5352SIcenowy Zheng }; 1234871b5352SIcenowy Zheng 123544a4f416SIgors Makejevs r_ir: ir@1f02000 { 123644a4f416SIgors Makejevs compatible = "allwinner,sun50i-a64-ir", 123744a4f416SIgors Makejevs "allwinner,sun6i-a31-ir"; 123844a4f416SIgors Makejevs reg = <0x01f02000 0x400>; 123944a4f416SIgors Makejevs clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 124044a4f416SIgors Makejevs clock-names = "apb", "ir"; 124144a4f416SIgors Makejevs resets = <&r_ccu RST_APB0_IR>; 124244a4f416SIgors Makejevs interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 124344a4f416SIgors Makejevs pinctrl-names = "default"; 124444a4f416SIgors Makejevs pinctrl-0 = <&r_ir_rx_pin>; 124544a4f416SIgors Makejevs status = "disabled"; 124644a4f416SIgors Makejevs }; 124744a4f416SIgors Makejevs 1248b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1249b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1250b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1251b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1252b5df280bSAndre Przywara clocks = <&osc24M>; 1253b5df280bSAndre Przywara pinctrl-names = "default"; 1254b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1255b5df280bSAndre Przywara #pwm-cells = <3>; 1256b5df280bSAndre Przywara status = "disabled"; 1257b5df280bSAndre Przywara }; 1258b5df280bSAndre Przywara 1259d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1260ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1261ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1262ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1263494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1264ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1265ec427905SIcenowy Zheng gpio-controller; 1266ec427905SIcenowy Zheng #gpio-cells = <3>; 1267ec427905SIcenowy Zheng interrupt-controller; 1268ec427905SIcenowy Zheng #interrupt-cells = <3>; 12693b38fdedSIcenowy Zheng 12701b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1271871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1272871b5352SIcenowy Zheng function = "s_i2c"; 1273871b5352SIcenowy Zheng }; 1274871b5352SIcenowy Zheng 127544a4f416SIgors Makejevs r_ir_rx_pin: r-ir-rx-pin { 127644a4f416SIgors Makejevs pins = "PL11"; 127744a4f416SIgors Makejevs function = "s_cir_rx"; 127844a4f416SIgors Makejevs }; 127944a4f416SIgors Makejevs 128054eac67bSMaxime Ripard r_pwm_pin: r-pwm-pin { 1281b5df280bSAndre Przywara pins = "PL10"; 1282b5df280bSAndre Przywara function = "s_pwm"; 1283b5df280bSAndre Przywara }; 1284b5df280bSAndre Przywara 128554eac67bSMaxime Ripard r_rsb_pins: r-rsb-pins { 12863b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 12873b38fdedSIcenowy Zheng function = "s_rsb"; 12883b38fdedSIcenowy Zheng }; 12893b38fdedSIcenowy Zheng }; 12903b38fdedSIcenowy Zheng 12913b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 12923b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 12933b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 12943b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 12953b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 12963b38fdedSIcenowy Zheng clock-frequency = <3000000>; 12973b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 12983b38fdedSIcenowy Zheng pinctrl-names = "default"; 12993b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 13003b38fdedSIcenowy Zheng status = "disabled"; 13013b38fdedSIcenowy Zheng #address-cells = <1>; 13023b38fdedSIcenowy Zheng #size-cells = <0>; 1303ec427905SIcenowy Zheng }; 1304d4185043SHarald Geyer 1305d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 1306d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 1307d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 1308d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 1309d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 13109e1975f0SMaxime Ripard clocks = <&osc24M>; 1311d4185043SHarald Geyer }; 13126bc37facSAndre Przywara }; 13136bc37facSAndre Przywara}; 1314