1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd. 3cabbaed7SClément Péron// based on the Allwinner H3 dtsi: 4cabbaed7SClément Péron// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara 6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 72c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 8494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 96bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 10a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 112c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 12871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 1359f5e9b9SVasily Khoruzhick#include <dt-bindings/thermal/thermal.h> 146bc37facSAndre Przywara 156bc37facSAndre Przywara/ { 166bc37facSAndre Przywara interrupt-parent = <&gic>; 176bc37facSAndre Przywara #address-cells = <1>; 186bc37facSAndre Przywara #size-cells = <1>; 196bc37facSAndre Przywara 20c1cff65fSHarald Geyer chosen { 21c1cff65fSHarald Geyer #address-cells = <1>; 22c1cff65fSHarald Geyer #size-cells = <1>; 23c1cff65fSHarald Geyer ranges; 24c1cff65fSHarald Geyer 25c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 26c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 27c1cff65fSHarald Geyer "simple-framebuffer"; 28c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 29c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 302c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 31c1cff65fSHarald Geyer status = "disabled"; 32c1cff65fSHarald Geyer }; 33fca63f58SIcenowy Zheng 34fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 35fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 36fca63f58SIcenowy Zheng "simple-framebuffer"; 37fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 38fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 39fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40fca63f58SIcenowy Zheng status = "disabled"; 41fca63f58SIcenowy Zheng }; 42c1cff65fSHarald Geyer }; 43c1cff65fSHarald Geyer 446bc37facSAndre Przywara cpus { 456bc37facSAndre Przywara #address-cells = <1>; 466bc37facSAndre Przywara #size-cells = <0>; 476bc37facSAndre Przywara 486bc37facSAndre Przywara cpu0: cpu@0 { 4931af04cdSRob Herring compatible = "arm,cortex-a53"; 506bc37facSAndre Przywara device_type = "cpu"; 516bc37facSAndre Przywara reg = <0>; 526bc37facSAndre Przywara enable-method = "psci"; 5339defc81SAndre Przywara next-level-cache = <&L2>; 546bc37facSAndre Przywara }; 556bc37facSAndre Przywara 566bc37facSAndre Przywara cpu1: cpu@1 { 5731af04cdSRob Herring compatible = "arm,cortex-a53"; 586bc37facSAndre Przywara device_type = "cpu"; 596bc37facSAndre Przywara reg = <1>; 606bc37facSAndre Przywara enable-method = "psci"; 6139defc81SAndre Przywara next-level-cache = <&L2>; 626bc37facSAndre Przywara }; 636bc37facSAndre Przywara 646bc37facSAndre Przywara cpu2: cpu@2 { 6531af04cdSRob Herring compatible = "arm,cortex-a53"; 666bc37facSAndre Przywara device_type = "cpu"; 676bc37facSAndre Przywara reg = <2>; 686bc37facSAndre Przywara enable-method = "psci"; 6939defc81SAndre Przywara next-level-cache = <&L2>; 706bc37facSAndre Przywara }; 716bc37facSAndre Przywara 726bc37facSAndre Przywara cpu3: cpu@3 { 7331af04cdSRob Herring compatible = "arm,cortex-a53"; 746bc37facSAndre Przywara device_type = "cpu"; 756bc37facSAndre Przywara reg = <3>; 766bc37facSAndre Przywara enable-method = "psci"; 7739defc81SAndre Przywara next-level-cache = <&L2>; 7839defc81SAndre Przywara }; 7939defc81SAndre Przywara 8039defc81SAndre Przywara L2: l2-cache { 8139defc81SAndre Przywara compatible = "cache"; 8239defc81SAndre Przywara cache-level = <2>; 836bc37facSAndre Przywara }; 846bc37facSAndre Przywara }; 856bc37facSAndre Przywara 86e85f28e0SJagan Teki de: display-engine { 87e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 88e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 89e85f28e0SJagan Teki <&mixer1>; 90e85f28e0SJagan Teki status = "disabled"; 91e85f28e0SJagan Teki }; 92e85f28e0SJagan Teki 936bc37facSAndre Przywara osc24M: osc24M_clk { 946bc37facSAndre Przywara #clock-cells = <0>; 956bc37facSAndre Przywara compatible = "fixed-clock"; 966bc37facSAndre Przywara clock-frequency = <24000000>; 976bc37facSAndre Przywara clock-output-names = "osc24M"; 986bc37facSAndre Przywara }; 996bc37facSAndre Przywara 1006bc37facSAndre Przywara osc32k: osc32k_clk { 1016bc37facSAndre Przywara #clock-cells = <0>; 1026bc37facSAndre Przywara compatible = "fixed-clock"; 1036bc37facSAndre Przywara clock-frequency = <32768>; 10444ff3cafSChen-Yu Tsai clock-output-names = "ext-osc32k"; 105791a9e00SIcenowy Zheng }; 106791a9e00SIcenowy Zheng 10734a97fccSHarald Geyer pmu { 10834a97fccSHarald Geyer compatible = "arm,cortex-a53-pmu"; 1096b832a14SAndre Przywara interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1106b832a14SAndre Przywara <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1116b832a14SAndre Przywara <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1126b832a14SAndre Przywara <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 11334a97fccSHarald Geyer interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 11434a97fccSHarald Geyer }; 11534a97fccSHarald Geyer 1166bc37facSAndre Przywara psci { 1176bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1186bc37facSAndre Przywara method = "smc"; 1196bc37facSAndre Przywara }; 1206bc37facSAndre Przywara 121ec4a9540SVasily Khoruzhick sound: sound { 122ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 123ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 124ec4a9540SVasily Khoruzhick simple-audio-card,format = "i2s"; 125ec4a9540SVasily Khoruzhick simple-audio-card,frame-master = <&cpudai>; 126ec4a9540SVasily Khoruzhick simple-audio-card,bitclock-master = <&cpudai>; 127ec4a9540SVasily Khoruzhick simple-audio-card,mclk-fs = <128>; 128ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 129ec4a9540SVasily Khoruzhick simple-audio-card,routing = 130ec4a9540SVasily Khoruzhick "Left DAC", "AIF1 Slot 0 Left", 131ec4a9540SVasily Khoruzhick "Right DAC", "AIF1 Slot 0 Right", 132ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Left ADC", "Left ADC", 133ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Right ADC", "Right ADC"; 134ec4a9540SVasily Khoruzhick status = "disabled"; 135ec4a9540SVasily Khoruzhick 136ec4a9540SVasily Khoruzhick cpudai: simple-audio-card,cpu { 137ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 138ec4a9540SVasily Khoruzhick }; 139ec4a9540SVasily Khoruzhick 140ec4a9540SVasily Khoruzhick link_codec: simple-audio-card,codec { 141ec4a9540SVasily Khoruzhick sound-dai = <&codec>; 142ec4a9540SVasily Khoruzhick }; 143ec4a9540SVasily Khoruzhick }; 144ec4a9540SVasily Khoruzhick 14578e07137SMarcus Cooper sound_spdif { 14678e07137SMarcus Cooper compatible = "simple-audio-card"; 14778e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 14878e07137SMarcus Cooper 14978e07137SMarcus Cooper simple-audio-card,cpu { 15078e07137SMarcus Cooper sound-dai = <&spdif>; 15178e07137SMarcus Cooper }; 15278e07137SMarcus Cooper 15378e07137SMarcus Cooper simple-audio-card,codec { 15478e07137SMarcus Cooper sound-dai = <&spdif_out>; 15578e07137SMarcus Cooper }; 15678e07137SMarcus Cooper }; 15778e07137SMarcus Cooper 15878e07137SMarcus Cooper spdif_out: spdif-out { 15978e07137SMarcus Cooper #sound-dai-cells = <0>; 16078e07137SMarcus Cooper compatible = "linux,spdif-dit"; 16178e07137SMarcus Cooper }; 16278e07137SMarcus Cooper 1636bc37facSAndre Przywara timer { 1646bc37facSAndre Przywara compatible = "arm,armv8-timer"; 16555ec26d6SSamuel Holland allwinner,erratum-unknown1; 1666bc37facSAndre Przywara interrupts = <GIC_PPI 13 1676bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1686bc37facSAndre Przywara <GIC_PPI 14 1696bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1706bc37facSAndre Przywara <GIC_PPI 11 1716bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1726bc37facSAndre Przywara <GIC_PPI 10 1736bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1746bc37facSAndre Przywara }; 1756bc37facSAndre Przywara 17659f5e9b9SVasily Khoruzhick thermal-zones { 17759f5e9b9SVasily Khoruzhick cpu_thermal: cpu0-thermal { 17859f5e9b9SVasily Khoruzhick /* milliseconds */ 17959f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 18059f5e9b9SVasily Khoruzhick polling-delay = <0>; 18159f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 0>; 18259f5e9b9SVasily Khoruzhick }; 18359f5e9b9SVasily Khoruzhick 18459f5e9b9SVasily Khoruzhick gpu0_thermal: gpu0-thermal { 18559f5e9b9SVasily Khoruzhick /* milliseconds */ 18659f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 18759f5e9b9SVasily Khoruzhick polling-delay = <0>; 18859f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 1>; 18959f5e9b9SVasily Khoruzhick }; 19059f5e9b9SVasily Khoruzhick 19159f5e9b9SVasily Khoruzhick gpu1_thermal: gpu1-thermal { 19259f5e9b9SVasily Khoruzhick /* milliseconds */ 19359f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 19459f5e9b9SVasily Khoruzhick polling-delay = <0>; 19559f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 2>; 19659f5e9b9SVasily Khoruzhick }; 19759f5e9b9SVasily Khoruzhick }; 19859f5e9b9SVasily Khoruzhick 1996bc37facSAndre Przywara soc { 2006bc37facSAndre Przywara compatible = "simple-bus"; 2016bc37facSAndre Przywara #address-cells = <1>; 2026bc37facSAndre Przywara #size-cells = <1>; 2036bc37facSAndre Przywara ranges; 2046bc37facSAndre Przywara 205275b6317SMaxime Ripard bus@1000000 { 2062c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 2072c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 2082c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 2092c796fc8SIcenowy Zheng #address-cells = <1>; 2102c796fc8SIcenowy Zheng #size-cells = <1>; 2112c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 2122c796fc8SIcenowy Zheng 2132c796fc8SIcenowy Zheng display_clocks: clock@0 { 2142c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 2152c796fc8SIcenowy Zheng reg = <0x0 0x100000>; 2165ea40f71SMaxime Ripard clocks = <&ccu CLK_BUS_DE>, 2175ea40f71SMaxime Ripard <&ccu CLK_DE>; 2185ea40f71SMaxime Ripard clock-names = "bus", 2195ea40f71SMaxime Ripard "mod"; 2202c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 2212c796fc8SIcenowy Zheng #clock-cells = <1>; 2222c796fc8SIcenowy Zheng #reset-cells = <1>; 2232c796fc8SIcenowy Zheng }; 224e85f28e0SJagan Teki 225e85f28e0SJagan Teki mixer0: mixer@100000 { 226e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 227e85f28e0SJagan Teki reg = <0x100000 0x100000>; 228e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 229e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 230e85f28e0SJagan Teki clock-names = "bus", 231e85f28e0SJagan Teki "mod"; 232e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 233e85f28e0SJagan Teki 234e85f28e0SJagan Teki ports { 235e85f28e0SJagan Teki #address-cells = <1>; 236e85f28e0SJagan Teki #size-cells = <0>; 237e85f28e0SJagan Teki 238e85f28e0SJagan Teki mixer0_out: port@1 { 239a7f7047fSMaxime Ripard #address-cells = <1>; 240a7f7047fSMaxime Ripard #size-cells = <0>; 241e85f28e0SJagan Teki reg = <1>; 242e85f28e0SJagan Teki 243a7f7047fSMaxime Ripard mixer0_out_tcon0: endpoint@0 { 244a7f7047fSMaxime Ripard reg = <0>; 245e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 246e85f28e0SJagan Teki }; 247a7f7047fSMaxime Ripard 248a7f7047fSMaxime Ripard mixer0_out_tcon1: endpoint@1 { 249a7f7047fSMaxime Ripard reg = <1>; 250a7f7047fSMaxime Ripard remote-endpoint = <&tcon1_in_mixer0>; 251a7f7047fSMaxime Ripard }; 252e85f28e0SJagan Teki }; 253e85f28e0SJagan Teki }; 254e85f28e0SJagan Teki }; 255e85f28e0SJagan Teki 256e85f28e0SJagan Teki mixer1: mixer@200000 { 257e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 258e85f28e0SJagan Teki reg = <0x200000 0x100000>; 259e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 260e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 261e85f28e0SJagan Teki clock-names = "bus", 262e85f28e0SJagan Teki "mod"; 263e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 264e85f28e0SJagan Teki 265e85f28e0SJagan Teki ports { 266e85f28e0SJagan Teki #address-cells = <1>; 267e85f28e0SJagan Teki #size-cells = <0>; 268e85f28e0SJagan Teki 269e85f28e0SJagan Teki mixer1_out: port@1 { 270d41a43a0SMaxime Ripard #address-cells = <1>; 271d41a43a0SMaxime Ripard #size-cells = <0>; 272e85f28e0SJagan Teki reg = <1>; 273e85f28e0SJagan Teki 274a7f7047fSMaxime Ripard mixer1_out_tcon0: endpoint@0 { 275a7f7047fSMaxime Ripard reg = <0>; 276a7f7047fSMaxime Ripard remote-endpoint = <&tcon0_in_mixer1>; 277a7f7047fSMaxime Ripard }; 278a7f7047fSMaxime Ripard 279a7f7047fSMaxime Ripard mixer1_out_tcon1: endpoint@1 { 280a7f7047fSMaxime Ripard reg = <1>; 281e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 282e85f28e0SJagan Teki }; 283e85f28e0SJagan Teki }; 284e85f28e0SJagan Teki }; 285e85f28e0SJagan Teki }; 2862c796fc8SIcenowy Zheng }; 2872c796fc8SIcenowy Zheng 28879b95360SCorentin Labbe syscon: syscon@1c00000 { 2891f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 29079b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 2911f1f5183SIcenowy Zheng #address-cells = <1>; 2921f1f5183SIcenowy Zheng #size-cells = <1>; 2931f1f5183SIcenowy Zheng ranges; 2941f1f5183SIcenowy Zheng 2951f1f5183SIcenowy Zheng sram_c: sram@18000 { 2961f1f5183SIcenowy Zheng compatible = "mmio-sram"; 2971f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 2981f1f5183SIcenowy Zheng #address-cells = <1>; 2991f1f5183SIcenowy Zheng #size-cells = <1>; 3001f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 3011f1f5183SIcenowy Zheng 3021f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 3031f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 3041f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 3051f1f5183SIcenowy Zheng }; 3061f1f5183SIcenowy Zheng }; 307106deea8SPaul Kocialkowski 308106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 309106deea8SPaul Kocialkowski compatible = "mmio-sram"; 310106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 311106deea8SPaul Kocialkowski #address-cells = <1>; 312106deea8SPaul Kocialkowski #size-cells = <1>; 313106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 314106deea8SPaul Kocialkowski 315106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 316106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 317106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 318106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 319106deea8SPaul Kocialkowski }; 320106deea8SPaul Kocialkowski }; 32179b95360SCorentin Labbe }; 32279b95360SCorentin Labbe 323c32637e0SStefan Brüns dma: dma-controller@1c02000 { 324c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 325c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 326c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 327c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 328c32637e0SStefan Brüns dma-channels = <8>; 329c32637e0SStefan Brüns dma-requests = <27>; 330c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 331c32637e0SStefan Brüns #dma-cells = <1>; 332c32637e0SStefan Brüns }; 333c32637e0SStefan Brüns 334e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 335e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 336e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 337e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 338e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 339e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 340e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 341e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 34226c609d5SMaxime Ripard #clock-cells = <0>; 343e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 344e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 345e85f28e0SJagan Teki 346e85f28e0SJagan Teki ports { 347e85f28e0SJagan Teki #address-cells = <1>; 348e85f28e0SJagan Teki #size-cells = <0>; 349e85f28e0SJagan Teki 350e85f28e0SJagan Teki tcon0_in: port@0 { 351e85f28e0SJagan Teki #address-cells = <1>; 352e85f28e0SJagan Teki #size-cells = <0>; 353e85f28e0SJagan Teki reg = <0>; 354e85f28e0SJagan Teki 355e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 356e85f28e0SJagan Teki reg = <0>; 357e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 358e85f28e0SJagan Teki }; 359a7f7047fSMaxime Ripard 360a7f7047fSMaxime Ripard tcon0_in_mixer1: endpoint@1 { 361a7f7047fSMaxime Ripard reg = <1>; 362d41a43a0SMaxime Ripard remote-endpoint = <&mixer1_out_tcon0>; 363a7f7047fSMaxime Ripard }; 364e85f28e0SJagan Teki }; 365e85f28e0SJagan Teki 366e85f28e0SJagan Teki tcon0_out: port@1 { 367e85f28e0SJagan Teki #address-cells = <1>; 368e85f28e0SJagan Teki #size-cells = <0>; 369e85f28e0SJagan Teki reg = <1>; 370e85f28e0SJagan Teki }; 371e85f28e0SJagan Teki }; 372e85f28e0SJagan Teki }; 373e85f28e0SJagan Teki 374e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 375e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 376e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 377e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 378e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 379e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 380e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 381e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 382e85f28e0SJagan Teki reset-names = "lcd"; 383e85f28e0SJagan Teki 384e85f28e0SJagan Teki ports { 385e85f28e0SJagan Teki #address-cells = <1>; 386e85f28e0SJagan Teki #size-cells = <0>; 387e85f28e0SJagan Teki 388e85f28e0SJagan Teki tcon1_in: port@0 { 389a7f7047fSMaxime Ripard #address-cells = <1>; 390a7f7047fSMaxime Ripard #size-cells = <0>; 391e85f28e0SJagan Teki reg = <0>; 392e85f28e0SJagan Teki 393a7f7047fSMaxime Ripard tcon1_in_mixer0: endpoint@0 { 394a7f7047fSMaxime Ripard reg = <0>; 395a7f7047fSMaxime Ripard remote-endpoint = <&mixer0_out_tcon1>; 396a7f7047fSMaxime Ripard }; 397a7f7047fSMaxime Ripard 398a7f7047fSMaxime Ripard tcon1_in_mixer1: endpoint@1 { 399a7f7047fSMaxime Ripard reg = <1>; 400e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 401e85f28e0SJagan Teki }; 402e85f28e0SJagan Teki }; 403e85f28e0SJagan Teki 404e85f28e0SJagan Teki tcon1_out: port@1 { 405e85f28e0SJagan Teki #address-cells = <1>; 406e85f28e0SJagan Teki #size-cells = <0>; 407e85f28e0SJagan Teki reg = <1>; 408e85f28e0SJagan Teki 409e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 410e85f28e0SJagan Teki reg = <1>; 411e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 412e85f28e0SJagan Teki }; 413e85f28e0SJagan Teki }; 414e85f28e0SJagan Teki }; 415e85f28e0SJagan Teki }; 416e85f28e0SJagan Teki 417d60ce247SPaul Kocialkowski video-codec@1c0e000 { 4184ab88516SPaul Kocialkowski compatible = "allwinner,sun50i-a64-video-engine"; 419d60ce247SPaul Kocialkowski reg = <0x01c0e000 0x1000>; 420d60ce247SPaul Kocialkowski clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 421d60ce247SPaul Kocialkowski <&ccu CLK_DRAM_VE>; 422d60ce247SPaul Kocialkowski clock-names = "ahb", "mod", "ram"; 423d60ce247SPaul Kocialkowski resets = <&ccu RST_BUS_VE>; 424d60ce247SPaul Kocialkowski interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 425d60ce247SPaul Kocialkowski allwinner,sram = <&ve_sram 1>; 426d60ce247SPaul Kocialkowski }; 427d60ce247SPaul Kocialkowski 428f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 429f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 430f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 431f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 432f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 433f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 434f3dff347SAndre Przywara reset-names = "ahb"; 435f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 43622be992fSMaxime Ripard max-frequency = <150000000>; 437f3dff347SAndre Przywara status = "disabled"; 438f3dff347SAndre Przywara #address-cells = <1>; 439f3dff347SAndre Przywara #size-cells = <0>; 440f3dff347SAndre Przywara }; 441f3dff347SAndre Przywara 442f3dff347SAndre Przywara mmc1: mmc@1c10000 { 443f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 444f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 445f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 446f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 447f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 448f3dff347SAndre Przywara reset-names = "ahb"; 449f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 45022be992fSMaxime Ripard max-frequency = <150000000>; 451f3dff347SAndre Przywara status = "disabled"; 452f3dff347SAndre Przywara #address-cells = <1>; 453f3dff347SAndre Przywara #size-cells = <0>; 454f3dff347SAndre Przywara }; 455f3dff347SAndre Przywara 456f3dff347SAndre Przywara mmc2: mmc@1c11000 { 457f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 458f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 459f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 460f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 461f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 462f3dff347SAndre Przywara reset-names = "ahb"; 463f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 46422be992fSMaxime Ripard max-frequency = <200000000>; 465f3dff347SAndre Przywara status = "disabled"; 466f3dff347SAndre Przywara #address-cells = <1>; 467f3dff347SAndre Przywara #size-cells = <0>; 468f3dff347SAndre Przywara }; 469f3dff347SAndre Przywara 470ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 471ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 472ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 47359f5e9b9SVasily Khoruzhick #address-cells = <1>; 47459f5e9b9SVasily Khoruzhick #size-cells = <1>; 47559f5e9b9SVasily Khoruzhick 47659f5e9b9SVasily Khoruzhick ths_calibration: thermal-sensor-calibration@34 { 47759f5e9b9SVasily Khoruzhick reg = <0x34 0x8>; 47859f5e9b9SVasily Khoruzhick }; 479ac947b17SEmmanuel Vadot }; 480ac947b17SEmmanuel Vadot 4810f5fc158SCorentin Labbe crypto: crypto@1c15000 { 4820f5fc158SCorentin Labbe compatible = "allwinner,sun50i-a64-crypto"; 4830f5fc158SCorentin Labbe reg = <0x01c15000 0x1000>; 4840f5fc158SCorentin Labbe interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 4850f5fc158SCorentin Labbe clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 4860f5fc158SCorentin Labbe clock-names = "bus", "mod"; 4870f5fc158SCorentin Labbe resets = <&ccu RST_BUS_CE>; 4880f5fc158SCorentin Labbe }; 4890f5fc158SCorentin Labbe 490d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 491972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 492972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 493972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 494972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 495972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 496972a3ecdSIcenowy Zheng interrupt-names = "mc"; 497972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 498972a3ecdSIcenowy Zheng phy-names = "usb"; 499972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 5000973c06bSMaxime Ripard dr_mode = "otg"; 501972a3ecdSIcenowy Zheng status = "disabled"; 502972a3ecdSIcenowy Zheng }; 503972a3ecdSIcenowy Zheng 504d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 505a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 506a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 5070d984797SIcenowy Zheng <0x01c1a800 0x4>, 508a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 509a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 5100d984797SIcenowy Zheng "pmu0", 511a004ee35SIcenowy Zheng "pmu1"; 512a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 513a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 514a004ee35SIcenowy Zheng clock-names = "usb0_phy", 515a004ee35SIcenowy Zheng "usb1_phy"; 516a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 517a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 518a004ee35SIcenowy Zheng reset-names = "usb0_reset", 519a004ee35SIcenowy Zheng "usb1_reset"; 520a004ee35SIcenowy Zheng status = "disabled"; 521a004ee35SIcenowy Zheng #phy-cells = <1>; 522a004ee35SIcenowy Zheng }; 523a004ee35SIcenowy Zheng 524d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 525dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 526dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 527dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 528dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 529dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 530dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 531dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 532dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 533dc03a047SIcenowy Zheng status = "disabled"; 534dc03a047SIcenowy Zheng }; 535dc03a047SIcenowy Zheng 536d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 537dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 538dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 539dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 540dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 541dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 542dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 543dc03a047SIcenowy Zheng status = "disabled"; 544dc03a047SIcenowy Zheng }; 545dc03a047SIcenowy Zheng 546d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 547a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 548a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 549a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 550a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 551a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 552a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 553a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 554a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 555a004ee35SIcenowy Zheng phys = <&usbphy 1>; 556e6064cf4SMaxime Ripard phy-names = "usb"; 557a004ee35SIcenowy Zheng status = "disabled"; 558a004ee35SIcenowy Zheng }; 559a004ee35SIcenowy Zheng 560d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 561a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 562a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 563a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 564a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 565a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 566a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 567a004ee35SIcenowy Zheng phys = <&usbphy 1>; 568e6064cf4SMaxime Ripard phy-names = "usb"; 569a004ee35SIcenowy Zheng status = "disabled"; 570a004ee35SIcenowy Zheng }; 571a004ee35SIcenowy Zheng 572d6c9da12SCorentin LABBE ccu: clock@1c20000 { 5736bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 5746bc37facSAndre Przywara reg = <0x01c20000 0x400>; 57544ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>; 5766bc37facSAndre Przywara clock-names = "hosc", "losc"; 5776bc37facSAndre Przywara #clock-cells = <1>; 5786bc37facSAndre Przywara #reset-cells = <1>; 5796bc37facSAndre Przywara }; 5806bc37facSAndre Przywara 5816bc37facSAndre Przywara pio: pinctrl@1c20800 { 5826bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 5836bc37facSAndre Przywara reg = <0x01c20800 0x400>; 5846bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 5856bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 5866bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 587562bf196SMaxime Ripard clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 588562bf196SMaxime Ripard clock-names = "apb", "hosc", "losc"; 5896bc37facSAndre Przywara gpio-controller; 5906bc37facSAndre Przywara #gpio-cells = <3>; 5916bc37facSAndre Przywara interrupt-controller; 5926bc37facSAndre Przywara #interrupt-cells = <3>; 5936bc37facSAndre Przywara 594ff29f13eSJagan Teki csi_pins: csi-pins { 595ff29f13eSJagan Teki pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 596ff29f13eSJagan Teki "PE7", "PE8", "PE9", "PE10", "PE11"; 597ff29f13eSJagan Teki function = "csi"; 598ff29f13eSJagan Teki }; 599ff29f13eSJagan Teki 600f7056b28SJagan Teki /omit-if-no-ref/ 601f7056b28SJagan Teki csi_mclk_pin: csi-mclk-pin { 602f7056b28SJagan Teki pins = "PE1"; 603f7056b28SJagan Teki function = "csi"; 604f7056b28SJagan Teki }; 605f7056b28SJagan Teki 60654eac67bSMaxime Ripard i2c0_pins: i2c0-pins { 60711239fe6SHarald Geyer pins = "PH0", "PH1"; 60811239fe6SHarald Geyer function = "i2c0"; 60911239fe6SHarald Geyer }; 61011239fe6SHarald Geyer 61154eac67bSMaxime Ripard i2c1_pins: i2c1-pins { 6126bc37facSAndre Przywara pins = "PH2", "PH3"; 6136bc37facSAndre Przywara function = "i2c1"; 6146bc37facSAndre Przywara }; 6156bc37facSAndre Przywara 616c478a12eSIcenowy Zheng /omit-if-no-ref/ 617c478a12eSIcenowy Zheng lcd_rgb666_pins: lcd-rgb666-pins { 618c478a12eSIcenowy Zheng pins = "PD0", "PD1", "PD2", "PD3", "PD4", 619c478a12eSIcenowy Zheng "PD5", "PD6", "PD7", "PD8", "PD9", 620c478a12eSIcenowy Zheng "PD10", "PD11", "PD12", "PD13", 621c478a12eSIcenowy Zheng "PD14", "PD15", "PD16", "PD17", 622c478a12eSIcenowy Zheng "PD18", "PD19", "PD20", "PD21"; 623c478a12eSIcenowy Zheng function = "lcd0"; 624c478a12eSIcenowy Zheng }; 625c478a12eSIcenowy Zheng 626a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 627a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 628a3e8f492SMaxime Ripard "PF4", "PF5"; 629a3e8f492SMaxime Ripard function = "mmc0"; 630a3e8f492SMaxime Ripard drive-strength = <30>; 631a3e8f492SMaxime Ripard bias-pull-up; 632a3e8f492SMaxime Ripard }; 633a3e8f492SMaxime Ripard 634a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 635a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 636a3e8f492SMaxime Ripard "PG4", "PG5"; 637a3e8f492SMaxime Ripard function = "mmc1"; 638a3e8f492SMaxime Ripard drive-strength = <30>; 639a3e8f492SMaxime Ripard bias-pull-up; 640a3e8f492SMaxime Ripard }; 641a3e8f492SMaxime Ripard 642a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 643fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 644a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 645a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 646a3e8f492SMaxime Ripard function = "mmc2"; 647a3e8f492SMaxime Ripard drive-strength = <30>; 648a3e8f492SMaxime Ripard bias-pull-up; 649a3e8f492SMaxime Ripard }; 650a3e8f492SMaxime Ripard 651fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 652fa59dd2eSChen-Yu Tsai pins = "PC1"; 653fa59dd2eSChen-Yu Tsai function = "mmc2"; 654fa59dd2eSChen-Yu Tsai drive-strength = <30>; 655fa59dd2eSChen-Yu Tsai bias-pull-up; 656fa59dd2eSChen-Yu Tsai }; 657fa59dd2eSChen-Yu Tsai 65854eac67bSMaxime Ripard pwm_pin: pwm-pin { 659b5df280bSAndre Przywara pins = "PD22"; 660b5df280bSAndre Przywara function = "pwm"; 661b5df280bSAndre Przywara }; 662b5df280bSAndre Przywara 66354eac67bSMaxime Ripard rmii_pins: rmii-pins { 664e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 665e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 666e53f67e9SCorentin Labbe function = "emac"; 667e53f67e9SCorentin Labbe drive-strength = <40>; 668e53f67e9SCorentin Labbe }; 669e53f67e9SCorentin Labbe 67054eac67bSMaxime Ripard rgmii_pins: rgmii-pins { 671e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 672e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 673e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 674e53f67e9SCorentin Labbe function = "emac"; 675e53f67e9SCorentin Labbe drive-strength = <40>; 676e53f67e9SCorentin Labbe }; 677e53f67e9SCorentin Labbe 67854eac67bSMaxime Ripard spdif_tx_pin: spdif-tx-pin { 679b399d2acSMarcus Cooper pins = "PH8"; 680b399d2acSMarcus Cooper function = "spdif"; 681b399d2acSMarcus Cooper }; 682b399d2acSMarcus Cooper 68354eac67bSMaxime Ripard spi0_pins: spi0-pins { 684b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 685b518bb15SStefan Brüns function = "spi0"; 686b518bb15SStefan Brüns }; 687b518bb15SStefan Brüns 68854eac67bSMaxime Ripard spi1_pins: spi1-pins { 689b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 690b518bb15SStefan Brüns function = "spi1"; 691b518bb15SStefan Brüns }; 692b518bb15SStefan Brüns 693d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 6946bc37facSAndre Przywara pins = "PB8", "PB9"; 6956bc37facSAndre Przywara function = "uart0"; 6966bc37facSAndre Przywara }; 697e7ba733dSAndre Przywara 69854eac67bSMaxime Ripard uart1_pins: uart1-pins { 699e7ba733dSAndre Przywara pins = "PG6", "PG7"; 700e7ba733dSAndre Przywara function = "uart1"; 701e7ba733dSAndre Przywara }; 702e7ba733dSAndre Przywara 70354eac67bSMaxime Ripard uart1_rts_cts_pins: uart1-rts-cts-pins { 704e7ba733dSAndre Przywara pins = "PG8", "PG9"; 705e7ba733dSAndre Przywara function = "uart1"; 706e7ba733dSAndre Przywara }; 70779825719SAndreas Färber 70879825719SAndreas Färber uart2_pins: uart2-pins { 70979825719SAndreas Färber pins = "PB0", "PB1"; 71079825719SAndreas Färber function = "uart2"; 71179825719SAndreas Färber }; 7122273aa16SAndreas Färber 7132273aa16SAndreas Färber uart3_pins: uart3-pins { 7142273aa16SAndreas Färber pins = "PD0", "PD1"; 7152273aa16SAndreas Färber function = "uart3"; 7162273aa16SAndreas Färber }; 7172273aa16SAndreas Färber 7182273aa16SAndreas Färber uart4_pins: uart4-pins { 7192273aa16SAndreas Färber pins = "PD2", "PD3"; 7202273aa16SAndreas Färber function = "uart4"; 7212273aa16SAndreas Färber }; 7222273aa16SAndreas Färber 7232273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 7242273aa16SAndreas Färber pins = "PD4", "PD5"; 7252273aa16SAndreas Färber function = "uart4"; 7262273aa16SAndreas Färber }; 7276bc37facSAndre Przywara }; 7286bc37facSAndre Przywara 729b399d2acSMarcus Cooper spdif: spdif@1c21000 { 730b399d2acSMarcus Cooper #sound-dai-cells = <0>; 731b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 732b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 733b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 734b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 735b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 736b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 737b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 738b399d2acSMarcus Cooper dmas = <&dma 2>; 739b399d2acSMarcus Cooper dma-names = "tx"; 740b399d2acSMarcus Cooper pinctrl-names = "default"; 741b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 742b399d2acSMarcus Cooper status = "disabled"; 743b399d2acSMarcus Cooper }; 744b399d2acSMarcus Cooper 74584204fb6SLuca Weiss lradc: lradc@1c21800 { 74684204fb6SLuca Weiss compatible = "allwinner,sun50i-a64-lradc", 74784204fb6SLuca Weiss "allwinner,sun8i-a83t-r-lradc"; 74884204fb6SLuca Weiss reg = <0x01c21800 0x400>; 74984204fb6SLuca Weiss interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 75084204fb6SLuca Weiss status = "disabled"; 75184204fb6SLuca Weiss }; 75284204fb6SLuca Weiss 7531c92c009SMarcus Cooper i2s0: i2s@1c22000 { 7541c92c009SMarcus Cooper #sound-dai-cells = <0>; 7551c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 7561c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 7571c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 7581c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7591c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 7601c92c009SMarcus Cooper clock-names = "apb", "mod"; 7611c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 7621c92c009SMarcus Cooper dma-names = "rx", "tx"; 7631c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 7641c92c009SMarcus Cooper status = "disabled"; 7651c92c009SMarcus Cooper }; 7661c92c009SMarcus Cooper 7671c92c009SMarcus Cooper i2s1: i2s@1c22400 { 7681c92c009SMarcus Cooper #sound-dai-cells = <0>; 7691c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 7701c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 7711c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 7721c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7731c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 7741c92c009SMarcus Cooper clock-names = "apb", "mod"; 7751c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 7761c92c009SMarcus Cooper dma-names = "rx", "tx"; 7771c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 7781c92c009SMarcus Cooper status = "disabled"; 7791c92c009SMarcus Cooper }; 7801c92c009SMarcus Cooper 781ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 782ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 783ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 784ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 785ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 786ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 787ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 788ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 789ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 790ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 791ec4a9540SVasily Khoruzhick status = "disabled"; 792ec4a9540SVasily Khoruzhick }; 793ec4a9540SVasily Khoruzhick 794ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 795ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 796ec4a9540SVasily Khoruzhick compatible = "allwinner,sun8i-a33-codec"; 797ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 798ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 799ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 800ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 801ec4a9540SVasily Khoruzhick status = "disabled"; 802ec4a9540SVasily Khoruzhick }; 803ec4a9540SVasily Khoruzhick 80459f5e9b9SVasily Khoruzhick ths: thermal-sensor@1c25000 { 80559f5e9b9SVasily Khoruzhick compatible = "allwinner,sun50i-a64-ths"; 80659f5e9b9SVasily Khoruzhick reg = <0x01c25000 0x100>; 80759f5e9b9SVasily Khoruzhick clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 80859f5e9b9SVasily Khoruzhick clock-names = "bus", "mod"; 80959f5e9b9SVasily Khoruzhick interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 81059f5e9b9SVasily Khoruzhick resets = <&ccu RST_BUS_THS>; 81159f5e9b9SVasily Khoruzhick nvmem-cells = <&ths_calibration>; 81259f5e9b9SVasily Khoruzhick nvmem-cell-names = "calibration"; 81359f5e9b9SVasily Khoruzhick #thermal-sensor-cells = <1>; 81459f5e9b9SVasily Khoruzhick }; 81559f5e9b9SVasily Khoruzhick 8166bc37facSAndre Przywara uart0: serial@1c28000 { 8176bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8186bc37facSAndre Przywara reg = <0x01c28000 0x400>; 8196bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8206bc37facSAndre Przywara reg-shift = <2>; 8216bc37facSAndre Przywara reg-io-width = <4>; 822494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 823494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 8246bc37facSAndre Przywara status = "disabled"; 8256bc37facSAndre Przywara }; 8266bc37facSAndre Przywara 8276bc37facSAndre Przywara uart1: serial@1c28400 { 8286bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8296bc37facSAndre Przywara reg = <0x01c28400 0x400>; 8306bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 8316bc37facSAndre Przywara reg-shift = <2>; 8326bc37facSAndre Przywara reg-io-width = <4>; 833494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 834494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 8356bc37facSAndre Przywara status = "disabled"; 8366bc37facSAndre Przywara }; 8376bc37facSAndre Przywara 8386bc37facSAndre Przywara uart2: serial@1c28800 { 8396bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8406bc37facSAndre Przywara reg = <0x01c28800 0x400>; 8416bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 8426bc37facSAndre Przywara reg-shift = <2>; 8436bc37facSAndre Przywara reg-io-width = <4>; 844494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 845494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 8466bc37facSAndre Przywara status = "disabled"; 8476bc37facSAndre Przywara }; 8486bc37facSAndre Przywara 8496bc37facSAndre Przywara uart3: serial@1c28c00 { 8506bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8516bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 8526bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 8536bc37facSAndre Przywara reg-shift = <2>; 8546bc37facSAndre Przywara reg-io-width = <4>; 855494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 856494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 8576bc37facSAndre Przywara status = "disabled"; 8586bc37facSAndre Przywara }; 8596bc37facSAndre Przywara 8606bc37facSAndre Przywara uart4: serial@1c29000 { 8616bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8626bc37facSAndre Przywara reg = <0x01c29000 0x400>; 8636bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 8646bc37facSAndre Przywara reg-shift = <2>; 8656bc37facSAndre Przywara reg-io-width = <4>; 866494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 867494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 8686bc37facSAndre Przywara status = "disabled"; 8696bc37facSAndre Przywara }; 8706bc37facSAndre Przywara 8716bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 8726bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8736bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 8746bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 875494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 876494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 87770f76289SJagan Teki pinctrl-names = "default"; 87870f76289SJagan Teki pinctrl-0 = <&i2c0_pins>; 8796bc37facSAndre Przywara status = "disabled"; 8806bc37facSAndre Przywara #address-cells = <1>; 8816bc37facSAndre Przywara #size-cells = <0>; 8826bc37facSAndre Przywara }; 8836bc37facSAndre Przywara 8846bc37facSAndre Przywara i2c1: i2c@1c2b000 { 8856bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8866bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 8876bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 888494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 889494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 89070f76289SJagan Teki pinctrl-names = "default"; 89170f76289SJagan Teki pinctrl-0 = <&i2c1_pins>; 8926bc37facSAndre Przywara status = "disabled"; 8936bc37facSAndre Przywara #address-cells = <1>; 8946bc37facSAndre Przywara #size-cells = <0>; 8956bc37facSAndre Przywara }; 8966bc37facSAndre Przywara 8976bc37facSAndre Przywara i2c2: i2c@1c2b400 { 8986bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8996bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 9006bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 901494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 902494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 9036bc37facSAndre Przywara status = "disabled"; 9046bc37facSAndre Przywara #address-cells = <1>; 9056bc37facSAndre Przywara #size-cells = <0>; 9066bc37facSAndre Przywara }; 9076bc37facSAndre Przywara 908b518bb15SStefan Brüns 909d6c9da12SCorentin LABBE spi0: spi@1c68000 { 910b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 911b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 912b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 913b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 914b518bb15SStefan Brüns clock-names = "ahb", "mod"; 91506c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 91606c1258aSStefan Brüns dma-names = "rx", "tx"; 917b518bb15SStefan Brüns pinctrl-names = "default"; 918b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 919b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 920b518bb15SStefan Brüns status = "disabled"; 921b518bb15SStefan Brüns num-cs = <1>; 922b518bb15SStefan Brüns #address-cells = <1>; 923b518bb15SStefan Brüns #size-cells = <0>; 924b518bb15SStefan Brüns }; 925b518bb15SStefan Brüns 926d6c9da12SCorentin LABBE spi1: spi@1c69000 { 927b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 928b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 929b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 930b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 931b518bb15SStefan Brüns clock-names = "ahb", "mod"; 93206c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 93306c1258aSStefan Brüns dma-names = "rx", "tx"; 934b518bb15SStefan Brüns pinctrl-names = "default"; 935b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 936b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 937b518bb15SStefan Brüns status = "disabled"; 938b518bb15SStefan Brüns num-cs = <1>; 939b518bb15SStefan Brüns #address-cells = <1>; 940b518bb15SStefan Brüns #size-cells = <0>; 941b518bb15SStefan Brüns }; 942b518bb15SStefan Brüns 94394f44288SCorentin Labbe emac: ethernet@1c30000 { 94494f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 94594f44288SCorentin Labbe syscon = <&syscon>; 94694f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 94794f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 94894f44288SCorentin Labbe interrupt-names = "macirq"; 94994f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 95094f44288SCorentin Labbe reset-names = "stmmaceth"; 95194f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 95294f44288SCorentin Labbe clock-names = "stmmaceth"; 95394f44288SCorentin Labbe status = "disabled"; 95494f44288SCorentin Labbe 95594f44288SCorentin Labbe mdio: mdio { 95616416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 95794f44288SCorentin Labbe #address-cells = <1>; 95894f44288SCorentin Labbe #size-cells = <0>; 95994f44288SCorentin Labbe }; 96094f44288SCorentin Labbe }; 96194f44288SCorentin Labbe 9626b683d76SJagan Teki mali: gpu@1c40000 { 9636b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 9646b683d76SJagan Teki reg = <0x01c40000 0x10000>; 9656b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 9666b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 9676b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 9686b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 9696b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 9706b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 9716b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 9726b683d76SJagan Teki interrupt-names = "gp", 9736b683d76SJagan Teki "gpmmu", 9746b683d76SJagan Teki "pp0", 9756b683d76SJagan Teki "ppmmu0", 9766b683d76SJagan Teki "pp1", 9776b683d76SJagan Teki "ppmmu1", 9786b683d76SJagan Teki "pmu"; 9796b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 9806b683d76SJagan Teki clock-names = "bus", "core"; 9816b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 9826b683d76SJagan Teki }; 9836b683d76SJagan Teki 9846bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 9856bc37facSAndre Przywara compatible = "arm,gic-400"; 9866bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 9876bc37facSAndre Przywara <0x01c82000 0x2000>, 9886bc37facSAndre Przywara <0x01c84000 0x2000>, 9896bc37facSAndre Przywara <0x01c86000 0x2000>; 9906bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 9916bc37facSAndre Przywara interrupt-controller; 9926bc37facSAndre Przywara #interrupt-cells = <3>; 9936bc37facSAndre Przywara }; 9946bc37facSAndre Przywara 995b5df280bSAndre Przywara pwm: pwm@1c21400 { 996b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 997b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 998b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 999b5df280bSAndre Przywara clocks = <&osc24M>; 1000b5df280bSAndre Przywara pinctrl-names = "default"; 1001b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 1002b5df280bSAndre Przywara #pwm-cells = <3>; 1003b5df280bSAndre Przywara status = "disabled"; 1004b5df280bSAndre Przywara }; 1005b5df280bSAndre Przywara 1006ff29f13eSJagan Teki csi: csi@1cb0000 { 1007ff29f13eSJagan Teki compatible = "allwinner,sun50i-a64-csi"; 1008ff29f13eSJagan Teki reg = <0x01cb0000 0x1000>; 1009ff29f13eSJagan Teki interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1010ff29f13eSJagan Teki clocks = <&ccu CLK_BUS_CSI>, 1011ff29f13eSJagan Teki <&ccu CLK_CSI_SCLK>, 1012ff29f13eSJagan Teki <&ccu CLK_DRAM_CSI>; 1013ff29f13eSJagan Teki clock-names = "bus", "mod", "ram"; 1014ff29f13eSJagan Teki resets = <&ccu RST_BUS_CSI>; 1015ff29f13eSJagan Teki pinctrl-names = "default"; 1016ff29f13eSJagan Teki pinctrl-0 = <&csi_pins>; 1017ff29f13eSJagan Teki status = "disabled"; 1018ff29f13eSJagan Teki }; 1019ff29f13eSJagan Teki 1020e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 1021e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 1022e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 1023e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 1024e85f28e0SJagan Teki reg-io-width = <1>; 1025e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1026e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1027e85f28e0SJagan Teki <&ccu CLK_HDMI>; 1028e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 1029e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 1030e85f28e0SJagan Teki reset-names = "ctrl"; 1031e85f28e0SJagan Teki phys = <&hdmi_phy>; 1032d40113fbSMaxime Ripard phy-names = "phy"; 1033e85f28e0SJagan Teki status = "disabled"; 1034e85f28e0SJagan Teki 1035e85f28e0SJagan Teki ports { 1036e85f28e0SJagan Teki #address-cells = <1>; 1037e85f28e0SJagan Teki #size-cells = <0>; 1038e85f28e0SJagan Teki 1039e85f28e0SJagan Teki hdmi_in: port@0 { 1040e85f28e0SJagan Teki reg = <0>; 1041e85f28e0SJagan Teki 1042e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 1043e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 1044e85f28e0SJagan Teki }; 1045e85f28e0SJagan Teki }; 1046e85f28e0SJagan Teki 1047e85f28e0SJagan Teki hdmi_out: port@1 { 1048e85f28e0SJagan Teki reg = <1>; 1049e85f28e0SJagan Teki }; 1050e85f28e0SJagan Teki }; 1051e85f28e0SJagan Teki }; 1052e85f28e0SJagan Teki 1053e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 1054e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 1055e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 1056e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1057e85f28e0SJagan Teki <&ccu 7>; 1058e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 1059e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 1060e85f28e0SJagan Teki reset-names = "phy"; 1061e85f28e0SJagan Teki #phy-cells = <0>; 1062e85f28e0SJagan Teki }; 1063e85f28e0SJagan Teki 10646bc37facSAndre Przywara rtc: rtc@1f00000 { 106544ff3cafSChen-Yu Tsai compatible = "allwinner,sun50i-a64-rtc", 106644ff3cafSChen-Yu Tsai "allwinner,sun8i-h3-rtc"; 106744ff3cafSChen-Yu Tsai reg = <0x01f00000 0x400>; 10686bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 10696bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 107044ff3cafSChen-Yu Tsai clock-output-names = "osc32k", "osc32k-out", "iosc"; 1071e1a9a474SJagan Teki clocks = <&osc32k>; 1072e1a9a474SJagan Teki #clock-cells = <1>; 10736bc37facSAndre Przywara }; 1074791a9e00SIcenowy Zheng 1075535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 1076535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 1077535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 1078535ca508SIcenowy Zheng interrupt-controller; 1079535ca508SIcenowy Zheng #interrupt-cells = <2>; 1080535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 1081535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1082535ca508SIcenowy Zheng }; 1083535ca508SIcenowy Zheng 1084791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 1085791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 1086791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 108744ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1088f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 1089791a9e00SIcenowy Zheng #clock-cells = <1>; 1090791a9e00SIcenowy Zheng #reset-cells = <1>; 1091791a9e00SIcenowy Zheng }; 1092ec427905SIcenowy Zheng 1093ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 1094ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 1095ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 1096ec4a9540SVasily Khoruzhick status = "disabled"; 1097ec4a9540SVasily Khoruzhick }; 1098ec4a9540SVasily Khoruzhick 1099871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 1100871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 1101871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 1102871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 1103871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1104871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1105871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1106871b5352SIcenowy Zheng status = "disabled"; 1107871b5352SIcenowy Zheng #address-cells = <1>; 1108871b5352SIcenowy Zheng #size-cells = <0>; 1109871b5352SIcenowy Zheng }; 1110871b5352SIcenowy Zheng 111144a4f416SIgors Makejevs r_ir: ir@1f02000 { 111244a4f416SIgors Makejevs compatible = "allwinner,sun50i-a64-ir", 111344a4f416SIgors Makejevs "allwinner,sun6i-a31-ir"; 111444a4f416SIgors Makejevs reg = <0x01f02000 0x400>; 111544a4f416SIgors Makejevs clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 111644a4f416SIgors Makejevs clock-names = "apb", "ir"; 111744a4f416SIgors Makejevs resets = <&r_ccu RST_APB0_IR>; 111844a4f416SIgors Makejevs interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 111944a4f416SIgors Makejevs pinctrl-names = "default"; 112044a4f416SIgors Makejevs pinctrl-0 = <&r_ir_rx_pin>; 112144a4f416SIgors Makejevs status = "disabled"; 112244a4f416SIgors Makejevs }; 112344a4f416SIgors Makejevs 1124b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1125b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1126b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1127b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1128b5df280bSAndre Przywara clocks = <&osc24M>; 1129b5df280bSAndre Przywara pinctrl-names = "default"; 1130b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1131b5df280bSAndre Przywara #pwm-cells = <3>; 1132b5df280bSAndre Przywara status = "disabled"; 1133b5df280bSAndre Przywara }; 1134b5df280bSAndre Przywara 1135d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1136ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1137ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1138ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1139494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1140ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1141ec427905SIcenowy Zheng gpio-controller; 1142ec427905SIcenowy Zheng #gpio-cells = <3>; 1143ec427905SIcenowy Zheng interrupt-controller; 1144ec427905SIcenowy Zheng #interrupt-cells = <3>; 11453b38fdedSIcenowy Zheng 11461b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1147871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1148871b5352SIcenowy Zheng function = "s_i2c"; 1149871b5352SIcenowy Zheng }; 1150871b5352SIcenowy Zheng 115144a4f416SIgors Makejevs r_ir_rx_pin: r-ir-rx-pin { 115244a4f416SIgors Makejevs pins = "PL11"; 115344a4f416SIgors Makejevs function = "s_cir_rx"; 115444a4f416SIgors Makejevs }; 115544a4f416SIgors Makejevs 115654eac67bSMaxime Ripard r_pwm_pin: r-pwm-pin { 1157b5df280bSAndre Przywara pins = "PL10"; 1158b5df280bSAndre Przywara function = "s_pwm"; 1159b5df280bSAndre Przywara }; 1160b5df280bSAndre Przywara 116154eac67bSMaxime Ripard r_rsb_pins: r-rsb-pins { 11623b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 11633b38fdedSIcenowy Zheng function = "s_rsb"; 11643b38fdedSIcenowy Zheng }; 11653b38fdedSIcenowy Zheng }; 11663b38fdedSIcenowy Zheng 11673b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 11683b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 11693b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 11703b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 11713b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 11723b38fdedSIcenowy Zheng clock-frequency = <3000000>; 11733b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 11743b38fdedSIcenowy Zheng pinctrl-names = "default"; 11753b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 11763b38fdedSIcenowy Zheng status = "disabled"; 11773b38fdedSIcenowy Zheng #address-cells = <1>; 11783b38fdedSIcenowy Zheng #size-cells = <0>; 1179ec427905SIcenowy Zheng }; 1180d4185043SHarald Geyer 1181d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 1182d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 1183d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 1184d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 1185d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 11869e1975f0SMaxime Ripard clocks = <&osc24M>; 1187d4185043SHarald Geyer }; 11886bc37facSAndre Przywara }; 11896bc37facSAndre Przywara}; 1190