16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 46494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 476bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 48a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 496bc37facSAndre Przywara 506bc37facSAndre Przywara/ { 516bc37facSAndre Przywara interrupt-parent = <&gic>; 526bc37facSAndre Przywara #address-cells = <1>; 536bc37facSAndre Przywara #size-cells = <1>; 546bc37facSAndre Przywara 556bc37facSAndre Przywara cpus { 566bc37facSAndre Przywara #address-cells = <1>; 576bc37facSAndre Przywara #size-cells = <0>; 586bc37facSAndre Przywara 596bc37facSAndre Przywara cpu0: cpu@0 { 606bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 616bc37facSAndre Przywara device_type = "cpu"; 626bc37facSAndre Przywara reg = <0>; 636bc37facSAndre Przywara enable-method = "psci"; 646bc37facSAndre Przywara }; 656bc37facSAndre Przywara 666bc37facSAndre Przywara cpu1: cpu@1 { 676bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 686bc37facSAndre Przywara device_type = "cpu"; 696bc37facSAndre Przywara reg = <1>; 706bc37facSAndre Przywara enable-method = "psci"; 716bc37facSAndre Przywara }; 726bc37facSAndre Przywara 736bc37facSAndre Przywara cpu2: cpu@2 { 746bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 756bc37facSAndre Przywara device_type = "cpu"; 766bc37facSAndre Przywara reg = <2>; 776bc37facSAndre Przywara enable-method = "psci"; 786bc37facSAndre Przywara }; 796bc37facSAndre Przywara 806bc37facSAndre Przywara cpu3: cpu@3 { 816bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 826bc37facSAndre Przywara device_type = "cpu"; 836bc37facSAndre Przywara reg = <3>; 846bc37facSAndre Przywara enable-method = "psci"; 856bc37facSAndre Przywara }; 866bc37facSAndre Przywara }; 876bc37facSAndre Przywara 886bc37facSAndre Przywara osc24M: osc24M_clk { 896bc37facSAndre Przywara #clock-cells = <0>; 906bc37facSAndre Przywara compatible = "fixed-clock"; 916bc37facSAndre Przywara clock-frequency = <24000000>; 926bc37facSAndre Przywara clock-output-names = "osc24M"; 936bc37facSAndre Przywara }; 946bc37facSAndre Przywara 956bc37facSAndre Przywara osc32k: osc32k_clk { 966bc37facSAndre Przywara #clock-cells = <0>; 976bc37facSAndre Przywara compatible = "fixed-clock"; 986bc37facSAndre Przywara clock-frequency = <32768>; 996bc37facSAndre Przywara clock-output-names = "osc32k"; 1006bc37facSAndre Przywara }; 1016bc37facSAndre Przywara 102791a9e00SIcenowy Zheng iosc: internal-osc-clk { 103791a9e00SIcenowy Zheng #clock-cells = <0>; 104791a9e00SIcenowy Zheng compatible = "fixed-clock"; 105791a9e00SIcenowy Zheng clock-frequency = <16000000>; 106791a9e00SIcenowy Zheng clock-accuracy = <300000000>; 107791a9e00SIcenowy Zheng clock-output-names = "iosc"; 108791a9e00SIcenowy Zheng }; 109791a9e00SIcenowy Zheng 1106bc37facSAndre Przywara psci { 1116bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1126bc37facSAndre Przywara method = "smc"; 1136bc37facSAndre Przywara }; 1146bc37facSAndre Przywara 1156bc37facSAndre Przywara timer { 1166bc37facSAndre Przywara compatible = "arm,armv8-timer"; 1176bc37facSAndre Przywara interrupts = <GIC_PPI 13 1186bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1196bc37facSAndre Przywara <GIC_PPI 14 1206bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1216bc37facSAndre Przywara <GIC_PPI 11 1226bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1236bc37facSAndre Przywara <GIC_PPI 10 1246bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1256bc37facSAndre Przywara }; 1266bc37facSAndre Przywara 1276bc37facSAndre Przywara soc { 1286bc37facSAndre Przywara compatible = "simple-bus"; 1296bc37facSAndre Przywara #address-cells = <1>; 1306bc37facSAndre Przywara #size-cells = <1>; 1316bc37facSAndre Przywara ranges; 1326bc37facSAndre Przywara 133f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 134f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 135f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 136f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 137f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 138f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 139f3dff347SAndre Przywara reset-names = "ahb"; 140f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 14122be992fSMaxime Ripard max-frequency = <150000000>; 142f3dff347SAndre Przywara status = "disabled"; 143f3dff347SAndre Przywara #address-cells = <1>; 144f3dff347SAndre Przywara #size-cells = <0>; 145f3dff347SAndre Przywara }; 146f3dff347SAndre Przywara 147f3dff347SAndre Przywara mmc1: mmc@1c10000 { 148f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 149f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 150f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 151f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 152f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 153f3dff347SAndre Przywara reset-names = "ahb"; 154f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 15522be992fSMaxime Ripard max-frequency = <150000000>; 156f3dff347SAndre Przywara status = "disabled"; 157f3dff347SAndre Przywara #address-cells = <1>; 158f3dff347SAndre Przywara #size-cells = <0>; 159f3dff347SAndre Przywara }; 160f3dff347SAndre Przywara 161f3dff347SAndre Przywara mmc2: mmc@1c11000 { 162f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 163f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 164f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 165f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 166f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 167f3dff347SAndre Przywara reset-names = "ahb"; 168f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 16922be992fSMaxime Ripard max-frequency = <200000000>; 170f3dff347SAndre Przywara status = "disabled"; 171f3dff347SAndre Przywara #address-cells = <1>; 172f3dff347SAndre Przywara #size-cells = <0>; 173f3dff347SAndre Przywara }; 174f3dff347SAndre Przywara 175972a3ecdSIcenowy Zheng usb_otg: usb@01c19000 { 176972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 177972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 178972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 179972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 180972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 181972a3ecdSIcenowy Zheng interrupt-names = "mc"; 182972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 183972a3ecdSIcenowy Zheng phy-names = "usb"; 184972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 185972a3ecdSIcenowy Zheng status = "disabled"; 186972a3ecdSIcenowy Zheng }; 187972a3ecdSIcenowy Zheng 188a004ee35SIcenowy Zheng usbphy: phy@01c19400 { 189a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 190a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 1910d984797SIcenowy Zheng <0x01c1a800 0x4>, 192a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 193a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 1940d984797SIcenowy Zheng "pmu0", 195a004ee35SIcenowy Zheng "pmu1"; 196a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 197a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 198a004ee35SIcenowy Zheng clock-names = "usb0_phy", 199a004ee35SIcenowy Zheng "usb1_phy"; 200a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 201a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 202a004ee35SIcenowy Zheng reset-names = "usb0_reset", 203a004ee35SIcenowy Zheng "usb1_reset"; 204a004ee35SIcenowy Zheng status = "disabled"; 205a004ee35SIcenowy Zheng #phy-cells = <1>; 206a004ee35SIcenowy Zheng }; 207a004ee35SIcenowy Zheng 208dc03a047SIcenowy Zheng ehci0: usb@01c1a000 { 209dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 210dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 211dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 212dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 213dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 214dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 215dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 216dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 217dc03a047SIcenowy Zheng status = "disabled"; 218dc03a047SIcenowy Zheng }; 219dc03a047SIcenowy Zheng 220dc03a047SIcenowy Zheng ohci0: usb@01c1a400 { 221dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 222dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 223dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 224dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 225dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 226dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 227dc03a047SIcenowy Zheng status = "disabled"; 228dc03a047SIcenowy Zheng }; 229dc03a047SIcenowy Zheng 230a004ee35SIcenowy Zheng ehci1: usb@01c1b000 { 231a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 232a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 233a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 234a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 235a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 236a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 237a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 238a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 239a004ee35SIcenowy Zheng phys = <&usbphy 1>; 240a004ee35SIcenowy Zheng phy-names = "usb"; 241a004ee35SIcenowy Zheng status = "disabled"; 242a004ee35SIcenowy Zheng }; 243a004ee35SIcenowy Zheng 244a004ee35SIcenowy Zheng ohci1: usb@01c1b400 { 245a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 246a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 247a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 248a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 249a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 250a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 251a004ee35SIcenowy Zheng phys = <&usbphy 1>; 252a004ee35SIcenowy Zheng phy-names = "usb"; 253a004ee35SIcenowy Zheng status = "disabled"; 254a004ee35SIcenowy Zheng }; 255a004ee35SIcenowy Zheng 2566bc37facSAndre Przywara ccu: clock@01c20000 { 2576bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 2586bc37facSAndre Przywara reg = <0x01c20000 0x400>; 2596bc37facSAndre Przywara clocks = <&osc24M>, <&osc32k>; 2606bc37facSAndre Przywara clock-names = "hosc", "losc"; 2616bc37facSAndre Przywara #clock-cells = <1>; 2626bc37facSAndre Przywara #reset-cells = <1>; 2636bc37facSAndre Przywara }; 2646bc37facSAndre Przywara 2656bc37facSAndre Przywara pio: pinctrl@1c20800 { 2666bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 2676bc37facSAndre Przywara reg = <0x01c20800 0x400>; 2686bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2696bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2706bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 271f98121f3SArnd Bergmann clocks = <&ccu 58>; 2726bc37facSAndre Przywara gpio-controller; 2736bc37facSAndre Przywara #gpio-cells = <3>; 2746bc37facSAndre Przywara interrupt-controller; 2756bc37facSAndre Przywara #interrupt-cells = <3>; 2766bc37facSAndre Przywara 2776bc37facSAndre Przywara i2c1_pins: i2c1_pins { 2786bc37facSAndre Przywara pins = "PH2", "PH3"; 2796bc37facSAndre Przywara function = "i2c1"; 2806bc37facSAndre Przywara }; 2816bc37facSAndre Przywara 282a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 283a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 284a3e8f492SMaxime Ripard "PF4", "PF5"; 285a3e8f492SMaxime Ripard function = "mmc0"; 286a3e8f492SMaxime Ripard drive-strength = <30>; 287a3e8f492SMaxime Ripard bias-pull-up; 288a3e8f492SMaxime Ripard }; 289a3e8f492SMaxime Ripard 290a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 291a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 292a3e8f492SMaxime Ripard "PG4", "PG5"; 293a3e8f492SMaxime Ripard function = "mmc1"; 294a3e8f492SMaxime Ripard drive-strength = <30>; 295a3e8f492SMaxime Ripard bias-pull-up; 296a3e8f492SMaxime Ripard }; 297a3e8f492SMaxime Ripard 298a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 299a3e8f492SMaxime Ripard pins = "PC1", "PC5", "PC6", "PC8", "PC9", 300a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 301a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 302a3e8f492SMaxime Ripard function = "mmc2"; 303a3e8f492SMaxime Ripard drive-strength = <30>; 304a3e8f492SMaxime Ripard bias-pull-up; 305a3e8f492SMaxime Ripard }; 306a3e8f492SMaxime Ripard 3076bc37facSAndre Przywara uart0_pins_a: uart0@0 { 3086bc37facSAndre Przywara pins = "PB8", "PB9"; 3096bc37facSAndre Przywara function = "uart0"; 3106bc37facSAndre Przywara }; 311e7ba733dSAndre Przywara 312e7ba733dSAndre Przywara uart1_pins: uart1_pins { 313e7ba733dSAndre Przywara pins = "PG6", "PG7"; 314e7ba733dSAndre Przywara function = "uart1"; 315e7ba733dSAndre Przywara }; 316e7ba733dSAndre Przywara 317e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 318e7ba733dSAndre Przywara pins = "PG8", "PG9"; 319e7ba733dSAndre Przywara function = "uart1"; 320e7ba733dSAndre Przywara }; 32179825719SAndreas Färber 32279825719SAndreas Färber uart2_pins: uart2-pins { 32379825719SAndreas Färber pins = "PB0", "PB1"; 32479825719SAndreas Färber function = "uart2"; 32579825719SAndreas Färber }; 3262273aa16SAndreas Färber 3272273aa16SAndreas Färber uart3_pins: uart3-pins { 3282273aa16SAndreas Färber pins = "PD0", "PD1"; 3292273aa16SAndreas Färber function = "uart3"; 3302273aa16SAndreas Färber }; 3312273aa16SAndreas Färber 3322273aa16SAndreas Färber uart4_pins: uart4-pins { 3332273aa16SAndreas Färber pins = "PD2", "PD3"; 3342273aa16SAndreas Färber function = "uart4"; 3352273aa16SAndreas Färber }; 3362273aa16SAndreas Färber 3372273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 3382273aa16SAndreas Färber pins = "PD4", "PD5"; 3392273aa16SAndreas Färber function = "uart4"; 3402273aa16SAndreas Färber }; 3416bc37facSAndre Przywara }; 3426bc37facSAndre Przywara 3436bc37facSAndre Przywara uart0: serial@1c28000 { 3446bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3456bc37facSAndre Przywara reg = <0x01c28000 0x400>; 3466bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3476bc37facSAndre Przywara reg-shift = <2>; 3486bc37facSAndre Przywara reg-io-width = <4>; 349494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 350494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 3516bc37facSAndre Przywara status = "disabled"; 3526bc37facSAndre Przywara }; 3536bc37facSAndre Przywara 3546bc37facSAndre Przywara uart1: serial@1c28400 { 3556bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3566bc37facSAndre Przywara reg = <0x01c28400 0x400>; 3576bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 3586bc37facSAndre Przywara reg-shift = <2>; 3596bc37facSAndre Przywara reg-io-width = <4>; 360494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 361494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 3626bc37facSAndre Przywara status = "disabled"; 3636bc37facSAndre Przywara }; 3646bc37facSAndre Przywara 3656bc37facSAndre Przywara uart2: serial@1c28800 { 3666bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3676bc37facSAndre Przywara reg = <0x01c28800 0x400>; 3686bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 3696bc37facSAndre Przywara reg-shift = <2>; 3706bc37facSAndre Przywara reg-io-width = <4>; 371494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 372494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 3736bc37facSAndre Przywara status = "disabled"; 3746bc37facSAndre Przywara }; 3756bc37facSAndre Przywara 3766bc37facSAndre Przywara uart3: serial@1c28c00 { 3776bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3786bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 3796bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 3806bc37facSAndre Przywara reg-shift = <2>; 3816bc37facSAndre Przywara reg-io-width = <4>; 382494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 383494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 3846bc37facSAndre Przywara status = "disabled"; 3856bc37facSAndre Przywara }; 3866bc37facSAndre Przywara 3876bc37facSAndre Przywara uart4: serial@1c29000 { 3886bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3896bc37facSAndre Przywara reg = <0x01c29000 0x400>; 3906bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 3916bc37facSAndre Przywara reg-shift = <2>; 3926bc37facSAndre Przywara reg-io-width = <4>; 393494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 394494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 3956bc37facSAndre Przywara status = "disabled"; 3966bc37facSAndre Przywara }; 3976bc37facSAndre Przywara 3986bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 3996bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 4006bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 4016bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 402494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 403494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 4046bc37facSAndre Przywara status = "disabled"; 4056bc37facSAndre Przywara #address-cells = <1>; 4066bc37facSAndre Przywara #size-cells = <0>; 4076bc37facSAndre Przywara }; 4086bc37facSAndre Przywara 4096bc37facSAndre Przywara i2c1: i2c@1c2b000 { 4106bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 4116bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 4126bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 413494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 414494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 4156bc37facSAndre Przywara status = "disabled"; 4166bc37facSAndre Przywara #address-cells = <1>; 4176bc37facSAndre Przywara #size-cells = <0>; 4186bc37facSAndre Przywara }; 4196bc37facSAndre Przywara 4206bc37facSAndre Przywara i2c2: i2c@1c2b400 { 4216bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 4226bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 4236bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 424494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 425494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 4266bc37facSAndre Przywara status = "disabled"; 4276bc37facSAndre Przywara #address-cells = <1>; 4286bc37facSAndre Przywara #size-cells = <0>; 4296bc37facSAndre Przywara }; 4306bc37facSAndre Przywara 4316bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 4326bc37facSAndre Przywara compatible = "arm,gic-400"; 4336bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 4346bc37facSAndre Przywara <0x01c82000 0x2000>, 4356bc37facSAndre Przywara <0x01c84000 0x2000>, 4366bc37facSAndre Przywara <0x01c86000 0x2000>; 4376bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 4386bc37facSAndre Przywara interrupt-controller; 4396bc37facSAndre Przywara #interrupt-cells = <3>; 4406bc37facSAndre Przywara }; 4416bc37facSAndre Przywara 4426bc37facSAndre Przywara rtc: rtc@1f00000 { 4436bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-rtc"; 4446bc37facSAndre Przywara reg = <0x01f00000 0x54>; 4456bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 4466bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 4476bc37facSAndre Przywara }; 448791a9e00SIcenowy Zheng 449791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 450791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 451791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 452791a9e00SIcenowy Zheng clocks = <&osc24M>, <&osc32k>, <&iosc>; 453791a9e00SIcenowy Zheng clock-names = "hosc", "losc", "iosc"; 454791a9e00SIcenowy Zheng #clock-cells = <1>; 455791a9e00SIcenowy Zheng #reset-cells = <1>; 456791a9e00SIcenowy Zheng }; 457ec427905SIcenowy Zheng 458ec427905SIcenowy Zheng r_pio: pinctrl@01f02c00 { 459ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 460ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 461ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 462494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 463ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 464ec427905SIcenowy Zheng gpio-controller; 465ec427905SIcenowy Zheng #gpio-cells = <3>; 466ec427905SIcenowy Zheng interrupt-controller; 467ec427905SIcenowy Zheng #interrupt-cells = <3>; 4683b38fdedSIcenowy Zheng 4693b38fdedSIcenowy Zheng r_rsb_pins: rsb@0 { 4703b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 4713b38fdedSIcenowy Zheng function = "s_rsb"; 4723b38fdedSIcenowy Zheng }; 4733b38fdedSIcenowy Zheng }; 4743b38fdedSIcenowy Zheng 4753b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 4763b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 4773b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 4783b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 4793b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 4803b38fdedSIcenowy Zheng clock-frequency = <3000000>; 4813b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 4823b38fdedSIcenowy Zheng pinctrl-names = "default"; 4833b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 4843b38fdedSIcenowy Zheng status = "disabled"; 4853b38fdedSIcenowy Zheng #address-cells = <1>; 4863b38fdedSIcenowy Zheng #size-cells = <0>; 487ec427905SIcenowy Zheng }; 4886bc37facSAndre Przywara }; 4896bc37facSAndre Przywara}; 490