16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 462c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 47494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 486bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 49a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 502c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 51871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 526bc37facSAndre Przywara 536bc37facSAndre Przywara/ { 546bc37facSAndre Przywara interrupt-parent = <&gic>; 556bc37facSAndre Przywara #address-cells = <1>; 566bc37facSAndre Przywara #size-cells = <1>; 576bc37facSAndre Przywara 58c1cff65fSHarald Geyer chosen { 59c1cff65fSHarald Geyer #address-cells = <1>; 60c1cff65fSHarald Geyer #size-cells = <1>; 61c1cff65fSHarald Geyer ranges; 62c1cff65fSHarald Geyer 63c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 64c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 65c1cff65fSHarald Geyer "simple-framebuffer"; 66c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 67c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 682c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 69c1cff65fSHarald Geyer status = "disabled"; 70c1cff65fSHarald Geyer }; 71c1cff65fSHarald Geyer }; 72c1cff65fSHarald Geyer 736bc37facSAndre Przywara cpus { 746bc37facSAndre Przywara #address-cells = <1>; 756bc37facSAndre Przywara #size-cells = <0>; 766bc37facSAndre Przywara 776bc37facSAndre Przywara cpu0: cpu@0 { 786bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 796bc37facSAndre Przywara device_type = "cpu"; 806bc37facSAndre Przywara reg = <0>; 816bc37facSAndre Przywara enable-method = "psci"; 826bc37facSAndre Przywara }; 836bc37facSAndre Przywara 846bc37facSAndre Przywara cpu1: cpu@1 { 856bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 866bc37facSAndre Przywara device_type = "cpu"; 876bc37facSAndre Przywara reg = <1>; 886bc37facSAndre Przywara enable-method = "psci"; 896bc37facSAndre Przywara }; 906bc37facSAndre Przywara 916bc37facSAndre Przywara cpu2: cpu@2 { 926bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 936bc37facSAndre Przywara device_type = "cpu"; 946bc37facSAndre Przywara reg = <2>; 956bc37facSAndre Przywara enable-method = "psci"; 966bc37facSAndre Przywara }; 976bc37facSAndre Przywara 986bc37facSAndre Przywara cpu3: cpu@3 { 996bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 1006bc37facSAndre Przywara device_type = "cpu"; 1016bc37facSAndre Przywara reg = <3>; 1026bc37facSAndre Przywara enable-method = "psci"; 1036bc37facSAndre Przywara }; 1046bc37facSAndre Przywara }; 1056bc37facSAndre Przywara 1066bc37facSAndre Przywara osc24M: osc24M_clk { 1076bc37facSAndre Przywara #clock-cells = <0>; 1086bc37facSAndre Przywara compatible = "fixed-clock"; 1096bc37facSAndre Przywara clock-frequency = <24000000>; 1106bc37facSAndre Przywara clock-output-names = "osc24M"; 1116bc37facSAndre Przywara }; 1126bc37facSAndre Przywara 1136bc37facSAndre Przywara osc32k: osc32k_clk { 1146bc37facSAndre Przywara #clock-cells = <0>; 1156bc37facSAndre Przywara compatible = "fixed-clock"; 1166bc37facSAndre Przywara clock-frequency = <32768>; 1176bc37facSAndre Przywara clock-output-names = "osc32k"; 1186bc37facSAndre Przywara }; 1196bc37facSAndre Przywara 120791a9e00SIcenowy Zheng iosc: internal-osc-clk { 121791a9e00SIcenowy Zheng #clock-cells = <0>; 122791a9e00SIcenowy Zheng compatible = "fixed-clock"; 123791a9e00SIcenowy Zheng clock-frequency = <16000000>; 124791a9e00SIcenowy Zheng clock-accuracy = <300000000>; 125791a9e00SIcenowy Zheng clock-output-names = "iosc"; 126791a9e00SIcenowy Zheng }; 127791a9e00SIcenowy Zheng 1286bc37facSAndre Przywara psci { 1296bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1306bc37facSAndre Przywara method = "smc"; 1316bc37facSAndre Przywara }; 1326bc37facSAndre Przywara 13378e07137SMarcus Cooper sound_spdif { 13478e07137SMarcus Cooper compatible = "simple-audio-card"; 13578e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 13678e07137SMarcus Cooper 13778e07137SMarcus Cooper simple-audio-card,cpu { 13878e07137SMarcus Cooper sound-dai = <&spdif>; 13978e07137SMarcus Cooper }; 14078e07137SMarcus Cooper 14178e07137SMarcus Cooper simple-audio-card,codec { 14278e07137SMarcus Cooper sound-dai = <&spdif_out>; 14378e07137SMarcus Cooper }; 14478e07137SMarcus Cooper }; 14578e07137SMarcus Cooper 14678e07137SMarcus Cooper spdif_out: spdif-out { 14778e07137SMarcus Cooper #sound-dai-cells = <0>; 14878e07137SMarcus Cooper compatible = "linux,spdif-dit"; 14978e07137SMarcus Cooper }; 15078e07137SMarcus Cooper 1516bc37facSAndre Przywara timer { 1526bc37facSAndre Przywara compatible = "arm,armv8-timer"; 1536bc37facSAndre Przywara interrupts = <GIC_PPI 13 1546bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1556bc37facSAndre Przywara <GIC_PPI 14 1566bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1576bc37facSAndre Przywara <GIC_PPI 11 1586bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1596bc37facSAndre Przywara <GIC_PPI 10 1606bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1616bc37facSAndre Przywara }; 1626bc37facSAndre Przywara 1636bc37facSAndre Przywara soc { 1646bc37facSAndre Przywara compatible = "simple-bus"; 1656bc37facSAndre Przywara #address-cells = <1>; 1666bc37facSAndre Przywara #size-cells = <1>; 1676bc37facSAndre Przywara ranges; 1686bc37facSAndre Przywara 1692c796fc8SIcenowy Zheng de2@1000000 { 1702c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 1712c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 1722c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 1732c796fc8SIcenowy Zheng #address-cells = <1>; 1742c796fc8SIcenowy Zheng #size-cells = <1>; 1752c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 1762c796fc8SIcenowy Zheng 1772c796fc8SIcenowy Zheng display_clocks: clock@0 { 1782c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 1792c796fc8SIcenowy Zheng reg = <0x0 0x100000>; 1802c796fc8SIcenowy Zheng clocks = <&ccu CLK_DE>, 1812c796fc8SIcenowy Zheng <&ccu CLK_BUS_DE>; 1822c796fc8SIcenowy Zheng clock-names = "mod", 1832c796fc8SIcenowy Zheng "bus"; 1842c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 1852c796fc8SIcenowy Zheng #clock-cells = <1>; 1862c796fc8SIcenowy Zheng #reset-cells = <1>; 1872c796fc8SIcenowy Zheng }; 1882c796fc8SIcenowy Zheng }; 1892c796fc8SIcenowy Zheng 19079b95360SCorentin Labbe syscon: syscon@1c00000 { 1911f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 19279b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 1931f1f5183SIcenowy Zheng #address-cells = <1>; 1941f1f5183SIcenowy Zheng #size-cells = <1>; 1951f1f5183SIcenowy Zheng ranges; 1961f1f5183SIcenowy Zheng 1971f1f5183SIcenowy Zheng sram_c: sram@18000 { 1981f1f5183SIcenowy Zheng compatible = "mmio-sram"; 1991f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 2001f1f5183SIcenowy Zheng #address-cells = <1>; 2011f1f5183SIcenowy Zheng #size-cells = <1>; 2021f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 2031f1f5183SIcenowy Zheng 2041f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 2051f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 2061f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 2071f1f5183SIcenowy Zheng }; 2081f1f5183SIcenowy Zheng }; 20979b95360SCorentin Labbe }; 21079b95360SCorentin Labbe 211c32637e0SStefan Brüns dma: dma-controller@1c02000 { 212c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 213c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 214c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 215c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 216c32637e0SStefan Brüns dma-channels = <8>; 217c32637e0SStefan Brüns dma-requests = <27>; 218c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 219c32637e0SStefan Brüns #dma-cells = <1>; 220c32637e0SStefan Brüns }; 221c32637e0SStefan Brüns 222f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 223f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 224f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 225f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 226f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 227f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 228f3dff347SAndre Przywara reset-names = "ahb"; 229f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 23022be992fSMaxime Ripard max-frequency = <150000000>; 231f3dff347SAndre Przywara status = "disabled"; 232f3dff347SAndre Przywara #address-cells = <1>; 233f3dff347SAndre Przywara #size-cells = <0>; 234f3dff347SAndre Przywara }; 235f3dff347SAndre Przywara 236f3dff347SAndre Przywara mmc1: mmc@1c10000 { 237f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 238f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 239f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 240f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 241f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 242f3dff347SAndre Przywara reset-names = "ahb"; 243f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 24422be992fSMaxime Ripard max-frequency = <150000000>; 245f3dff347SAndre Przywara status = "disabled"; 246f3dff347SAndre Przywara #address-cells = <1>; 247f3dff347SAndre Przywara #size-cells = <0>; 248f3dff347SAndre Przywara }; 249f3dff347SAndre Przywara 250f3dff347SAndre Przywara mmc2: mmc@1c11000 { 251f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 252f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 253f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 254f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 255f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 256f3dff347SAndre Przywara reset-names = "ahb"; 257f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 25822be992fSMaxime Ripard max-frequency = <200000000>; 259f3dff347SAndre Przywara status = "disabled"; 260f3dff347SAndre Przywara #address-cells = <1>; 261f3dff347SAndre Przywara #size-cells = <0>; 262f3dff347SAndre Przywara }; 263f3dff347SAndre Przywara 264d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 265972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 266972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 267972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 268972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 269972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 270972a3ecdSIcenowy Zheng interrupt-names = "mc"; 271972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 272972a3ecdSIcenowy Zheng phy-names = "usb"; 273972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 274972a3ecdSIcenowy Zheng status = "disabled"; 275972a3ecdSIcenowy Zheng }; 276972a3ecdSIcenowy Zheng 277d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 278a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 279a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 2800d984797SIcenowy Zheng <0x01c1a800 0x4>, 281a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 282a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 2830d984797SIcenowy Zheng "pmu0", 284a004ee35SIcenowy Zheng "pmu1"; 285a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 286a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 287a004ee35SIcenowy Zheng clock-names = "usb0_phy", 288a004ee35SIcenowy Zheng "usb1_phy"; 289a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 290a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 291a004ee35SIcenowy Zheng reset-names = "usb0_reset", 292a004ee35SIcenowy Zheng "usb1_reset"; 293a004ee35SIcenowy Zheng status = "disabled"; 294a004ee35SIcenowy Zheng #phy-cells = <1>; 295a004ee35SIcenowy Zheng }; 296a004ee35SIcenowy Zheng 297d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 298dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 299dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 300dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 301dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 302dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 303dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 304dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 305dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 306dc03a047SIcenowy Zheng status = "disabled"; 307dc03a047SIcenowy Zheng }; 308dc03a047SIcenowy Zheng 309d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 310dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 311dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 312dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 313dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 314dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 315dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 316dc03a047SIcenowy Zheng status = "disabled"; 317dc03a047SIcenowy Zheng }; 318dc03a047SIcenowy Zheng 319d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 320a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 321a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 322a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 323a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 324a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 325a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 326a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 327a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 328a004ee35SIcenowy Zheng phys = <&usbphy 1>; 329a004ee35SIcenowy Zheng phy-names = "usb"; 330a004ee35SIcenowy Zheng status = "disabled"; 331a004ee35SIcenowy Zheng }; 332a004ee35SIcenowy Zheng 333d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 334a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 335a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 336a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 337a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 338a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 339a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 340a004ee35SIcenowy Zheng phys = <&usbphy 1>; 341a004ee35SIcenowy Zheng phy-names = "usb"; 342a004ee35SIcenowy Zheng status = "disabled"; 343a004ee35SIcenowy Zheng }; 344a004ee35SIcenowy Zheng 345d6c9da12SCorentin LABBE ccu: clock@1c20000 { 3466bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 3476bc37facSAndre Przywara reg = <0x01c20000 0x400>; 3486bc37facSAndre Przywara clocks = <&osc24M>, <&osc32k>; 3496bc37facSAndre Przywara clock-names = "hosc", "losc"; 3506bc37facSAndre Przywara #clock-cells = <1>; 3516bc37facSAndre Przywara #reset-cells = <1>; 3526bc37facSAndre Przywara }; 3536bc37facSAndre Przywara 3546bc37facSAndre Przywara pio: pinctrl@1c20800 { 3556bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 3566bc37facSAndre Przywara reg = <0x01c20800 0x400>; 3576bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 3586bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 3596bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 360f98121f3SArnd Bergmann clocks = <&ccu 58>; 3616bc37facSAndre Przywara gpio-controller; 3626bc37facSAndre Przywara #gpio-cells = <3>; 3636bc37facSAndre Przywara interrupt-controller; 3646bc37facSAndre Przywara #interrupt-cells = <3>; 3656bc37facSAndre Przywara 36611239fe6SHarald Geyer i2c0_pins: i2c0_pins { 36711239fe6SHarald Geyer pins = "PH0", "PH1"; 36811239fe6SHarald Geyer function = "i2c0"; 36911239fe6SHarald Geyer }; 37011239fe6SHarald Geyer 3716bc37facSAndre Przywara i2c1_pins: i2c1_pins { 3726bc37facSAndre Przywara pins = "PH2", "PH3"; 3736bc37facSAndre Przywara function = "i2c1"; 3746bc37facSAndre Przywara }; 3756bc37facSAndre Przywara 376a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 377a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 378a3e8f492SMaxime Ripard "PF4", "PF5"; 379a3e8f492SMaxime Ripard function = "mmc0"; 380a3e8f492SMaxime Ripard drive-strength = <30>; 381a3e8f492SMaxime Ripard bias-pull-up; 382a3e8f492SMaxime Ripard }; 383a3e8f492SMaxime Ripard 384a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 385a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 386a3e8f492SMaxime Ripard "PG4", "PG5"; 387a3e8f492SMaxime Ripard function = "mmc1"; 388a3e8f492SMaxime Ripard drive-strength = <30>; 389a3e8f492SMaxime Ripard bias-pull-up; 390a3e8f492SMaxime Ripard }; 391a3e8f492SMaxime Ripard 392a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 393a3e8f492SMaxime Ripard pins = "PC1", "PC5", "PC6", "PC8", "PC9", 394a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 395a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 396a3e8f492SMaxime Ripard function = "mmc2"; 397a3e8f492SMaxime Ripard drive-strength = <30>; 398a3e8f492SMaxime Ripard bias-pull-up; 399a3e8f492SMaxime Ripard }; 400a3e8f492SMaxime Ripard 401b5df280bSAndre Przywara pwm_pin: pwm_pin { 402b5df280bSAndre Przywara pins = "PD22"; 403b5df280bSAndre Przywara function = "pwm"; 404b5df280bSAndre Przywara }; 405b5df280bSAndre Przywara 406e53f67e9SCorentin Labbe rmii_pins: rmii_pins { 407e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 408e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 409e53f67e9SCorentin Labbe function = "emac"; 410e53f67e9SCorentin Labbe drive-strength = <40>; 411e53f67e9SCorentin Labbe }; 412e53f67e9SCorentin Labbe 413e53f67e9SCorentin Labbe rgmii_pins: rgmii_pins { 414e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 415e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 416e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 417e53f67e9SCorentin Labbe function = "emac"; 418e53f67e9SCorentin Labbe drive-strength = <40>; 419e53f67e9SCorentin Labbe }; 420e53f67e9SCorentin Labbe 421b399d2acSMarcus Cooper spdif_tx_pin: spdif { 422b399d2acSMarcus Cooper pins = "PH8"; 423b399d2acSMarcus Cooper function = "spdif"; 424b399d2acSMarcus Cooper }; 425b399d2acSMarcus Cooper 426b518bb15SStefan Brüns spi0_pins: spi0 { 427b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 428b518bb15SStefan Brüns function = "spi0"; 429b518bb15SStefan Brüns }; 430b518bb15SStefan Brüns 431b518bb15SStefan Brüns spi1_pins: spi1 { 432b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 433b518bb15SStefan Brüns function = "spi1"; 434b518bb15SStefan Brüns }; 435b518bb15SStefan Brüns 43692d378fbSCorentin LABBE uart0_pins_a: uart0 { 4376bc37facSAndre Przywara pins = "PB8", "PB9"; 4386bc37facSAndre Przywara function = "uart0"; 4396bc37facSAndre Przywara }; 440e7ba733dSAndre Przywara 441e7ba733dSAndre Przywara uart1_pins: uart1_pins { 442e7ba733dSAndre Przywara pins = "PG6", "PG7"; 443e7ba733dSAndre Przywara function = "uart1"; 444e7ba733dSAndre Przywara }; 445e7ba733dSAndre Przywara 446e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 447e7ba733dSAndre Przywara pins = "PG8", "PG9"; 448e7ba733dSAndre Przywara function = "uart1"; 449e7ba733dSAndre Przywara }; 45079825719SAndreas Färber 45179825719SAndreas Färber uart2_pins: uart2-pins { 45279825719SAndreas Färber pins = "PB0", "PB1"; 45379825719SAndreas Färber function = "uart2"; 45479825719SAndreas Färber }; 4552273aa16SAndreas Färber 4562273aa16SAndreas Färber uart3_pins: uart3-pins { 4572273aa16SAndreas Färber pins = "PD0", "PD1"; 4582273aa16SAndreas Färber function = "uart3"; 4592273aa16SAndreas Färber }; 4602273aa16SAndreas Färber 4612273aa16SAndreas Färber uart4_pins: uart4-pins { 4622273aa16SAndreas Färber pins = "PD2", "PD3"; 4632273aa16SAndreas Färber function = "uart4"; 4642273aa16SAndreas Färber }; 4652273aa16SAndreas Färber 4662273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 4672273aa16SAndreas Färber pins = "PD4", "PD5"; 4682273aa16SAndreas Färber function = "uart4"; 4692273aa16SAndreas Färber }; 4706bc37facSAndre Przywara }; 4716bc37facSAndre Przywara 472b399d2acSMarcus Cooper spdif: spdif@1c21000 { 473b399d2acSMarcus Cooper #sound-dai-cells = <0>; 474b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 475b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 476b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 477b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 478b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 479b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 480b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 481b399d2acSMarcus Cooper dmas = <&dma 2>; 482b399d2acSMarcus Cooper dma-names = "tx"; 483b399d2acSMarcus Cooper pinctrl-names = "default"; 484b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 485b399d2acSMarcus Cooper status = "disabled"; 486b399d2acSMarcus Cooper }; 487b399d2acSMarcus Cooper 4881c92c009SMarcus Cooper i2s0: i2s@1c22000 { 4891c92c009SMarcus Cooper #sound-dai-cells = <0>; 4901c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 4911c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 4921c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 4931c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4941c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 4951c92c009SMarcus Cooper clock-names = "apb", "mod"; 4961c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 4971c92c009SMarcus Cooper dma-names = "rx", "tx"; 4981c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 4991c92c009SMarcus Cooper status = "disabled"; 5001c92c009SMarcus Cooper }; 5011c92c009SMarcus Cooper 5021c92c009SMarcus Cooper i2s1: i2s@1c22400 { 5031c92c009SMarcus Cooper #sound-dai-cells = <0>; 5041c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 5051c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 5061c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 5071c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5081c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 5091c92c009SMarcus Cooper clock-names = "apb", "mod"; 5101c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 5111c92c009SMarcus Cooper dma-names = "rx", "tx"; 5121c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 5131c92c009SMarcus Cooper status = "disabled"; 5141c92c009SMarcus Cooper }; 5151c92c009SMarcus Cooper 5166bc37facSAndre Przywara uart0: serial@1c28000 { 5176bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5186bc37facSAndre Przywara reg = <0x01c28000 0x400>; 5196bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5206bc37facSAndre Przywara reg-shift = <2>; 5216bc37facSAndre Przywara reg-io-width = <4>; 522494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 523494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 5246bc37facSAndre Przywara status = "disabled"; 5256bc37facSAndre Przywara }; 5266bc37facSAndre Przywara 5276bc37facSAndre Przywara uart1: serial@1c28400 { 5286bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5296bc37facSAndre Przywara reg = <0x01c28400 0x400>; 5306bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 5316bc37facSAndre Przywara reg-shift = <2>; 5326bc37facSAndre Przywara reg-io-width = <4>; 533494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 534494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 5356bc37facSAndre Przywara status = "disabled"; 5366bc37facSAndre Przywara }; 5376bc37facSAndre Przywara 5386bc37facSAndre Przywara uart2: serial@1c28800 { 5396bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5406bc37facSAndre Przywara reg = <0x01c28800 0x400>; 5416bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 5426bc37facSAndre Przywara reg-shift = <2>; 5436bc37facSAndre Przywara reg-io-width = <4>; 544494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 545494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 5466bc37facSAndre Przywara status = "disabled"; 5476bc37facSAndre Przywara }; 5486bc37facSAndre Przywara 5496bc37facSAndre Przywara uart3: serial@1c28c00 { 5506bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5516bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 5526bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 5536bc37facSAndre Przywara reg-shift = <2>; 5546bc37facSAndre Przywara reg-io-width = <4>; 555494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 556494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 5576bc37facSAndre Przywara status = "disabled"; 5586bc37facSAndre Przywara }; 5596bc37facSAndre Przywara 5606bc37facSAndre Przywara uart4: serial@1c29000 { 5616bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5626bc37facSAndre Przywara reg = <0x01c29000 0x400>; 5636bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 5646bc37facSAndre Przywara reg-shift = <2>; 5656bc37facSAndre Przywara reg-io-width = <4>; 566494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 567494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 5686bc37facSAndre Przywara status = "disabled"; 5696bc37facSAndre Przywara }; 5706bc37facSAndre Przywara 5716bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 5726bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5736bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 5746bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 575494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 576494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 5776bc37facSAndre Przywara status = "disabled"; 5786bc37facSAndre Przywara #address-cells = <1>; 5796bc37facSAndre Przywara #size-cells = <0>; 5806bc37facSAndre Przywara }; 5816bc37facSAndre Przywara 5826bc37facSAndre Przywara i2c1: i2c@1c2b000 { 5836bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5846bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 5856bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 586494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 587494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 5886bc37facSAndre Przywara status = "disabled"; 5896bc37facSAndre Przywara #address-cells = <1>; 5906bc37facSAndre Przywara #size-cells = <0>; 5916bc37facSAndre Przywara }; 5926bc37facSAndre Przywara 5936bc37facSAndre Przywara i2c2: i2c@1c2b400 { 5946bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5956bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 5966bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 597494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 598494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 5996bc37facSAndre Przywara status = "disabled"; 6006bc37facSAndre Przywara #address-cells = <1>; 6016bc37facSAndre Przywara #size-cells = <0>; 6026bc37facSAndre Przywara }; 6036bc37facSAndre Przywara 604b518bb15SStefan Brüns 605d6c9da12SCorentin LABBE spi0: spi@1c68000 { 606b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 607b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 608b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 609b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 610b518bb15SStefan Brüns clock-names = "ahb", "mod"; 61106c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 61206c1258aSStefan Brüns dma-names = "rx", "tx"; 613b518bb15SStefan Brüns pinctrl-names = "default"; 614b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 615b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 616b518bb15SStefan Brüns status = "disabled"; 617b518bb15SStefan Brüns num-cs = <1>; 618b518bb15SStefan Brüns #address-cells = <1>; 619b518bb15SStefan Brüns #size-cells = <0>; 620b518bb15SStefan Brüns }; 621b518bb15SStefan Brüns 622d6c9da12SCorentin LABBE spi1: spi@1c69000 { 623b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 624b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 625b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 626b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 627b518bb15SStefan Brüns clock-names = "ahb", "mod"; 62806c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 62906c1258aSStefan Brüns dma-names = "rx", "tx"; 630b518bb15SStefan Brüns pinctrl-names = "default"; 631b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 632b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 633b518bb15SStefan Brüns status = "disabled"; 634b518bb15SStefan Brüns num-cs = <1>; 635b518bb15SStefan Brüns #address-cells = <1>; 636b518bb15SStefan Brüns #size-cells = <0>; 637b518bb15SStefan Brüns }; 638b518bb15SStefan Brüns 63994f44288SCorentin Labbe emac: ethernet@1c30000 { 64094f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 64194f44288SCorentin Labbe syscon = <&syscon>; 64294f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 64394f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 64494f44288SCorentin Labbe interrupt-names = "macirq"; 64594f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 64694f44288SCorentin Labbe reset-names = "stmmaceth"; 64794f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 64894f44288SCorentin Labbe clock-names = "stmmaceth"; 64994f44288SCorentin Labbe status = "disabled"; 65094f44288SCorentin Labbe #address-cells = <1>; 65194f44288SCorentin Labbe #size-cells = <0>; 65294f44288SCorentin Labbe 65394f44288SCorentin Labbe mdio: mdio { 65416416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 65594f44288SCorentin Labbe #address-cells = <1>; 65694f44288SCorentin Labbe #size-cells = <0>; 65794f44288SCorentin Labbe }; 65894f44288SCorentin Labbe }; 65994f44288SCorentin Labbe 6606bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 6616bc37facSAndre Przywara compatible = "arm,gic-400"; 6626bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 6636bc37facSAndre Przywara <0x01c82000 0x2000>, 6646bc37facSAndre Przywara <0x01c84000 0x2000>, 6656bc37facSAndre Przywara <0x01c86000 0x2000>; 6666bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 6676bc37facSAndre Przywara interrupt-controller; 6686bc37facSAndre Przywara #interrupt-cells = <3>; 6696bc37facSAndre Przywara }; 6706bc37facSAndre Przywara 671b5df280bSAndre Przywara pwm: pwm@1c21400 { 672b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 673b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 674b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 675b5df280bSAndre Przywara clocks = <&osc24M>; 676b5df280bSAndre Przywara pinctrl-names = "default"; 677b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 678b5df280bSAndre Przywara #pwm-cells = <3>; 679b5df280bSAndre Przywara status = "disabled"; 680b5df280bSAndre Przywara }; 681b5df280bSAndre Przywara 6826bc37facSAndre Przywara rtc: rtc@1f00000 { 6836bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-rtc"; 6846bc37facSAndre Przywara reg = <0x01f00000 0x54>; 6856bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 6866bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 687e1a9a474SJagan Teki clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 688e1a9a474SJagan Teki clocks = <&osc32k>; 689e1a9a474SJagan Teki #clock-cells = <1>; 6906bc37facSAndre Przywara }; 691791a9e00SIcenowy Zheng 692535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 693535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 694535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 695535ca508SIcenowy Zheng interrupt-controller; 696535ca508SIcenowy Zheng #interrupt-cells = <2>; 697535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 698535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 699535ca508SIcenowy Zheng }; 700535ca508SIcenowy Zheng 701791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 702791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 703791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 704f74994a9SChen-Yu Tsai clocks = <&osc24M>, <&osc32k>, <&iosc>, 705f74994a9SChen-Yu Tsai <&ccu 11>; 706f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 707791a9e00SIcenowy Zheng #clock-cells = <1>; 708791a9e00SIcenowy Zheng #reset-cells = <1>; 709791a9e00SIcenowy Zheng }; 710ec427905SIcenowy Zheng 711871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 712871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 713871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 714871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 715871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 716871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 717871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 718871b5352SIcenowy Zheng status = "disabled"; 719871b5352SIcenowy Zheng #address-cells = <1>; 720871b5352SIcenowy Zheng #size-cells = <0>; 721871b5352SIcenowy Zheng }; 722871b5352SIcenowy Zheng 723b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 724b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 725b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 726b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 727b5df280bSAndre Przywara clocks = <&osc24M>; 728b5df280bSAndre Przywara pinctrl-names = "default"; 729b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 730b5df280bSAndre Przywara #pwm-cells = <3>; 731b5df280bSAndre Przywara status = "disabled"; 732b5df280bSAndre Przywara }; 733b5df280bSAndre Przywara 734d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 735ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 736ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 737ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 738494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 739ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 740ec427905SIcenowy Zheng gpio-controller; 741ec427905SIcenowy Zheng #gpio-cells = <3>; 742ec427905SIcenowy Zheng interrupt-controller; 743ec427905SIcenowy Zheng #interrupt-cells = <3>; 7443b38fdedSIcenowy Zheng 745871b5352SIcenowy Zheng r_i2c_pins_a: i2c-a { 746871b5352SIcenowy Zheng pins = "PL8", "PL9"; 747871b5352SIcenowy Zheng function = "s_i2c"; 748871b5352SIcenowy Zheng }; 749871b5352SIcenowy Zheng 750b5df280bSAndre Przywara r_pwm_pin: pwm { 751b5df280bSAndre Przywara pins = "PL10"; 752b5df280bSAndre Przywara function = "s_pwm"; 753b5df280bSAndre Przywara }; 754b5df280bSAndre Przywara 75592d378fbSCorentin LABBE r_rsb_pins: rsb { 7563b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 7573b38fdedSIcenowy Zheng function = "s_rsb"; 7583b38fdedSIcenowy Zheng }; 7593b38fdedSIcenowy Zheng }; 7603b38fdedSIcenowy Zheng 7613b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 7623b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 7633b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 7643b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 7653b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 7663b38fdedSIcenowy Zheng clock-frequency = <3000000>; 7673b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 7683b38fdedSIcenowy Zheng pinctrl-names = "default"; 7693b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 7703b38fdedSIcenowy Zheng status = "disabled"; 7713b38fdedSIcenowy Zheng #address-cells = <1>; 7723b38fdedSIcenowy Zheng #size-cells = <0>; 773ec427905SIcenowy Zheng }; 774d4185043SHarald Geyer 775d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 776d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 777d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 778d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 779d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 780d4185043SHarald Geyer }; 7816bc37facSAndre Przywara }; 7826bc37facSAndre Przywara}; 783