16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 466bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 47a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 486bc37facSAndre Przywara 496bc37facSAndre Przywara/ { 506bc37facSAndre Przywara interrupt-parent = <&gic>; 516bc37facSAndre Przywara #address-cells = <1>; 526bc37facSAndre Przywara #size-cells = <1>; 536bc37facSAndre Przywara 546bc37facSAndre Przywara cpus { 556bc37facSAndre Przywara #address-cells = <1>; 566bc37facSAndre Przywara #size-cells = <0>; 576bc37facSAndre Przywara 586bc37facSAndre Przywara cpu0: cpu@0 { 596bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 606bc37facSAndre Przywara device_type = "cpu"; 616bc37facSAndre Przywara reg = <0>; 626bc37facSAndre Przywara enable-method = "psci"; 636bc37facSAndre Przywara }; 646bc37facSAndre Przywara 656bc37facSAndre Przywara cpu1: cpu@1 { 666bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 676bc37facSAndre Przywara device_type = "cpu"; 686bc37facSAndre Przywara reg = <1>; 696bc37facSAndre Przywara enable-method = "psci"; 706bc37facSAndre Przywara }; 716bc37facSAndre Przywara 726bc37facSAndre Przywara cpu2: cpu@2 { 736bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 746bc37facSAndre Przywara device_type = "cpu"; 756bc37facSAndre Przywara reg = <2>; 766bc37facSAndre Przywara enable-method = "psci"; 776bc37facSAndre Przywara }; 786bc37facSAndre Przywara 796bc37facSAndre Przywara cpu3: cpu@3 { 806bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 816bc37facSAndre Przywara device_type = "cpu"; 826bc37facSAndre Przywara reg = <3>; 836bc37facSAndre Przywara enable-method = "psci"; 846bc37facSAndre Przywara }; 856bc37facSAndre Przywara }; 866bc37facSAndre Przywara 876bc37facSAndre Przywara osc24M: osc24M_clk { 886bc37facSAndre Przywara #clock-cells = <0>; 896bc37facSAndre Przywara compatible = "fixed-clock"; 906bc37facSAndre Przywara clock-frequency = <24000000>; 916bc37facSAndre Przywara clock-output-names = "osc24M"; 926bc37facSAndre Przywara }; 936bc37facSAndre Przywara 946bc37facSAndre Przywara osc32k: osc32k_clk { 956bc37facSAndre Przywara #clock-cells = <0>; 966bc37facSAndre Przywara compatible = "fixed-clock"; 976bc37facSAndre Przywara clock-frequency = <32768>; 986bc37facSAndre Przywara clock-output-names = "osc32k"; 996bc37facSAndre Przywara }; 1006bc37facSAndre Przywara 101791a9e00SIcenowy Zheng iosc: internal-osc-clk { 102791a9e00SIcenowy Zheng #clock-cells = <0>; 103791a9e00SIcenowy Zheng compatible = "fixed-clock"; 104791a9e00SIcenowy Zheng clock-frequency = <16000000>; 105791a9e00SIcenowy Zheng clock-accuracy = <300000000>; 106791a9e00SIcenowy Zheng clock-output-names = "iosc"; 107791a9e00SIcenowy Zheng }; 108791a9e00SIcenowy Zheng 1096bc37facSAndre Przywara psci { 1106bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1116bc37facSAndre Przywara method = "smc"; 1126bc37facSAndre Przywara }; 1136bc37facSAndre Przywara 1146bc37facSAndre Przywara timer { 1156bc37facSAndre Przywara compatible = "arm,armv8-timer"; 1166bc37facSAndre Przywara interrupts = <GIC_PPI 13 1176bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1186bc37facSAndre Przywara <GIC_PPI 14 1196bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1206bc37facSAndre Przywara <GIC_PPI 11 1216bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1226bc37facSAndre Przywara <GIC_PPI 10 1236bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1246bc37facSAndre Przywara }; 1256bc37facSAndre Przywara 1266bc37facSAndre Przywara soc { 1276bc37facSAndre Przywara compatible = "simple-bus"; 1286bc37facSAndre Przywara #address-cells = <1>; 1296bc37facSAndre Przywara #size-cells = <1>; 1306bc37facSAndre Przywara ranges; 1316bc37facSAndre Przywara 132f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 133f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 134f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 135f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 136f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 137f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 138f3dff347SAndre Przywara reset-names = "ahb"; 139f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 14022be992fSMaxime Ripard max-frequency = <150000000>; 141f3dff347SAndre Przywara status = "disabled"; 142f3dff347SAndre Przywara #address-cells = <1>; 143f3dff347SAndre Przywara #size-cells = <0>; 144f3dff347SAndre Przywara }; 145f3dff347SAndre Przywara 146f3dff347SAndre Przywara mmc1: mmc@1c10000 { 147f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 148f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 149f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 150f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 151f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 152f3dff347SAndre Przywara reset-names = "ahb"; 153f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 15422be992fSMaxime Ripard max-frequency = <150000000>; 155f3dff347SAndre Przywara status = "disabled"; 156f3dff347SAndre Przywara #address-cells = <1>; 157f3dff347SAndre Przywara #size-cells = <0>; 158f3dff347SAndre Przywara }; 159f3dff347SAndre Przywara 160f3dff347SAndre Przywara mmc2: mmc@1c11000 { 161f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 162f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 163f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 164f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 165f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 166f3dff347SAndre Przywara reset-names = "ahb"; 167f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 16822be992fSMaxime Ripard max-frequency = <200000000>; 169f3dff347SAndre Przywara status = "disabled"; 170f3dff347SAndre Przywara #address-cells = <1>; 171f3dff347SAndre Przywara #size-cells = <0>; 172f3dff347SAndre Przywara }; 173f3dff347SAndre Przywara 174972a3ecdSIcenowy Zheng usb_otg: usb@01c19000 { 175972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 176972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 177972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 178972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 179972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 180972a3ecdSIcenowy Zheng interrupt-names = "mc"; 181972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 182972a3ecdSIcenowy Zheng phy-names = "usb"; 183972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 184972a3ecdSIcenowy Zheng status = "disabled"; 185972a3ecdSIcenowy Zheng }; 186972a3ecdSIcenowy Zheng 187a004ee35SIcenowy Zheng usbphy: phy@01c19400 { 188a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 189a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 1900d984797SIcenowy Zheng <0x01c1a800 0x4>, 191a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 192a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 1930d984797SIcenowy Zheng "pmu0", 194a004ee35SIcenowy Zheng "pmu1"; 195a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 196a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 197a004ee35SIcenowy Zheng clock-names = "usb0_phy", 198a004ee35SIcenowy Zheng "usb1_phy"; 199a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 200a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 201a004ee35SIcenowy Zheng reset-names = "usb0_reset", 202a004ee35SIcenowy Zheng "usb1_reset"; 203a004ee35SIcenowy Zheng status = "disabled"; 204a004ee35SIcenowy Zheng #phy-cells = <1>; 205a004ee35SIcenowy Zheng }; 206a004ee35SIcenowy Zheng 207dc03a047SIcenowy Zheng ehci0: usb@01c1a000 { 208dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 209dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 210dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 211dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 212dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 213dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 214dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 215dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 216dc03a047SIcenowy Zheng status = "disabled"; 217dc03a047SIcenowy Zheng }; 218dc03a047SIcenowy Zheng 219dc03a047SIcenowy Zheng ohci0: usb@01c1a400 { 220dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 221dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 222dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 223dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 224dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 225dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 226dc03a047SIcenowy Zheng status = "disabled"; 227dc03a047SIcenowy Zheng }; 228dc03a047SIcenowy Zheng 229a004ee35SIcenowy Zheng ehci1: usb@01c1b000 { 230a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 231a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 232a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 233a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 234a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 235a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 236a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 237a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 238a004ee35SIcenowy Zheng phys = <&usbphy 1>; 239a004ee35SIcenowy Zheng phy-names = "usb"; 240a004ee35SIcenowy Zheng status = "disabled"; 241a004ee35SIcenowy Zheng }; 242a004ee35SIcenowy Zheng 243a004ee35SIcenowy Zheng ohci1: usb@01c1b400 { 244a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 245a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 246a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 247a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 248a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 249a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 250a004ee35SIcenowy Zheng phys = <&usbphy 1>; 251a004ee35SIcenowy Zheng phy-names = "usb"; 252a004ee35SIcenowy Zheng status = "disabled"; 253a004ee35SIcenowy Zheng }; 254a004ee35SIcenowy Zheng 2556bc37facSAndre Przywara ccu: clock@01c20000 { 2566bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 2576bc37facSAndre Przywara reg = <0x01c20000 0x400>; 2586bc37facSAndre Przywara clocks = <&osc24M>, <&osc32k>; 2596bc37facSAndre Przywara clock-names = "hosc", "losc"; 2606bc37facSAndre Przywara #clock-cells = <1>; 2616bc37facSAndre Przywara #reset-cells = <1>; 2626bc37facSAndre Przywara }; 2636bc37facSAndre Przywara 2646bc37facSAndre Przywara pio: pinctrl@1c20800 { 2656bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 2666bc37facSAndre Przywara reg = <0x01c20800 0x400>; 2676bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2686bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2696bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 270f98121f3SArnd Bergmann clocks = <&ccu 58>; 2716bc37facSAndre Przywara gpio-controller; 2726bc37facSAndre Przywara #gpio-cells = <3>; 2736bc37facSAndre Przywara interrupt-controller; 2746bc37facSAndre Przywara #interrupt-cells = <3>; 2756bc37facSAndre Przywara 2766bc37facSAndre Przywara i2c1_pins: i2c1_pins { 2776bc37facSAndre Przywara pins = "PH2", "PH3"; 2786bc37facSAndre Przywara function = "i2c1"; 2796bc37facSAndre Przywara }; 2806bc37facSAndre Przywara 281a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 282a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 283a3e8f492SMaxime Ripard "PF4", "PF5"; 284a3e8f492SMaxime Ripard function = "mmc0"; 285a3e8f492SMaxime Ripard drive-strength = <30>; 286a3e8f492SMaxime Ripard bias-pull-up; 287a3e8f492SMaxime Ripard }; 288a3e8f492SMaxime Ripard 289a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 290a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 291a3e8f492SMaxime Ripard "PG4", "PG5"; 292a3e8f492SMaxime Ripard function = "mmc1"; 293a3e8f492SMaxime Ripard drive-strength = <30>; 294a3e8f492SMaxime Ripard bias-pull-up; 295a3e8f492SMaxime Ripard }; 296a3e8f492SMaxime Ripard 297a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 298a3e8f492SMaxime Ripard pins = "PC1", "PC5", "PC6", "PC8", "PC9", 299a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 300a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 301a3e8f492SMaxime Ripard function = "mmc2"; 302a3e8f492SMaxime Ripard drive-strength = <30>; 303a3e8f492SMaxime Ripard bias-pull-up; 304a3e8f492SMaxime Ripard }; 305a3e8f492SMaxime Ripard 3066bc37facSAndre Przywara uart0_pins_a: uart0@0 { 3076bc37facSAndre Przywara pins = "PB8", "PB9"; 3086bc37facSAndre Przywara function = "uart0"; 3096bc37facSAndre Przywara }; 310e7ba733dSAndre Przywara 311e7ba733dSAndre Przywara uart1_pins: uart1_pins { 312e7ba733dSAndre Przywara pins = "PG6", "PG7"; 313e7ba733dSAndre Przywara function = "uart1"; 314e7ba733dSAndre Przywara }; 315e7ba733dSAndre Przywara 316e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 317e7ba733dSAndre Przywara pins = "PG8", "PG9"; 318e7ba733dSAndre Przywara function = "uart1"; 319e7ba733dSAndre Przywara }; 32079825719SAndreas Färber 32179825719SAndreas Färber uart2_pins: uart2-pins { 32279825719SAndreas Färber pins = "PB0", "PB1"; 32379825719SAndreas Färber function = "uart2"; 32479825719SAndreas Färber }; 3252273aa16SAndreas Färber 3262273aa16SAndreas Färber uart3_pins: uart3-pins { 3272273aa16SAndreas Färber pins = "PD0", "PD1"; 3282273aa16SAndreas Färber function = "uart3"; 3292273aa16SAndreas Färber }; 3302273aa16SAndreas Färber 3312273aa16SAndreas Färber uart4_pins: uart4-pins { 3322273aa16SAndreas Färber pins = "PD2", "PD3"; 3332273aa16SAndreas Färber function = "uart4"; 3342273aa16SAndreas Färber }; 3352273aa16SAndreas Färber 3362273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 3372273aa16SAndreas Färber pins = "PD4", "PD5"; 3382273aa16SAndreas Färber function = "uart4"; 3392273aa16SAndreas Färber }; 3406bc37facSAndre Przywara }; 3416bc37facSAndre Przywara 3426bc37facSAndre Przywara uart0: serial@1c28000 { 3436bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3446bc37facSAndre Przywara reg = <0x01c28000 0x400>; 3456bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3466bc37facSAndre Przywara reg-shift = <2>; 3476bc37facSAndre Przywara reg-io-width = <4>; 348f98121f3SArnd Bergmann clocks = <&ccu 67>; 349f98121f3SArnd Bergmann resets = <&ccu 46>; 3506bc37facSAndre Przywara status = "disabled"; 3516bc37facSAndre Przywara }; 3526bc37facSAndre Przywara 3536bc37facSAndre Przywara uart1: serial@1c28400 { 3546bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3556bc37facSAndre Przywara reg = <0x01c28400 0x400>; 3566bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 3576bc37facSAndre Przywara reg-shift = <2>; 3586bc37facSAndre Przywara reg-io-width = <4>; 359f98121f3SArnd Bergmann clocks = <&ccu 68>; 360f98121f3SArnd Bergmann resets = <&ccu 47>; 3616bc37facSAndre Przywara status = "disabled"; 3626bc37facSAndre Przywara }; 3636bc37facSAndre Przywara 3646bc37facSAndre Przywara uart2: serial@1c28800 { 3656bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3666bc37facSAndre Przywara reg = <0x01c28800 0x400>; 3676bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 3686bc37facSAndre Przywara reg-shift = <2>; 3696bc37facSAndre Przywara reg-io-width = <4>; 370f98121f3SArnd Bergmann clocks = <&ccu 69>; 371f98121f3SArnd Bergmann resets = <&ccu 48>; 3726bc37facSAndre Przywara status = "disabled"; 3736bc37facSAndre Przywara }; 3746bc37facSAndre Przywara 3756bc37facSAndre Przywara uart3: serial@1c28c00 { 3766bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3776bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 3786bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 3796bc37facSAndre Przywara reg-shift = <2>; 3806bc37facSAndre Przywara reg-io-width = <4>; 381f98121f3SArnd Bergmann clocks = <&ccu 70>; 382f98121f3SArnd Bergmann resets = <&ccu 49>; 3836bc37facSAndre Przywara status = "disabled"; 3846bc37facSAndre Przywara }; 3856bc37facSAndre Przywara 3866bc37facSAndre Przywara uart4: serial@1c29000 { 3876bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 3886bc37facSAndre Przywara reg = <0x01c29000 0x400>; 3896bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 3906bc37facSAndre Przywara reg-shift = <2>; 3916bc37facSAndre Przywara reg-io-width = <4>; 392f98121f3SArnd Bergmann clocks = <&ccu 71>; 393f98121f3SArnd Bergmann resets = <&ccu 50>; 3946bc37facSAndre Przywara status = "disabled"; 3956bc37facSAndre Przywara }; 3966bc37facSAndre Przywara 3976bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 3986bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 3996bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 4006bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 401f98121f3SArnd Bergmann clocks = <&ccu 63>; 402f98121f3SArnd Bergmann resets = <&ccu 42>; 4036bc37facSAndre Przywara status = "disabled"; 4046bc37facSAndre Przywara #address-cells = <1>; 4056bc37facSAndre Przywara #size-cells = <0>; 4066bc37facSAndre Przywara }; 4076bc37facSAndre Przywara 4086bc37facSAndre Przywara i2c1: i2c@1c2b000 { 4096bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 4106bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 4116bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 412f98121f3SArnd Bergmann clocks = <&ccu 64>; 413f98121f3SArnd Bergmann resets = <&ccu 43>; 4146bc37facSAndre Przywara status = "disabled"; 4156bc37facSAndre Przywara #address-cells = <1>; 4166bc37facSAndre Przywara #size-cells = <0>; 4176bc37facSAndre Przywara }; 4186bc37facSAndre Przywara 4196bc37facSAndre Przywara i2c2: i2c@1c2b400 { 4206bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 4216bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 4226bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 423f98121f3SArnd Bergmann clocks = <&ccu 65>; 424f98121f3SArnd Bergmann resets = <&ccu 44>; 4256bc37facSAndre Przywara status = "disabled"; 4266bc37facSAndre Przywara #address-cells = <1>; 4276bc37facSAndre Przywara #size-cells = <0>; 4286bc37facSAndre Przywara }; 4296bc37facSAndre Przywara 4306bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 4316bc37facSAndre Przywara compatible = "arm,gic-400"; 4326bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 4336bc37facSAndre Przywara <0x01c82000 0x2000>, 4346bc37facSAndre Przywara <0x01c84000 0x2000>, 4356bc37facSAndre Przywara <0x01c86000 0x2000>; 4366bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 4376bc37facSAndre Przywara interrupt-controller; 4386bc37facSAndre Przywara #interrupt-cells = <3>; 4396bc37facSAndre Przywara }; 4406bc37facSAndre Przywara 4416bc37facSAndre Przywara rtc: rtc@1f00000 { 4426bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-rtc"; 4436bc37facSAndre Przywara reg = <0x01f00000 0x54>; 4446bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 4456bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 4466bc37facSAndre Przywara }; 447791a9e00SIcenowy Zheng 448791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 449791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 450791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 451791a9e00SIcenowy Zheng clocks = <&osc24M>, <&osc32k>, <&iosc>; 452791a9e00SIcenowy Zheng clock-names = "hosc", "losc", "iosc"; 453791a9e00SIcenowy Zheng #clock-cells = <1>; 454791a9e00SIcenowy Zheng #reset-cells = <1>; 455791a9e00SIcenowy Zheng }; 456ec427905SIcenowy Zheng 457ec427905SIcenowy Zheng r_pio: pinctrl@01f02c00 { 458ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 459ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 460ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 461ec427905SIcenowy Zheng clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; 462ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 463ec427905SIcenowy Zheng gpio-controller; 464ec427905SIcenowy Zheng #gpio-cells = <3>; 465ec427905SIcenowy Zheng interrupt-controller; 466ec427905SIcenowy Zheng #interrupt-cells = <3>; 4673b38fdedSIcenowy Zheng 4683b38fdedSIcenowy Zheng r_rsb_pins: rsb@0 { 4693b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 4703b38fdedSIcenowy Zheng function = "s_rsb"; 4713b38fdedSIcenowy Zheng }; 4723b38fdedSIcenowy Zheng }; 4733b38fdedSIcenowy Zheng 4743b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 4753b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 4763b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 4773b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 4783b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 4793b38fdedSIcenowy Zheng clock-frequency = <3000000>; 4803b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 4813b38fdedSIcenowy Zheng pinctrl-names = "default"; 4823b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 4833b38fdedSIcenowy Zheng status = "disabled"; 4843b38fdedSIcenowy Zheng #address-cells = <1>; 4853b38fdedSIcenowy Zheng #size-cells = <0>; 486ec427905SIcenowy Zheng }; 4876bc37facSAndre Przywara }; 4886bc37facSAndre Przywara}; 489