16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 46494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 476bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 48a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 49871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 506bc37facSAndre Przywara 516bc37facSAndre Przywara/ { 526bc37facSAndre Przywara interrupt-parent = <&gic>; 536bc37facSAndre Przywara #address-cells = <1>; 546bc37facSAndre Przywara #size-cells = <1>; 556bc37facSAndre Przywara 56c1cff65fSHarald Geyer chosen { 57c1cff65fSHarald Geyer #address-cells = <1>; 58c1cff65fSHarald Geyer #size-cells = <1>; 59c1cff65fSHarald Geyer ranges; 60c1cff65fSHarald Geyer 61c1cff65fSHarald Geyer/* 62c1cff65fSHarald Geyer * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU. 63c1cff65fSHarald Geyer * However there is no support for this clock on A64 yet, so we depend 64c1cff65fSHarald Geyer * on the upstream clocks here to keep them (and thus CLK_MIXER0) up. 65c1cff65fSHarald Geyer */ 66c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 67c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 68c1cff65fSHarald Geyer "simple-framebuffer"; 69c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 70c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 71c1cff65fSHarald Geyer <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; 72c1cff65fSHarald Geyer status = "disabled"; 73c1cff65fSHarald Geyer }; 74c1cff65fSHarald Geyer }; 75c1cff65fSHarald Geyer 766bc37facSAndre Przywara cpus { 776bc37facSAndre Przywara #address-cells = <1>; 786bc37facSAndre Przywara #size-cells = <0>; 796bc37facSAndre Przywara 806bc37facSAndre Przywara cpu0: cpu@0 { 816bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 826bc37facSAndre Przywara device_type = "cpu"; 836bc37facSAndre Przywara reg = <0>; 846bc37facSAndre Przywara enable-method = "psci"; 856bc37facSAndre Przywara }; 866bc37facSAndre Przywara 876bc37facSAndre Przywara cpu1: cpu@1 { 886bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 896bc37facSAndre Przywara device_type = "cpu"; 906bc37facSAndre Przywara reg = <1>; 916bc37facSAndre Przywara enable-method = "psci"; 926bc37facSAndre Przywara }; 936bc37facSAndre Przywara 946bc37facSAndre Przywara cpu2: cpu@2 { 956bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 966bc37facSAndre Przywara device_type = "cpu"; 976bc37facSAndre Przywara reg = <2>; 986bc37facSAndre Przywara enable-method = "psci"; 996bc37facSAndre Przywara }; 1006bc37facSAndre Przywara 1016bc37facSAndre Przywara cpu3: cpu@3 { 1026bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 1036bc37facSAndre Przywara device_type = "cpu"; 1046bc37facSAndre Przywara reg = <3>; 1056bc37facSAndre Przywara enable-method = "psci"; 1066bc37facSAndre Przywara }; 1076bc37facSAndre Przywara }; 1086bc37facSAndre Przywara 1096bc37facSAndre Przywara osc24M: osc24M_clk { 1106bc37facSAndre Przywara #clock-cells = <0>; 1116bc37facSAndre Przywara compatible = "fixed-clock"; 1126bc37facSAndre Przywara clock-frequency = <24000000>; 1136bc37facSAndre Przywara clock-output-names = "osc24M"; 1146bc37facSAndre Przywara }; 1156bc37facSAndre Przywara 1166bc37facSAndre Przywara osc32k: osc32k_clk { 1176bc37facSAndre Przywara #clock-cells = <0>; 1186bc37facSAndre Przywara compatible = "fixed-clock"; 1196bc37facSAndre Przywara clock-frequency = <32768>; 1206bc37facSAndre Przywara clock-output-names = "osc32k"; 1216bc37facSAndre Przywara }; 1226bc37facSAndre Przywara 123791a9e00SIcenowy Zheng iosc: internal-osc-clk { 124791a9e00SIcenowy Zheng #clock-cells = <0>; 125791a9e00SIcenowy Zheng compatible = "fixed-clock"; 126791a9e00SIcenowy Zheng clock-frequency = <16000000>; 127791a9e00SIcenowy Zheng clock-accuracy = <300000000>; 128791a9e00SIcenowy Zheng clock-output-names = "iosc"; 129791a9e00SIcenowy Zheng }; 130791a9e00SIcenowy Zheng 1316bc37facSAndre Przywara psci { 1326bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1336bc37facSAndre Przywara method = "smc"; 1346bc37facSAndre Przywara }; 1356bc37facSAndre Przywara 13678e07137SMarcus Cooper sound_spdif { 13778e07137SMarcus Cooper compatible = "simple-audio-card"; 13878e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 13978e07137SMarcus Cooper 14078e07137SMarcus Cooper simple-audio-card,cpu { 14178e07137SMarcus Cooper sound-dai = <&spdif>; 14278e07137SMarcus Cooper }; 14378e07137SMarcus Cooper 14478e07137SMarcus Cooper simple-audio-card,codec { 14578e07137SMarcus Cooper sound-dai = <&spdif_out>; 14678e07137SMarcus Cooper }; 14778e07137SMarcus Cooper }; 14878e07137SMarcus Cooper 14978e07137SMarcus Cooper spdif_out: spdif-out { 15078e07137SMarcus Cooper #sound-dai-cells = <0>; 15178e07137SMarcus Cooper compatible = "linux,spdif-dit"; 15278e07137SMarcus Cooper }; 15378e07137SMarcus Cooper 1546bc37facSAndre Przywara timer { 1556bc37facSAndre Przywara compatible = "arm,armv8-timer"; 1566bc37facSAndre Przywara interrupts = <GIC_PPI 13 1576bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1586bc37facSAndre Przywara <GIC_PPI 14 1596bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1606bc37facSAndre Przywara <GIC_PPI 11 1616bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1626bc37facSAndre Przywara <GIC_PPI 10 1636bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1646bc37facSAndre Przywara }; 1656bc37facSAndre Przywara 1666bc37facSAndre Przywara soc { 1676bc37facSAndre Przywara compatible = "simple-bus"; 1686bc37facSAndre Przywara #address-cells = <1>; 1696bc37facSAndre Przywara #size-cells = <1>; 1706bc37facSAndre Przywara ranges; 1716bc37facSAndre Przywara 17279b95360SCorentin Labbe syscon: syscon@1c00000 { 1731f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 17479b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 1751f1f5183SIcenowy Zheng #address-cells = <1>; 1761f1f5183SIcenowy Zheng #size-cells = <1>; 1771f1f5183SIcenowy Zheng ranges; 1781f1f5183SIcenowy Zheng 1791f1f5183SIcenowy Zheng sram_c: sram@18000 { 1801f1f5183SIcenowy Zheng compatible = "mmio-sram"; 1811f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 1821f1f5183SIcenowy Zheng #address-cells = <1>; 1831f1f5183SIcenowy Zheng #size-cells = <1>; 1841f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 1851f1f5183SIcenowy Zheng 1861f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 1871f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 1881f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 1891f1f5183SIcenowy Zheng }; 1901f1f5183SIcenowy Zheng }; 19179b95360SCorentin Labbe }; 19279b95360SCorentin Labbe 193c32637e0SStefan Brüns dma: dma-controller@1c02000 { 194c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 195c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 196c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 197c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 198c32637e0SStefan Brüns dma-channels = <8>; 199c32637e0SStefan Brüns dma-requests = <27>; 200c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 201c32637e0SStefan Brüns #dma-cells = <1>; 202c32637e0SStefan Brüns }; 203c32637e0SStefan Brüns 204f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 205f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 206f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 207f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 208f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 209f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 210f3dff347SAndre Przywara reset-names = "ahb"; 211f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 21222be992fSMaxime Ripard max-frequency = <150000000>; 213f3dff347SAndre Przywara status = "disabled"; 214f3dff347SAndre Przywara #address-cells = <1>; 215f3dff347SAndre Przywara #size-cells = <0>; 216f3dff347SAndre Przywara }; 217f3dff347SAndre Przywara 218f3dff347SAndre Przywara mmc1: mmc@1c10000 { 219f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 220f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 221f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 222f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 223f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 224f3dff347SAndre Przywara reset-names = "ahb"; 225f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 22622be992fSMaxime Ripard max-frequency = <150000000>; 227f3dff347SAndre Przywara status = "disabled"; 228f3dff347SAndre Przywara #address-cells = <1>; 229f3dff347SAndre Przywara #size-cells = <0>; 230f3dff347SAndre Przywara }; 231f3dff347SAndre Przywara 232f3dff347SAndre Przywara mmc2: mmc@1c11000 { 233f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 234f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 235f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 236f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 237f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 238f3dff347SAndre Przywara reset-names = "ahb"; 239f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 24022be992fSMaxime Ripard max-frequency = <200000000>; 241f3dff347SAndre Przywara status = "disabled"; 242f3dff347SAndre Przywara #address-cells = <1>; 243f3dff347SAndre Przywara #size-cells = <0>; 244f3dff347SAndre Przywara }; 245f3dff347SAndre Przywara 246d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 247972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 248972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 249972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 250972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 251972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 252972a3ecdSIcenowy Zheng interrupt-names = "mc"; 253972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 254972a3ecdSIcenowy Zheng phy-names = "usb"; 255972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 256972a3ecdSIcenowy Zheng status = "disabled"; 257972a3ecdSIcenowy Zheng }; 258972a3ecdSIcenowy Zheng 259d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 260a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 261a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 2620d984797SIcenowy Zheng <0x01c1a800 0x4>, 263a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 264a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 2650d984797SIcenowy Zheng "pmu0", 266a004ee35SIcenowy Zheng "pmu1"; 267a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 268a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 269a004ee35SIcenowy Zheng clock-names = "usb0_phy", 270a004ee35SIcenowy Zheng "usb1_phy"; 271a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 272a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 273a004ee35SIcenowy Zheng reset-names = "usb0_reset", 274a004ee35SIcenowy Zheng "usb1_reset"; 275a004ee35SIcenowy Zheng status = "disabled"; 276a004ee35SIcenowy Zheng #phy-cells = <1>; 277a004ee35SIcenowy Zheng }; 278a004ee35SIcenowy Zheng 279d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 280dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 281dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 282dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 283dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 284dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 285dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 286dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 287dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 288dc03a047SIcenowy Zheng status = "disabled"; 289dc03a047SIcenowy Zheng }; 290dc03a047SIcenowy Zheng 291d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 292dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 293dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 294dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 295dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 296dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 297dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 298dc03a047SIcenowy Zheng status = "disabled"; 299dc03a047SIcenowy Zheng }; 300dc03a047SIcenowy Zheng 301d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 302a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 303a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 304a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 305a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 306a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 307a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 308a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 309a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 310a004ee35SIcenowy Zheng phys = <&usbphy 1>; 311a004ee35SIcenowy Zheng phy-names = "usb"; 312a004ee35SIcenowy Zheng status = "disabled"; 313a004ee35SIcenowy Zheng }; 314a004ee35SIcenowy Zheng 315d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 316a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 317a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 318a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 319a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 320a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 321a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 322a004ee35SIcenowy Zheng phys = <&usbphy 1>; 323a004ee35SIcenowy Zheng phy-names = "usb"; 324a004ee35SIcenowy Zheng status = "disabled"; 325a004ee35SIcenowy Zheng }; 326a004ee35SIcenowy Zheng 327d6c9da12SCorentin LABBE ccu: clock@1c20000 { 3286bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 3296bc37facSAndre Przywara reg = <0x01c20000 0x400>; 3306bc37facSAndre Przywara clocks = <&osc24M>, <&osc32k>; 3316bc37facSAndre Przywara clock-names = "hosc", "losc"; 3326bc37facSAndre Przywara #clock-cells = <1>; 3336bc37facSAndre Przywara #reset-cells = <1>; 3346bc37facSAndre Przywara }; 3356bc37facSAndre Przywara 3366bc37facSAndre Przywara pio: pinctrl@1c20800 { 3376bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 3386bc37facSAndre Przywara reg = <0x01c20800 0x400>; 3396bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 3406bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 3416bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 342f98121f3SArnd Bergmann clocks = <&ccu 58>; 3436bc37facSAndre Przywara gpio-controller; 3446bc37facSAndre Przywara #gpio-cells = <3>; 3456bc37facSAndre Przywara interrupt-controller; 3466bc37facSAndre Przywara #interrupt-cells = <3>; 3476bc37facSAndre Przywara 34811239fe6SHarald Geyer i2c0_pins: i2c0_pins { 34911239fe6SHarald Geyer pins = "PH0", "PH1"; 35011239fe6SHarald Geyer function = "i2c0"; 35111239fe6SHarald Geyer }; 35211239fe6SHarald Geyer 3536bc37facSAndre Przywara i2c1_pins: i2c1_pins { 3546bc37facSAndre Przywara pins = "PH2", "PH3"; 3556bc37facSAndre Przywara function = "i2c1"; 3566bc37facSAndre Przywara }; 3576bc37facSAndre Przywara 358a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 359a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 360a3e8f492SMaxime Ripard "PF4", "PF5"; 361a3e8f492SMaxime Ripard function = "mmc0"; 362a3e8f492SMaxime Ripard drive-strength = <30>; 363a3e8f492SMaxime Ripard bias-pull-up; 364a3e8f492SMaxime Ripard }; 365a3e8f492SMaxime Ripard 366a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 367a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 368a3e8f492SMaxime Ripard "PG4", "PG5"; 369a3e8f492SMaxime Ripard function = "mmc1"; 370a3e8f492SMaxime Ripard drive-strength = <30>; 371a3e8f492SMaxime Ripard bias-pull-up; 372a3e8f492SMaxime Ripard }; 373a3e8f492SMaxime Ripard 374a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 375a3e8f492SMaxime Ripard pins = "PC1", "PC5", "PC6", "PC8", "PC9", 376a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 377a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 378a3e8f492SMaxime Ripard function = "mmc2"; 379a3e8f492SMaxime Ripard drive-strength = <30>; 380a3e8f492SMaxime Ripard bias-pull-up; 381a3e8f492SMaxime Ripard }; 382a3e8f492SMaxime Ripard 383b5df280bSAndre Przywara pwm_pin: pwm_pin { 384b5df280bSAndre Przywara pins = "PD22"; 385b5df280bSAndre Przywara function = "pwm"; 386b5df280bSAndre Przywara }; 387b5df280bSAndre Przywara 388e53f67e9SCorentin Labbe rmii_pins: rmii_pins { 389e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 390e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 391e53f67e9SCorentin Labbe function = "emac"; 392e53f67e9SCorentin Labbe drive-strength = <40>; 393e53f67e9SCorentin Labbe }; 394e53f67e9SCorentin Labbe 395e53f67e9SCorentin Labbe rgmii_pins: rgmii_pins { 396e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 397e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 398e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 399e53f67e9SCorentin Labbe function = "emac"; 400e53f67e9SCorentin Labbe drive-strength = <40>; 401e53f67e9SCorentin Labbe }; 402e53f67e9SCorentin Labbe 403b399d2acSMarcus Cooper spdif_tx_pin: spdif { 404b399d2acSMarcus Cooper pins = "PH8"; 405b399d2acSMarcus Cooper function = "spdif"; 406b399d2acSMarcus Cooper }; 407b399d2acSMarcus Cooper 408b518bb15SStefan Brüns spi0_pins: spi0 { 409b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 410b518bb15SStefan Brüns function = "spi0"; 411b518bb15SStefan Brüns }; 412b518bb15SStefan Brüns 413b518bb15SStefan Brüns spi1_pins: spi1 { 414b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 415b518bb15SStefan Brüns function = "spi1"; 416b518bb15SStefan Brüns }; 417b518bb15SStefan Brüns 41892d378fbSCorentin LABBE uart0_pins_a: uart0 { 4196bc37facSAndre Przywara pins = "PB8", "PB9"; 4206bc37facSAndre Przywara function = "uart0"; 4216bc37facSAndre Przywara }; 422e7ba733dSAndre Przywara 423e7ba733dSAndre Przywara uart1_pins: uart1_pins { 424e7ba733dSAndre Przywara pins = "PG6", "PG7"; 425e7ba733dSAndre Przywara function = "uart1"; 426e7ba733dSAndre Przywara }; 427e7ba733dSAndre Przywara 428e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 429e7ba733dSAndre Przywara pins = "PG8", "PG9"; 430e7ba733dSAndre Przywara function = "uart1"; 431e7ba733dSAndre Przywara }; 43279825719SAndreas Färber 43379825719SAndreas Färber uart2_pins: uart2-pins { 43479825719SAndreas Färber pins = "PB0", "PB1"; 43579825719SAndreas Färber function = "uart2"; 43679825719SAndreas Färber }; 4372273aa16SAndreas Färber 4382273aa16SAndreas Färber uart3_pins: uart3-pins { 4392273aa16SAndreas Färber pins = "PD0", "PD1"; 4402273aa16SAndreas Färber function = "uart3"; 4412273aa16SAndreas Färber }; 4422273aa16SAndreas Färber 4432273aa16SAndreas Färber uart4_pins: uart4-pins { 4442273aa16SAndreas Färber pins = "PD2", "PD3"; 4452273aa16SAndreas Färber function = "uart4"; 4462273aa16SAndreas Färber }; 4472273aa16SAndreas Färber 4482273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 4492273aa16SAndreas Färber pins = "PD4", "PD5"; 4502273aa16SAndreas Färber function = "uart4"; 4512273aa16SAndreas Färber }; 4526bc37facSAndre Przywara }; 4536bc37facSAndre Przywara 454b399d2acSMarcus Cooper spdif: spdif@1c21000 { 455b399d2acSMarcus Cooper #sound-dai-cells = <0>; 456b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 457b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 458b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 459b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 460b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 461b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 462b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 463b399d2acSMarcus Cooper dmas = <&dma 2>; 464b399d2acSMarcus Cooper dma-names = "tx"; 465b399d2acSMarcus Cooper pinctrl-names = "default"; 466b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 467b399d2acSMarcus Cooper status = "disabled"; 468b399d2acSMarcus Cooper }; 469b399d2acSMarcus Cooper 4701c92c009SMarcus Cooper i2s0: i2s@1c22000 { 4711c92c009SMarcus Cooper #sound-dai-cells = <0>; 4721c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 4731c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 4741c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 4751c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4761c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 4771c92c009SMarcus Cooper clock-names = "apb", "mod"; 4781c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 4791c92c009SMarcus Cooper dma-names = "rx", "tx"; 4801c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 4811c92c009SMarcus Cooper status = "disabled"; 4821c92c009SMarcus Cooper }; 4831c92c009SMarcus Cooper 4841c92c009SMarcus Cooper i2s1: i2s@1c22400 { 4851c92c009SMarcus Cooper #sound-dai-cells = <0>; 4861c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 4871c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 4881c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 4891c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4901c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 4911c92c009SMarcus Cooper clock-names = "apb", "mod"; 4921c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 4931c92c009SMarcus Cooper dma-names = "rx", "tx"; 4941c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 4951c92c009SMarcus Cooper status = "disabled"; 4961c92c009SMarcus Cooper }; 4971c92c009SMarcus Cooper 4986bc37facSAndre Przywara uart0: serial@1c28000 { 4996bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5006bc37facSAndre Przywara reg = <0x01c28000 0x400>; 5016bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5026bc37facSAndre Przywara reg-shift = <2>; 5036bc37facSAndre Przywara reg-io-width = <4>; 504494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 505494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 5066bc37facSAndre Przywara status = "disabled"; 5076bc37facSAndre Przywara }; 5086bc37facSAndre Przywara 5096bc37facSAndre Przywara uart1: serial@1c28400 { 5106bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5116bc37facSAndre Przywara reg = <0x01c28400 0x400>; 5126bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 5136bc37facSAndre Przywara reg-shift = <2>; 5146bc37facSAndre Przywara reg-io-width = <4>; 515494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 516494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 5176bc37facSAndre Przywara status = "disabled"; 5186bc37facSAndre Przywara }; 5196bc37facSAndre Przywara 5206bc37facSAndre Przywara uart2: serial@1c28800 { 5216bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5226bc37facSAndre Przywara reg = <0x01c28800 0x400>; 5236bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 5246bc37facSAndre Przywara reg-shift = <2>; 5256bc37facSAndre Przywara reg-io-width = <4>; 526494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 527494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 5286bc37facSAndre Przywara status = "disabled"; 5296bc37facSAndre Przywara }; 5306bc37facSAndre Przywara 5316bc37facSAndre Przywara uart3: serial@1c28c00 { 5326bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5336bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 5346bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 5356bc37facSAndre Przywara reg-shift = <2>; 5366bc37facSAndre Przywara reg-io-width = <4>; 537494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 538494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 5396bc37facSAndre Przywara status = "disabled"; 5406bc37facSAndre Przywara }; 5416bc37facSAndre Przywara 5426bc37facSAndre Przywara uart4: serial@1c29000 { 5436bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 5446bc37facSAndre Przywara reg = <0x01c29000 0x400>; 5456bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 5466bc37facSAndre Przywara reg-shift = <2>; 5476bc37facSAndre Przywara reg-io-width = <4>; 548494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 549494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 5506bc37facSAndre Przywara status = "disabled"; 5516bc37facSAndre Przywara }; 5526bc37facSAndre Przywara 5536bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 5546bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5556bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 5566bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 557494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 558494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 5596bc37facSAndre Przywara status = "disabled"; 5606bc37facSAndre Przywara #address-cells = <1>; 5616bc37facSAndre Przywara #size-cells = <0>; 5626bc37facSAndre Przywara }; 5636bc37facSAndre Przywara 5646bc37facSAndre Przywara i2c1: i2c@1c2b000 { 5656bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5666bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 5676bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 568494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 569494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 5706bc37facSAndre Przywara status = "disabled"; 5716bc37facSAndre Przywara #address-cells = <1>; 5726bc37facSAndre Przywara #size-cells = <0>; 5736bc37facSAndre Przywara }; 5746bc37facSAndre Przywara 5756bc37facSAndre Przywara i2c2: i2c@1c2b400 { 5766bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 5776bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 5786bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 579494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 580494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 5816bc37facSAndre Przywara status = "disabled"; 5826bc37facSAndre Przywara #address-cells = <1>; 5836bc37facSAndre Przywara #size-cells = <0>; 5846bc37facSAndre Przywara }; 5856bc37facSAndre Przywara 586b518bb15SStefan Brüns 587d6c9da12SCorentin LABBE spi0: spi@1c68000 { 588b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 589b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 590b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 591b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 592b518bb15SStefan Brüns clock-names = "ahb", "mod"; 59306c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 59406c1258aSStefan Brüns dma-names = "rx", "tx"; 595b518bb15SStefan Brüns pinctrl-names = "default"; 596b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 597b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 598b518bb15SStefan Brüns status = "disabled"; 599b518bb15SStefan Brüns num-cs = <1>; 600b518bb15SStefan Brüns #address-cells = <1>; 601b518bb15SStefan Brüns #size-cells = <0>; 602b518bb15SStefan Brüns }; 603b518bb15SStefan Brüns 604d6c9da12SCorentin LABBE spi1: spi@1c69000 { 605b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 606b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 607b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 608b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 609b518bb15SStefan Brüns clock-names = "ahb", "mod"; 61006c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 61106c1258aSStefan Brüns dma-names = "rx", "tx"; 612b518bb15SStefan Brüns pinctrl-names = "default"; 613b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 614b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 615b518bb15SStefan Brüns status = "disabled"; 616b518bb15SStefan Brüns num-cs = <1>; 617b518bb15SStefan Brüns #address-cells = <1>; 618b518bb15SStefan Brüns #size-cells = <0>; 619b518bb15SStefan Brüns }; 620b518bb15SStefan Brüns 62194f44288SCorentin Labbe emac: ethernet@1c30000 { 62294f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 62394f44288SCorentin Labbe syscon = <&syscon>; 62494f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 62594f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 62694f44288SCorentin Labbe interrupt-names = "macirq"; 62794f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 62894f44288SCorentin Labbe reset-names = "stmmaceth"; 62994f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 63094f44288SCorentin Labbe clock-names = "stmmaceth"; 63194f44288SCorentin Labbe status = "disabled"; 63294f44288SCorentin Labbe #address-cells = <1>; 63394f44288SCorentin Labbe #size-cells = <0>; 63494f44288SCorentin Labbe 63594f44288SCorentin Labbe mdio: mdio { 63616416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 63794f44288SCorentin Labbe #address-cells = <1>; 63894f44288SCorentin Labbe #size-cells = <0>; 63994f44288SCorentin Labbe }; 64094f44288SCorentin Labbe }; 64194f44288SCorentin Labbe 6426bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 6436bc37facSAndre Przywara compatible = "arm,gic-400"; 6446bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 6456bc37facSAndre Przywara <0x01c82000 0x2000>, 6466bc37facSAndre Przywara <0x01c84000 0x2000>, 6476bc37facSAndre Przywara <0x01c86000 0x2000>; 6486bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 6496bc37facSAndre Przywara interrupt-controller; 6506bc37facSAndre Przywara #interrupt-cells = <3>; 6516bc37facSAndre Przywara }; 6526bc37facSAndre Przywara 653b5df280bSAndre Przywara pwm: pwm@1c21400 { 654b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 655b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 656b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 657b5df280bSAndre Przywara clocks = <&osc24M>; 658b5df280bSAndre Przywara pinctrl-names = "default"; 659b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 660b5df280bSAndre Przywara #pwm-cells = <3>; 661b5df280bSAndre Przywara status = "disabled"; 662b5df280bSAndre Przywara }; 663b5df280bSAndre Przywara 6646bc37facSAndre Przywara rtc: rtc@1f00000 { 6656bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-rtc"; 6666bc37facSAndre Przywara reg = <0x01f00000 0x54>; 6676bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 6686bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 669e1a9a474SJagan Teki clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 670e1a9a474SJagan Teki clocks = <&osc32k>; 671e1a9a474SJagan Teki #clock-cells = <1>; 6726bc37facSAndre Przywara }; 673791a9e00SIcenowy Zheng 674535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 675535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 676535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 677535ca508SIcenowy Zheng interrupt-controller; 678535ca508SIcenowy Zheng #interrupt-cells = <2>; 679535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 680535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 681535ca508SIcenowy Zheng }; 682535ca508SIcenowy Zheng 683791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 684791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 685791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 686f74994a9SChen-Yu Tsai clocks = <&osc24M>, <&osc32k>, <&iosc>, 687f74994a9SChen-Yu Tsai <&ccu 11>; 688f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 689791a9e00SIcenowy Zheng #clock-cells = <1>; 690791a9e00SIcenowy Zheng #reset-cells = <1>; 691791a9e00SIcenowy Zheng }; 692ec427905SIcenowy Zheng 693871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 694871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 695871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 696871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 697871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 698871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 699871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 700871b5352SIcenowy Zheng status = "disabled"; 701871b5352SIcenowy Zheng #address-cells = <1>; 702871b5352SIcenowy Zheng #size-cells = <0>; 703871b5352SIcenowy Zheng }; 704871b5352SIcenowy Zheng 705b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 706b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 707b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 708b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 709b5df280bSAndre Przywara clocks = <&osc24M>; 710b5df280bSAndre Przywara pinctrl-names = "default"; 711b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 712b5df280bSAndre Przywara #pwm-cells = <3>; 713b5df280bSAndre Przywara status = "disabled"; 714b5df280bSAndre Przywara }; 715b5df280bSAndre Przywara 716d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 717ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 718ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 719ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 720494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 721ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 722ec427905SIcenowy Zheng gpio-controller; 723ec427905SIcenowy Zheng #gpio-cells = <3>; 724ec427905SIcenowy Zheng interrupt-controller; 725ec427905SIcenowy Zheng #interrupt-cells = <3>; 7263b38fdedSIcenowy Zheng 727871b5352SIcenowy Zheng r_i2c_pins_a: i2c-a { 728871b5352SIcenowy Zheng pins = "PL8", "PL9"; 729871b5352SIcenowy Zheng function = "s_i2c"; 730871b5352SIcenowy Zheng }; 731871b5352SIcenowy Zheng 732b5df280bSAndre Przywara r_pwm_pin: pwm { 733b5df280bSAndre Przywara pins = "PL10"; 734b5df280bSAndre Przywara function = "s_pwm"; 735b5df280bSAndre Przywara }; 736b5df280bSAndre Przywara 73792d378fbSCorentin LABBE r_rsb_pins: rsb { 7383b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 7393b38fdedSIcenowy Zheng function = "s_rsb"; 7403b38fdedSIcenowy Zheng }; 7413b38fdedSIcenowy Zheng }; 7423b38fdedSIcenowy Zheng 7433b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 7443b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 7453b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 7463b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 7473b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 7483b38fdedSIcenowy Zheng clock-frequency = <3000000>; 7493b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 7503b38fdedSIcenowy Zheng pinctrl-names = "default"; 7513b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 7523b38fdedSIcenowy Zheng status = "disabled"; 7533b38fdedSIcenowy Zheng #address-cells = <1>; 7543b38fdedSIcenowy Zheng #size-cells = <0>; 755ec427905SIcenowy Zheng }; 756d4185043SHarald Geyer 757d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 758d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 759d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 760d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 761d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 762d4185043SHarald Geyer }; 7636bc37facSAndre Przywara }; 7646bc37facSAndre Przywara}; 765