16bc37facSAndre Przywara/* 26bc37facSAndre Przywara * Copyright (C) 2016 ARM Ltd. 36bc37facSAndre Przywara * based on the Allwinner H3 dtsi: 46bc37facSAndre Przywara * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara * 66bc37facSAndre Przywara * This file is dual-licensed: you can use it either under the terms 76bc37facSAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 86bc37facSAndre Przywara * licensing only applies to this file, and not this project as a 96bc37facSAndre Przywara * whole. 106bc37facSAndre Przywara * 116bc37facSAndre Przywara * a) This file is free software; you can redistribute it and/or 126bc37facSAndre Przywara * modify it under the terms of the GNU General Public License as 136bc37facSAndre Przywara * published by the Free Software Foundation; either version 2 of the 146bc37facSAndre Przywara * License, or (at your option) any later version. 156bc37facSAndre Przywara * 166bc37facSAndre Przywara * This file is distributed in the hope that it will be useful, 176bc37facSAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 186bc37facSAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 196bc37facSAndre Przywara * GNU General Public License for more details. 206bc37facSAndre Przywara * 216bc37facSAndre Przywara * Or, alternatively, 226bc37facSAndre Przywara * 236bc37facSAndre Przywara * b) Permission is hereby granted, free of charge, to any person 246bc37facSAndre Przywara * obtaining a copy of this software and associated documentation 256bc37facSAndre Przywara * files (the "Software"), to deal in the Software without 266bc37facSAndre Przywara * restriction, including without limitation the rights to use, 276bc37facSAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 286bc37facSAndre Przywara * sell copies of the Software, and to permit persons to whom the 296bc37facSAndre Przywara * Software is furnished to do so, subject to the following 306bc37facSAndre Przywara * conditions: 316bc37facSAndre Przywara * 326bc37facSAndre Przywara * The above copyright notice and this permission notice shall be 336bc37facSAndre Przywara * included in all copies or substantial portions of the Software. 346bc37facSAndre Przywara * 356bc37facSAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 366bc37facSAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 376bc37facSAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 386bc37facSAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 396bc37facSAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 406bc37facSAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 416bc37facSAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 426bc37facSAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 436bc37facSAndre Przywara */ 446bc37facSAndre Przywara 45a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 462c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 47494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 486bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 49a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 502c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 51871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 526bc37facSAndre Przywara 536bc37facSAndre Przywara/ { 546bc37facSAndre Przywara interrupt-parent = <&gic>; 556bc37facSAndre Przywara #address-cells = <1>; 566bc37facSAndre Przywara #size-cells = <1>; 576bc37facSAndre Przywara 58c1cff65fSHarald Geyer chosen { 59c1cff65fSHarald Geyer #address-cells = <1>; 60c1cff65fSHarald Geyer #size-cells = <1>; 61c1cff65fSHarald Geyer ranges; 62c1cff65fSHarald Geyer 63c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 64c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 65c1cff65fSHarald Geyer "simple-framebuffer"; 66c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 67c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 682c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 69c1cff65fSHarald Geyer status = "disabled"; 70c1cff65fSHarald Geyer }; 71fca63f58SIcenowy Zheng 72fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 73fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 74fca63f58SIcenowy Zheng "simple-framebuffer"; 75fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 76fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 77fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78fca63f58SIcenowy Zheng status = "disabled"; 79fca63f58SIcenowy Zheng }; 80c1cff65fSHarald Geyer }; 81c1cff65fSHarald Geyer 826bc37facSAndre Przywara cpus { 836bc37facSAndre Przywara #address-cells = <1>; 846bc37facSAndre Przywara #size-cells = <0>; 856bc37facSAndre Przywara 866bc37facSAndre Przywara cpu0: cpu@0 { 876bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 886bc37facSAndre Przywara device_type = "cpu"; 896bc37facSAndre Przywara reg = <0>; 906bc37facSAndre Przywara enable-method = "psci"; 9139defc81SAndre Przywara next-level-cache = <&L2>; 926bc37facSAndre Przywara }; 936bc37facSAndre Przywara 946bc37facSAndre Przywara cpu1: cpu@1 { 956bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 966bc37facSAndre Przywara device_type = "cpu"; 976bc37facSAndre Przywara reg = <1>; 986bc37facSAndre Przywara enable-method = "psci"; 9939defc81SAndre Przywara next-level-cache = <&L2>; 1006bc37facSAndre Przywara }; 1016bc37facSAndre Przywara 1026bc37facSAndre Przywara cpu2: cpu@2 { 1036bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 1046bc37facSAndre Przywara device_type = "cpu"; 1056bc37facSAndre Przywara reg = <2>; 1066bc37facSAndre Przywara enable-method = "psci"; 10739defc81SAndre Przywara next-level-cache = <&L2>; 1086bc37facSAndre Przywara }; 1096bc37facSAndre Przywara 1106bc37facSAndre Przywara cpu3: cpu@3 { 1116bc37facSAndre Przywara compatible = "arm,cortex-a53", "arm,armv8"; 1126bc37facSAndre Przywara device_type = "cpu"; 1136bc37facSAndre Przywara reg = <3>; 1146bc37facSAndre Przywara enable-method = "psci"; 11539defc81SAndre Przywara next-level-cache = <&L2>; 11639defc81SAndre Przywara }; 11739defc81SAndre Przywara 11839defc81SAndre Przywara L2: l2-cache { 11939defc81SAndre Przywara compatible = "cache"; 12039defc81SAndre Przywara cache-level = <2>; 1216bc37facSAndre Przywara }; 1226bc37facSAndre Przywara }; 1236bc37facSAndre Przywara 124e85f28e0SJagan Teki de: display-engine { 125e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 126e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 127e85f28e0SJagan Teki <&mixer1>; 128e85f28e0SJagan Teki status = "disabled"; 129e85f28e0SJagan Teki }; 130e85f28e0SJagan Teki 1316bc37facSAndre Przywara osc24M: osc24M_clk { 1326bc37facSAndre Przywara #clock-cells = <0>; 1336bc37facSAndre Przywara compatible = "fixed-clock"; 1346bc37facSAndre Przywara clock-frequency = <24000000>; 1356bc37facSAndre Przywara clock-output-names = "osc24M"; 1366bc37facSAndre Przywara }; 1376bc37facSAndre Przywara 1386bc37facSAndre Przywara osc32k: osc32k_clk { 1396bc37facSAndre Przywara #clock-cells = <0>; 1406bc37facSAndre Przywara compatible = "fixed-clock"; 1416bc37facSAndre Przywara clock-frequency = <32768>; 1426bc37facSAndre Przywara clock-output-names = "osc32k"; 1436bc37facSAndre Przywara }; 1446bc37facSAndre Przywara 145791a9e00SIcenowy Zheng iosc: internal-osc-clk { 146791a9e00SIcenowy Zheng #clock-cells = <0>; 147791a9e00SIcenowy Zheng compatible = "fixed-clock"; 148791a9e00SIcenowy Zheng clock-frequency = <16000000>; 149791a9e00SIcenowy Zheng clock-accuracy = <300000000>; 150791a9e00SIcenowy Zheng clock-output-names = "iosc"; 151791a9e00SIcenowy Zheng }; 152791a9e00SIcenowy Zheng 1536bc37facSAndre Przywara psci { 1546bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1556bc37facSAndre Przywara method = "smc"; 1566bc37facSAndre Przywara }; 1576bc37facSAndre Przywara 158ec4a9540SVasily Khoruzhick sound: sound { 159ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 160ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 161ec4a9540SVasily Khoruzhick simple-audio-card,format = "i2s"; 162ec4a9540SVasily Khoruzhick simple-audio-card,frame-master = <&cpudai>; 163ec4a9540SVasily Khoruzhick simple-audio-card,bitclock-master = <&cpudai>; 164ec4a9540SVasily Khoruzhick simple-audio-card,mclk-fs = <128>; 165ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 166ec4a9540SVasily Khoruzhick simple-audio-card,routing = 167ec4a9540SVasily Khoruzhick "Left DAC", "AIF1 Slot 0 Left", 168ec4a9540SVasily Khoruzhick "Right DAC", "AIF1 Slot 0 Right", 169ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Left ADC", "Left ADC", 170ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Right ADC", "Right ADC"; 171ec4a9540SVasily Khoruzhick status = "disabled"; 172ec4a9540SVasily Khoruzhick 173ec4a9540SVasily Khoruzhick cpudai: simple-audio-card,cpu { 174ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 175ec4a9540SVasily Khoruzhick }; 176ec4a9540SVasily Khoruzhick 177ec4a9540SVasily Khoruzhick link_codec: simple-audio-card,codec { 178ec4a9540SVasily Khoruzhick sound-dai = <&codec>; 179ec4a9540SVasily Khoruzhick }; 180ec4a9540SVasily Khoruzhick }; 181ec4a9540SVasily Khoruzhick 18278e07137SMarcus Cooper sound_spdif { 18378e07137SMarcus Cooper compatible = "simple-audio-card"; 18478e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 18578e07137SMarcus Cooper 18678e07137SMarcus Cooper simple-audio-card,cpu { 18778e07137SMarcus Cooper sound-dai = <&spdif>; 18878e07137SMarcus Cooper }; 18978e07137SMarcus Cooper 19078e07137SMarcus Cooper simple-audio-card,codec { 19178e07137SMarcus Cooper sound-dai = <&spdif_out>; 19278e07137SMarcus Cooper }; 19378e07137SMarcus Cooper }; 19478e07137SMarcus Cooper 19578e07137SMarcus Cooper spdif_out: spdif-out { 19678e07137SMarcus Cooper #sound-dai-cells = <0>; 19778e07137SMarcus Cooper compatible = "linux,spdif-dit"; 19878e07137SMarcus Cooper }; 19978e07137SMarcus Cooper 2006bc37facSAndre Przywara timer { 2016bc37facSAndre Przywara compatible = "arm,armv8-timer"; 2026bc37facSAndre Przywara interrupts = <GIC_PPI 13 2036bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2046bc37facSAndre Przywara <GIC_PPI 14 2056bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2066bc37facSAndre Przywara <GIC_PPI 11 2076bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2086bc37facSAndre Przywara <GIC_PPI 10 2096bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 2106bc37facSAndre Przywara }; 2116bc37facSAndre Przywara 2126bc37facSAndre Przywara soc { 2136bc37facSAndre Przywara compatible = "simple-bus"; 2146bc37facSAndre Przywara #address-cells = <1>; 2156bc37facSAndre Przywara #size-cells = <1>; 2166bc37facSAndre Przywara ranges; 2176bc37facSAndre Przywara 2182c796fc8SIcenowy Zheng de2@1000000 { 2192c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 2202c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 2212c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 2222c796fc8SIcenowy Zheng #address-cells = <1>; 2232c796fc8SIcenowy Zheng #size-cells = <1>; 2242c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 2252c796fc8SIcenowy Zheng 2262c796fc8SIcenowy Zheng display_clocks: clock@0 { 2272c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 2282c796fc8SIcenowy Zheng reg = <0x0 0x100000>; 2292c796fc8SIcenowy Zheng clocks = <&ccu CLK_DE>, 2302c796fc8SIcenowy Zheng <&ccu CLK_BUS_DE>; 2312c796fc8SIcenowy Zheng clock-names = "mod", 2322c796fc8SIcenowy Zheng "bus"; 2332c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 2342c796fc8SIcenowy Zheng #clock-cells = <1>; 2352c796fc8SIcenowy Zheng #reset-cells = <1>; 2362c796fc8SIcenowy Zheng }; 237e85f28e0SJagan Teki 238e85f28e0SJagan Teki mixer0: mixer@100000 { 239e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 240e85f28e0SJagan Teki reg = <0x100000 0x100000>; 241e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 242e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 243e85f28e0SJagan Teki clock-names = "bus", 244e85f28e0SJagan Teki "mod"; 245e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 246e85f28e0SJagan Teki 247e85f28e0SJagan Teki ports { 248e85f28e0SJagan Teki #address-cells = <1>; 249e85f28e0SJagan Teki #size-cells = <0>; 250e85f28e0SJagan Teki 251e85f28e0SJagan Teki mixer0_out: port@1 { 252e85f28e0SJagan Teki reg = <1>; 253e85f28e0SJagan Teki 254e85f28e0SJagan Teki mixer0_out_tcon0: endpoint { 255e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 256e85f28e0SJagan Teki }; 257e85f28e0SJagan Teki }; 258e85f28e0SJagan Teki }; 259e85f28e0SJagan Teki }; 260e85f28e0SJagan Teki 261e85f28e0SJagan Teki mixer1: mixer@200000 { 262e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 263e85f28e0SJagan Teki reg = <0x200000 0x100000>; 264e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 265e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 266e85f28e0SJagan Teki clock-names = "bus", 267e85f28e0SJagan Teki "mod"; 268e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 269e85f28e0SJagan Teki 270e85f28e0SJagan Teki ports { 271e85f28e0SJagan Teki #address-cells = <1>; 272e85f28e0SJagan Teki #size-cells = <0>; 273e85f28e0SJagan Teki 274e85f28e0SJagan Teki mixer1_out: port@1 { 275e85f28e0SJagan Teki reg = <1>; 276e85f28e0SJagan Teki 277e85f28e0SJagan Teki mixer1_out_tcon1: endpoint { 278e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 279e85f28e0SJagan Teki }; 280e85f28e0SJagan Teki }; 281e85f28e0SJagan Teki }; 282e85f28e0SJagan Teki }; 2832c796fc8SIcenowy Zheng }; 2842c796fc8SIcenowy Zheng 28579b95360SCorentin Labbe syscon: syscon@1c00000 { 2861f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 28779b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 2881f1f5183SIcenowy Zheng #address-cells = <1>; 2891f1f5183SIcenowy Zheng #size-cells = <1>; 2901f1f5183SIcenowy Zheng ranges; 2911f1f5183SIcenowy Zheng 2921f1f5183SIcenowy Zheng sram_c: sram@18000 { 2931f1f5183SIcenowy Zheng compatible = "mmio-sram"; 2941f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 2951f1f5183SIcenowy Zheng #address-cells = <1>; 2961f1f5183SIcenowy Zheng #size-cells = <1>; 2971f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 2981f1f5183SIcenowy Zheng 2991f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 3001f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 3011f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 3021f1f5183SIcenowy Zheng }; 3031f1f5183SIcenowy Zheng }; 304106deea8SPaul Kocialkowski 305106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 306106deea8SPaul Kocialkowski compatible = "mmio-sram"; 307106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 308106deea8SPaul Kocialkowski #address-cells = <1>; 309106deea8SPaul Kocialkowski #size-cells = <1>; 310106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 311106deea8SPaul Kocialkowski 312106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 313106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 314106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 315106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 316106deea8SPaul Kocialkowski }; 317106deea8SPaul Kocialkowski }; 31879b95360SCorentin Labbe }; 31979b95360SCorentin Labbe 320c32637e0SStefan Brüns dma: dma-controller@1c02000 { 321c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 322c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 323c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 324c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 325c32637e0SStefan Brüns dma-channels = <8>; 326c32637e0SStefan Brüns dma-requests = <27>; 327c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 328c32637e0SStefan Brüns #dma-cells = <1>; 329c32637e0SStefan Brüns }; 330c32637e0SStefan Brüns 331e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 332e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 333e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 334e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 335e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 336e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 337e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 338e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 339e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 340e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 341e85f28e0SJagan Teki 342e85f28e0SJagan Teki ports { 343e85f28e0SJagan Teki #address-cells = <1>; 344e85f28e0SJagan Teki #size-cells = <0>; 345e85f28e0SJagan Teki 346e85f28e0SJagan Teki tcon0_in: port@0 { 347e85f28e0SJagan Teki #address-cells = <1>; 348e85f28e0SJagan Teki #size-cells = <0>; 349e85f28e0SJagan Teki reg = <0>; 350e85f28e0SJagan Teki 351e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 352e85f28e0SJagan Teki reg = <0>; 353e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 354e85f28e0SJagan Teki }; 355e85f28e0SJagan Teki }; 356e85f28e0SJagan Teki 357e85f28e0SJagan Teki tcon0_out: port@1 { 358e85f28e0SJagan Teki #address-cells = <1>; 359e85f28e0SJagan Teki #size-cells = <0>; 360e85f28e0SJagan Teki reg = <1>; 361e85f28e0SJagan Teki }; 362e85f28e0SJagan Teki }; 363e85f28e0SJagan Teki }; 364e85f28e0SJagan Teki 365e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 366e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 367e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 368e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 369e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 370e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 371e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 372e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 373e85f28e0SJagan Teki reset-names = "lcd"; 374e85f28e0SJagan Teki 375e85f28e0SJagan Teki ports { 376e85f28e0SJagan Teki #address-cells = <1>; 377e85f28e0SJagan Teki #size-cells = <0>; 378e85f28e0SJagan Teki 379e85f28e0SJagan Teki tcon1_in: port@0 { 380e85f28e0SJagan Teki reg = <0>; 381e85f28e0SJagan Teki 382e85f28e0SJagan Teki tcon1_in_mixer1: endpoint { 383e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 384e85f28e0SJagan Teki }; 385e85f28e0SJagan Teki }; 386e85f28e0SJagan Teki 387e85f28e0SJagan Teki tcon1_out: port@1 { 388e85f28e0SJagan Teki #address-cells = <1>; 389e85f28e0SJagan Teki #size-cells = <0>; 390e85f28e0SJagan Teki reg = <1>; 391e85f28e0SJagan Teki 392e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 393e85f28e0SJagan Teki reg = <1>; 394e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 395e85f28e0SJagan Teki }; 396e85f28e0SJagan Teki }; 397e85f28e0SJagan Teki }; 398e85f28e0SJagan Teki }; 399e85f28e0SJagan Teki 400f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 401f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 402f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 403f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 404f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 405f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 406f3dff347SAndre Przywara reset-names = "ahb"; 407f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 40822be992fSMaxime Ripard max-frequency = <150000000>; 409f3dff347SAndre Przywara status = "disabled"; 410f3dff347SAndre Przywara #address-cells = <1>; 411f3dff347SAndre Przywara #size-cells = <0>; 412f3dff347SAndre Przywara }; 413f3dff347SAndre Przywara 414f3dff347SAndre Przywara mmc1: mmc@1c10000 { 415f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 416f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 417f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 418f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 419f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 420f3dff347SAndre Przywara reset-names = "ahb"; 421f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 42222be992fSMaxime Ripard max-frequency = <150000000>; 423f3dff347SAndre Przywara status = "disabled"; 424f3dff347SAndre Przywara #address-cells = <1>; 425f3dff347SAndre Przywara #size-cells = <0>; 426f3dff347SAndre Przywara }; 427f3dff347SAndre Przywara 428f3dff347SAndre Przywara mmc2: mmc@1c11000 { 429f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 430f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 431f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 432f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 433f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 434f3dff347SAndre Przywara reset-names = "ahb"; 435f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 43622be992fSMaxime Ripard max-frequency = <200000000>; 437f3dff347SAndre Przywara status = "disabled"; 438f3dff347SAndre Przywara #address-cells = <1>; 439f3dff347SAndre Przywara #size-cells = <0>; 440f3dff347SAndre Przywara }; 441f3dff347SAndre Przywara 442ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 443ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 444ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 445ac947b17SEmmanuel Vadot }; 446ac947b17SEmmanuel Vadot 447d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 448972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 449972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 450972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 451972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 452972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 453972a3ecdSIcenowy Zheng interrupt-names = "mc"; 454972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 455972a3ecdSIcenowy Zheng phy-names = "usb"; 456972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 457972a3ecdSIcenowy Zheng status = "disabled"; 458972a3ecdSIcenowy Zheng }; 459972a3ecdSIcenowy Zheng 460d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 461a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 462a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 4630d984797SIcenowy Zheng <0x01c1a800 0x4>, 464a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 465a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 4660d984797SIcenowy Zheng "pmu0", 467a004ee35SIcenowy Zheng "pmu1"; 468a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 469a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 470a004ee35SIcenowy Zheng clock-names = "usb0_phy", 471a004ee35SIcenowy Zheng "usb1_phy"; 472a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 473a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 474a004ee35SIcenowy Zheng reset-names = "usb0_reset", 475a004ee35SIcenowy Zheng "usb1_reset"; 476a004ee35SIcenowy Zheng status = "disabled"; 477a004ee35SIcenowy Zheng #phy-cells = <1>; 478a004ee35SIcenowy Zheng }; 479a004ee35SIcenowy Zheng 480d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 481dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 482dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 483dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 484dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 485dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 486dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 487dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 488dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 489dc03a047SIcenowy Zheng status = "disabled"; 490dc03a047SIcenowy Zheng }; 491dc03a047SIcenowy Zheng 492d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 493dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 494dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 495dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 496dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 497dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 498dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 499dc03a047SIcenowy Zheng status = "disabled"; 500dc03a047SIcenowy Zheng }; 501dc03a047SIcenowy Zheng 502d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 503a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 504a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 505a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 506a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 507a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 508a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 509a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 510a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 511a004ee35SIcenowy Zheng phys = <&usbphy 1>; 512a004ee35SIcenowy Zheng phy-names = "usb"; 513a004ee35SIcenowy Zheng status = "disabled"; 514a004ee35SIcenowy Zheng }; 515a004ee35SIcenowy Zheng 516d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 517a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 518a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 519a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 520a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 521a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 522a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 523a004ee35SIcenowy Zheng phys = <&usbphy 1>; 524a004ee35SIcenowy Zheng phy-names = "usb"; 525a004ee35SIcenowy Zheng status = "disabled"; 526a004ee35SIcenowy Zheng }; 527a004ee35SIcenowy Zheng 528d6c9da12SCorentin LABBE ccu: clock@1c20000 { 5296bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 5306bc37facSAndre Przywara reg = <0x01c20000 0x400>; 5316bc37facSAndre Przywara clocks = <&osc24M>, <&osc32k>; 5326bc37facSAndre Przywara clock-names = "hosc", "losc"; 5336bc37facSAndre Przywara #clock-cells = <1>; 5346bc37facSAndre Przywara #reset-cells = <1>; 5356bc37facSAndre Przywara }; 5366bc37facSAndre Przywara 5376bc37facSAndre Przywara pio: pinctrl@1c20800 { 5386bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 5396bc37facSAndre Przywara reg = <0x01c20800 0x400>; 5406bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 5416bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 5426bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 543f98121f3SArnd Bergmann clocks = <&ccu 58>; 5446bc37facSAndre Przywara gpio-controller; 5456bc37facSAndre Przywara #gpio-cells = <3>; 5466bc37facSAndre Przywara interrupt-controller; 5476bc37facSAndre Przywara #interrupt-cells = <3>; 5486bc37facSAndre Przywara 54911239fe6SHarald Geyer i2c0_pins: i2c0_pins { 55011239fe6SHarald Geyer pins = "PH0", "PH1"; 55111239fe6SHarald Geyer function = "i2c0"; 55211239fe6SHarald Geyer }; 55311239fe6SHarald Geyer 5546bc37facSAndre Przywara i2c1_pins: i2c1_pins { 5556bc37facSAndre Przywara pins = "PH2", "PH3"; 5566bc37facSAndre Przywara function = "i2c1"; 5576bc37facSAndre Przywara }; 5586bc37facSAndre Przywara 559a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 560a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 561a3e8f492SMaxime Ripard "PF4", "PF5"; 562a3e8f492SMaxime Ripard function = "mmc0"; 563a3e8f492SMaxime Ripard drive-strength = <30>; 564a3e8f492SMaxime Ripard bias-pull-up; 565a3e8f492SMaxime Ripard }; 566a3e8f492SMaxime Ripard 567a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 568a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 569a3e8f492SMaxime Ripard "PG4", "PG5"; 570a3e8f492SMaxime Ripard function = "mmc1"; 571a3e8f492SMaxime Ripard drive-strength = <30>; 572a3e8f492SMaxime Ripard bias-pull-up; 573a3e8f492SMaxime Ripard }; 574a3e8f492SMaxime Ripard 575a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 576fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 577a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 578a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 579a3e8f492SMaxime Ripard function = "mmc2"; 580a3e8f492SMaxime Ripard drive-strength = <30>; 581a3e8f492SMaxime Ripard bias-pull-up; 582a3e8f492SMaxime Ripard }; 583a3e8f492SMaxime Ripard 584fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 585fa59dd2eSChen-Yu Tsai pins = "PC1"; 586fa59dd2eSChen-Yu Tsai function = "mmc2"; 587fa59dd2eSChen-Yu Tsai drive-strength = <30>; 588fa59dd2eSChen-Yu Tsai bias-pull-up; 589fa59dd2eSChen-Yu Tsai }; 590fa59dd2eSChen-Yu Tsai 591b5df280bSAndre Przywara pwm_pin: pwm_pin { 592b5df280bSAndre Przywara pins = "PD22"; 593b5df280bSAndre Przywara function = "pwm"; 594b5df280bSAndre Przywara }; 595b5df280bSAndre Przywara 596e53f67e9SCorentin Labbe rmii_pins: rmii_pins { 597e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 598e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 599e53f67e9SCorentin Labbe function = "emac"; 600e53f67e9SCorentin Labbe drive-strength = <40>; 601e53f67e9SCorentin Labbe }; 602e53f67e9SCorentin Labbe 603e53f67e9SCorentin Labbe rgmii_pins: rgmii_pins { 604e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 605e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 606e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 607e53f67e9SCorentin Labbe function = "emac"; 608e53f67e9SCorentin Labbe drive-strength = <40>; 609e53f67e9SCorentin Labbe }; 610e53f67e9SCorentin Labbe 611b399d2acSMarcus Cooper spdif_tx_pin: spdif { 612b399d2acSMarcus Cooper pins = "PH8"; 613b399d2acSMarcus Cooper function = "spdif"; 614b399d2acSMarcus Cooper }; 615b399d2acSMarcus Cooper 616b518bb15SStefan Brüns spi0_pins: spi0 { 617b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 618b518bb15SStefan Brüns function = "spi0"; 619b518bb15SStefan Brüns }; 620b518bb15SStefan Brüns 621b518bb15SStefan Brüns spi1_pins: spi1 { 622b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 623b518bb15SStefan Brüns function = "spi1"; 624b518bb15SStefan Brüns }; 625b518bb15SStefan Brüns 626d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 6276bc37facSAndre Przywara pins = "PB8", "PB9"; 6286bc37facSAndre Przywara function = "uart0"; 6296bc37facSAndre Przywara }; 630e7ba733dSAndre Przywara 631e7ba733dSAndre Przywara uart1_pins: uart1_pins { 632e7ba733dSAndre Przywara pins = "PG6", "PG7"; 633e7ba733dSAndre Przywara function = "uart1"; 634e7ba733dSAndre Przywara }; 635e7ba733dSAndre Przywara 636e7ba733dSAndre Przywara uart1_rts_cts_pins: uart1_rts_cts_pins { 637e7ba733dSAndre Przywara pins = "PG8", "PG9"; 638e7ba733dSAndre Przywara function = "uart1"; 639e7ba733dSAndre Przywara }; 64079825719SAndreas Färber 64179825719SAndreas Färber uart2_pins: uart2-pins { 64279825719SAndreas Färber pins = "PB0", "PB1"; 64379825719SAndreas Färber function = "uart2"; 64479825719SAndreas Färber }; 6452273aa16SAndreas Färber 6462273aa16SAndreas Färber uart3_pins: uart3-pins { 6472273aa16SAndreas Färber pins = "PD0", "PD1"; 6482273aa16SAndreas Färber function = "uart3"; 6492273aa16SAndreas Färber }; 6502273aa16SAndreas Färber 6512273aa16SAndreas Färber uart4_pins: uart4-pins { 6522273aa16SAndreas Färber pins = "PD2", "PD3"; 6532273aa16SAndreas Färber function = "uart4"; 6542273aa16SAndreas Färber }; 6552273aa16SAndreas Färber 6562273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 6572273aa16SAndreas Färber pins = "PD4", "PD5"; 6582273aa16SAndreas Färber function = "uart4"; 6592273aa16SAndreas Färber }; 6606bc37facSAndre Przywara }; 6616bc37facSAndre Przywara 662b399d2acSMarcus Cooper spdif: spdif@1c21000 { 663b399d2acSMarcus Cooper #sound-dai-cells = <0>; 664b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 665b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 666b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 667b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 668b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 669b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 670b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 671b399d2acSMarcus Cooper dmas = <&dma 2>; 672b399d2acSMarcus Cooper dma-names = "tx"; 673b399d2acSMarcus Cooper pinctrl-names = "default"; 674b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 675b399d2acSMarcus Cooper status = "disabled"; 676b399d2acSMarcus Cooper }; 677b399d2acSMarcus Cooper 6781c92c009SMarcus Cooper i2s0: i2s@1c22000 { 6791c92c009SMarcus Cooper #sound-dai-cells = <0>; 6801c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 6811c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 6821c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 6831c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6841c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 6851c92c009SMarcus Cooper clock-names = "apb", "mod"; 6861c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 6871c92c009SMarcus Cooper dma-names = "rx", "tx"; 6881c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 6891c92c009SMarcus Cooper status = "disabled"; 6901c92c009SMarcus Cooper }; 6911c92c009SMarcus Cooper 6921c92c009SMarcus Cooper i2s1: i2s@1c22400 { 6931c92c009SMarcus Cooper #sound-dai-cells = <0>; 6941c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 6951c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 6961c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 6971c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6981c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 6991c92c009SMarcus Cooper clock-names = "apb", "mod"; 7001c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 7011c92c009SMarcus Cooper dma-names = "rx", "tx"; 7021c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 7031c92c009SMarcus Cooper status = "disabled"; 7041c92c009SMarcus Cooper }; 7051c92c009SMarcus Cooper 706ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 707ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 708ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 709ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 710ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 711ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 712ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 713ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 714ec4a9540SVasily Khoruzhick reset-names = "rst"; 715ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 716ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 717ec4a9540SVasily Khoruzhick status = "disabled"; 718ec4a9540SVasily Khoruzhick }; 719ec4a9540SVasily Khoruzhick 720ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 721ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 722ec4a9540SVasily Khoruzhick compatible = "allwinner,sun8i-a33-codec"; 723ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 724ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 725ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 726ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 727ec4a9540SVasily Khoruzhick status = "disabled"; 728ec4a9540SVasily Khoruzhick }; 729ec4a9540SVasily Khoruzhick 7306bc37facSAndre Przywara uart0: serial@1c28000 { 7316bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7326bc37facSAndre Przywara reg = <0x01c28000 0x400>; 7336bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 7346bc37facSAndre Przywara reg-shift = <2>; 7356bc37facSAndre Przywara reg-io-width = <4>; 736494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 737494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 7386bc37facSAndre Przywara status = "disabled"; 7396bc37facSAndre Przywara }; 7406bc37facSAndre Przywara 7416bc37facSAndre Przywara uart1: serial@1c28400 { 7426bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7436bc37facSAndre Przywara reg = <0x01c28400 0x400>; 7446bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 7456bc37facSAndre Przywara reg-shift = <2>; 7466bc37facSAndre Przywara reg-io-width = <4>; 747494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 748494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 7496bc37facSAndre Przywara status = "disabled"; 7506bc37facSAndre Przywara }; 7516bc37facSAndre Przywara 7526bc37facSAndre Przywara uart2: serial@1c28800 { 7536bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7546bc37facSAndre Przywara reg = <0x01c28800 0x400>; 7556bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 7566bc37facSAndre Przywara reg-shift = <2>; 7576bc37facSAndre Przywara reg-io-width = <4>; 758494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 759494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 7606bc37facSAndre Przywara status = "disabled"; 7616bc37facSAndre Przywara }; 7626bc37facSAndre Przywara 7636bc37facSAndre Przywara uart3: serial@1c28c00 { 7646bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7656bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 7666bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 7676bc37facSAndre Przywara reg-shift = <2>; 7686bc37facSAndre Przywara reg-io-width = <4>; 769494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 770494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 7716bc37facSAndre Przywara status = "disabled"; 7726bc37facSAndre Przywara }; 7736bc37facSAndre Przywara 7746bc37facSAndre Przywara uart4: serial@1c29000 { 7756bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 7766bc37facSAndre Przywara reg = <0x01c29000 0x400>; 7776bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 7786bc37facSAndre Przywara reg-shift = <2>; 7796bc37facSAndre Przywara reg-io-width = <4>; 780494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 781494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 7826bc37facSAndre Przywara status = "disabled"; 7836bc37facSAndre Przywara }; 7846bc37facSAndre Przywara 7856bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 7866bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 7876bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 7886bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 789494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 790494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 7916bc37facSAndre Przywara status = "disabled"; 7926bc37facSAndre Przywara #address-cells = <1>; 7936bc37facSAndre Przywara #size-cells = <0>; 7946bc37facSAndre Przywara }; 7956bc37facSAndre Przywara 7966bc37facSAndre Przywara i2c1: i2c@1c2b000 { 7976bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 7986bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 7996bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 800494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 801494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 8026bc37facSAndre Przywara status = "disabled"; 8036bc37facSAndre Przywara #address-cells = <1>; 8046bc37facSAndre Przywara #size-cells = <0>; 8056bc37facSAndre Przywara }; 8066bc37facSAndre Przywara 8076bc37facSAndre Przywara i2c2: i2c@1c2b400 { 8086bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 8096bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 8106bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 811494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 812494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 8136bc37facSAndre Przywara status = "disabled"; 8146bc37facSAndre Przywara #address-cells = <1>; 8156bc37facSAndre Przywara #size-cells = <0>; 8166bc37facSAndre Przywara }; 8176bc37facSAndre Przywara 818b518bb15SStefan Brüns 819d6c9da12SCorentin LABBE spi0: spi@1c68000 { 820b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 821b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 822b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 823b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 824b518bb15SStefan Brüns clock-names = "ahb", "mod"; 82506c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 82606c1258aSStefan Brüns dma-names = "rx", "tx"; 827b518bb15SStefan Brüns pinctrl-names = "default"; 828b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 829b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 830b518bb15SStefan Brüns status = "disabled"; 831b518bb15SStefan Brüns num-cs = <1>; 832b518bb15SStefan Brüns #address-cells = <1>; 833b518bb15SStefan Brüns #size-cells = <0>; 834b518bb15SStefan Brüns }; 835b518bb15SStefan Brüns 836d6c9da12SCorentin LABBE spi1: spi@1c69000 { 837b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 838b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 839b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 840b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 841b518bb15SStefan Brüns clock-names = "ahb", "mod"; 84206c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 84306c1258aSStefan Brüns dma-names = "rx", "tx"; 844b518bb15SStefan Brüns pinctrl-names = "default"; 845b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 846b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 847b518bb15SStefan Brüns status = "disabled"; 848b518bb15SStefan Brüns num-cs = <1>; 849b518bb15SStefan Brüns #address-cells = <1>; 850b518bb15SStefan Brüns #size-cells = <0>; 851b518bb15SStefan Brüns }; 852b518bb15SStefan Brüns 85394f44288SCorentin Labbe emac: ethernet@1c30000 { 85494f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 85594f44288SCorentin Labbe syscon = <&syscon>; 85694f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 85794f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 85894f44288SCorentin Labbe interrupt-names = "macirq"; 85994f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 86094f44288SCorentin Labbe reset-names = "stmmaceth"; 86194f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 86294f44288SCorentin Labbe clock-names = "stmmaceth"; 86394f44288SCorentin Labbe status = "disabled"; 86494f44288SCorentin Labbe 86594f44288SCorentin Labbe mdio: mdio { 86616416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 86794f44288SCorentin Labbe #address-cells = <1>; 86894f44288SCorentin Labbe #size-cells = <0>; 86994f44288SCorentin Labbe }; 87094f44288SCorentin Labbe }; 87194f44288SCorentin Labbe 8726b683d76SJagan Teki mali: gpu@1c40000 { 8736b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 8746b683d76SJagan Teki reg = <0x01c40000 0x10000>; 8756b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 8766b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 8776b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 8786b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 8796b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 8806b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 8816b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 8826b683d76SJagan Teki interrupt-names = "gp", 8836b683d76SJagan Teki "gpmmu", 8846b683d76SJagan Teki "pp0", 8856b683d76SJagan Teki "ppmmu0", 8866b683d76SJagan Teki "pp1", 8876b683d76SJagan Teki "ppmmu1", 8886b683d76SJagan Teki "pmu"; 8896b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 8906b683d76SJagan Teki clock-names = "bus", "core"; 8916b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 8926b683d76SJagan Teki }; 8936b683d76SJagan Teki 8946bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 8956bc37facSAndre Przywara compatible = "arm,gic-400"; 8966bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 8976bc37facSAndre Przywara <0x01c82000 0x2000>, 8986bc37facSAndre Przywara <0x01c84000 0x2000>, 8996bc37facSAndre Przywara <0x01c86000 0x2000>; 9006bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 9016bc37facSAndre Przywara interrupt-controller; 9026bc37facSAndre Przywara #interrupt-cells = <3>; 9036bc37facSAndre Przywara }; 9046bc37facSAndre Przywara 905b5df280bSAndre Przywara pwm: pwm@1c21400 { 906b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 907b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 908b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 909b5df280bSAndre Przywara clocks = <&osc24M>; 910b5df280bSAndre Przywara pinctrl-names = "default"; 911b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 912b5df280bSAndre Przywara #pwm-cells = <3>; 913b5df280bSAndre Przywara status = "disabled"; 914b5df280bSAndre Przywara }; 915b5df280bSAndre Przywara 916e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 917e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 918e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 919e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 920e85f28e0SJagan Teki reg-io-width = <1>; 921e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 922e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 923e85f28e0SJagan Teki <&ccu CLK_HDMI>; 924e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 925e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 926e85f28e0SJagan Teki reset-names = "ctrl"; 927e85f28e0SJagan Teki phys = <&hdmi_phy>; 928e85f28e0SJagan Teki phy-names = "hdmi-phy"; 929e85f28e0SJagan Teki status = "disabled"; 930e85f28e0SJagan Teki 931e85f28e0SJagan Teki ports { 932e85f28e0SJagan Teki #address-cells = <1>; 933e85f28e0SJagan Teki #size-cells = <0>; 934e85f28e0SJagan Teki 935e85f28e0SJagan Teki hdmi_in: port@0 { 936e85f28e0SJagan Teki reg = <0>; 937e85f28e0SJagan Teki 938e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 939e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 940e85f28e0SJagan Teki }; 941e85f28e0SJagan Teki }; 942e85f28e0SJagan Teki 943e85f28e0SJagan Teki hdmi_out: port@1 { 944e85f28e0SJagan Teki reg = <1>; 945e85f28e0SJagan Teki }; 946e85f28e0SJagan Teki }; 947e85f28e0SJagan Teki }; 948e85f28e0SJagan Teki 949e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 950e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 951e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 952e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 953e85f28e0SJagan Teki <&ccu 7>; 954e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 955e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 956e85f28e0SJagan Teki reset-names = "phy"; 957e85f28e0SJagan Teki #phy-cells = <0>; 958e85f28e0SJagan Teki }; 959e85f28e0SJagan Teki 9606bc37facSAndre Przywara rtc: rtc@1f00000 { 9616bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-rtc"; 9626bc37facSAndre Przywara reg = <0x01f00000 0x54>; 9636bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 9646bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 965e1a9a474SJagan Teki clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 966e1a9a474SJagan Teki clocks = <&osc32k>; 967e1a9a474SJagan Teki #clock-cells = <1>; 9686bc37facSAndre Przywara }; 969791a9e00SIcenowy Zheng 970535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 971535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 972535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 973535ca508SIcenowy Zheng interrupt-controller; 974535ca508SIcenowy Zheng #interrupt-cells = <2>; 975535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 976535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 977535ca508SIcenowy Zheng }; 978535ca508SIcenowy Zheng 979791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 980791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 981791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 982f74994a9SChen-Yu Tsai clocks = <&osc24M>, <&osc32k>, <&iosc>, 983f74994a9SChen-Yu Tsai <&ccu 11>; 984f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 985791a9e00SIcenowy Zheng #clock-cells = <1>; 986791a9e00SIcenowy Zheng #reset-cells = <1>; 987791a9e00SIcenowy Zheng }; 988ec427905SIcenowy Zheng 989ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 990ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 991ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 992ec4a9540SVasily Khoruzhick status = "disabled"; 993ec4a9540SVasily Khoruzhick }; 994ec4a9540SVasily Khoruzhick 995871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 996871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 997871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 998871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 999871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1000871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1001871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1002871b5352SIcenowy Zheng status = "disabled"; 1003871b5352SIcenowy Zheng #address-cells = <1>; 1004871b5352SIcenowy Zheng #size-cells = <0>; 1005871b5352SIcenowy Zheng }; 1006871b5352SIcenowy Zheng 1007b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1008b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1009b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1010b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1011b5df280bSAndre Przywara clocks = <&osc24M>; 1012b5df280bSAndre Przywara pinctrl-names = "default"; 1013b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1014b5df280bSAndre Przywara #pwm-cells = <3>; 1015b5df280bSAndre Przywara status = "disabled"; 1016b5df280bSAndre Przywara }; 1017b5df280bSAndre Przywara 1018d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1019ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1020ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1021ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1022494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1023ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1024ec427905SIcenowy Zheng gpio-controller; 1025ec427905SIcenowy Zheng #gpio-cells = <3>; 1026ec427905SIcenowy Zheng interrupt-controller; 1027ec427905SIcenowy Zheng #interrupt-cells = <3>; 10283b38fdedSIcenowy Zheng 10291b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1030871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1031871b5352SIcenowy Zheng function = "s_i2c"; 1032871b5352SIcenowy Zheng }; 1033871b5352SIcenowy Zheng 1034b5df280bSAndre Przywara r_pwm_pin: pwm { 1035b5df280bSAndre Przywara pins = "PL10"; 1036b5df280bSAndre Przywara function = "s_pwm"; 1037b5df280bSAndre Przywara }; 1038b5df280bSAndre Przywara 103992d378fbSCorentin LABBE r_rsb_pins: rsb { 10403b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 10413b38fdedSIcenowy Zheng function = "s_rsb"; 10423b38fdedSIcenowy Zheng }; 10433b38fdedSIcenowy Zheng }; 10443b38fdedSIcenowy Zheng 10453b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 10463b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 10473b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 10483b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 10493b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 10503b38fdedSIcenowy Zheng clock-frequency = <3000000>; 10513b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 10523b38fdedSIcenowy Zheng pinctrl-names = "default"; 10533b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 10543b38fdedSIcenowy Zheng status = "disabled"; 10553b38fdedSIcenowy Zheng #address-cells = <1>; 10563b38fdedSIcenowy Zheng #size-cells = <0>; 1057ec427905SIcenowy Zheng }; 1058d4185043SHarald Geyer 1059d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 1060d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 1061d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 1062d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 1063d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1064d4185043SHarald Geyer }; 10656bc37facSAndre Przywara }; 10666bc37facSAndre Przywara}; 1067