1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2cabbaed7SClément Péron// Copyright (C) 2016 ARM Ltd. 3cabbaed7SClément Péron// based on the Allwinner H3 dtsi: 4cabbaed7SClément Péron// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 56bc37facSAndre Przywara 6a004ee35SIcenowy Zheng#include <dt-bindings/clock/sun50i-a64-ccu.h> 72c796fc8SIcenowy Zheng#include <dt-bindings/clock/sun8i-de2.h> 8494d8a2cSChen-Yu Tsai#include <dt-bindings/clock/sun8i-r-ccu.h> 96bc37facSAndre Przywara#include <dt-bindings/interrupt-controller/arm-gic.h> 10a004ee35SIcenowy Zheng#include <dt-bindings/reset/sun50i-a64-ccu.h> 112c796fc8SIcenowy Zheng#include <dt-bindings/reset/sun8i-de2.h> 12871b5352SIcenowy Zheng#include <dt-bindings/reset/sun8i-r-ccu.h> 1359f5e9b9SVasily Khoruzhick#include <dt-bindings/thermal/thermal.h> 146bc37facSAndre Przywara 156bc37facSAndre Przywara/ { 166bc37facSAndre Przywara interrupt-parent = <&gic>; 176bc37facSAndre Przywara #address-cells = <1>; 186bc37facSAndre Przywara #size-cells = <1>; 196bc37facSAndre Przywara 20c1cff65fSHarald Geyer chosen { 21c1cff65fSHarald Geyer #address-cells = <1>; 22c1cff65fSHarald Geyer #size-cells = <1>; 23c1cff65fSHarald Geyer ranges; 24c1cff65fSHarald Geyer 25c1cff65fSHarald Geyer simplefb_lcd: framebuffer-lcd { 26c1cff65fSHarald Geyer compatible = "allwinner,simple-framebuffer", 27c1cff65fSHarald Geyer "simple-framebuffer"; 28c1cff65fSHarald Geyer allwinner,pipeline = "mixer0-lcd0"; 29c1cff65fSHarald Geyer clocks = <&ccu CLK_TCON0>, 302c796fc8SIcenowy Zheng <&display_clocks CLK_MIXER0>; 31c1cff65fSHarald Geyer status = "disabled"; 32c1cff65fSHarald Geyer }; 33fca63f58SIcenowy Zheng 34fca63f58SIcenowy Zheng simplefb_hdmi: framebuffer-hdmi { 35fca63f58SIcenowy Zheng compatible = "allwinner,simple-framebuffer", 36fca63f58SIcenowy Zheng "simple-framebuffer"; 37fca63f58SIcenowy Zheng allwinner,pipeline = "mixer1-lcd1-hdmi"; 38fca63f58SIcenowy Zheng clocks = <&display_clocks CLK_MIXER1>, 39fca63f58SIcenowy Zheng <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 40fca63f58SIcenowy Zheng status = "disabled"; 41fca63f58SIcenowy Zheng }; 42c1cff65fSHarald Geyer }; 43c1cff65fSHarald Geyer 446bc37facSAndre Przywara cpus { 456bc37facSAndre Przywara #address-cells = <1>; 466bc37facSAndre Przywara #size-cells = <0>; 476bc37facSAndre Przywara 486bc37facSAndre Przywara cpu0: cpu@0 { 4931af04cdSRob Herring compatible = "arm,cortex-a53"; 506bc37facSAndre Przywara device_type = "cpu"; 516bc37facSAndre Przywara reg = <0>; 526bc37facSAndre Przywara enable-method = "psci"; 5339defc81SAndre Przywara next-level-cache = <&L2>; 54f267eff7SVasily Khoruzhick clocks = <&ccu 21>; 55f267eff7SVasily Khoruzhick clock-names = "cpu"; 56e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 576bc37facSAndre Przywara }; 586bc37facSAndre Przywara 596bc37facSAndre Przywara cpu1: cpu@1 { 6031af04cdSRob Herring compatible = "arm,cortex-a53"; 616bc37facSAndre Przywara device_type = "cpu"; 626bc37facSAndre Przywara reg = <1>; 636bc37facSAndre Przywara enable-method = "psci"; 6439defc81SAndre Przywara next-level-cache = <&L2>; 65f267eff7SVasily Khoruzhick clocks = <&ccu 21>; 66f267eff7SVasily Khoruzhick clock-names = "cpu"; 67e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 686bc37facSAndre Przywara }; 696bc37facSAndre Przywara 706bc37facSAndre Przywara cpu2: cpu@2 { 7131af04cdSRob Herring compatible = "arm,cortex-a53"; 726bc37facSAndre Przywara device_type = "cpu"; 736bc37facSAndre Przywara reg = <2>; 746bc37facSAndre Przywara enable-method = "psci"; 7539defc81SAndre Przywara next-level-cache = <&L2>; 76f267eff7SVasily Khoruzhick clocks = <&ccu 21>; 77f267eff7SVasily Khoruzhick clock-names = "cpu"; 78e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 796bc37facSAndre Przywara }; 806bc37facSAndre Przywara 816bc37facSAndre Przywara cpu3: cpu@3 { 8231af04cdSRob Herring compatible = "arm,cortex-a53"; 836bc37facSAndre Przywara device_type = "cpu"; 846bc37facSAndre Przywara reg = <3>; 856bc37facSAndre Przywara enable-method = "psci"; 8639defc81SAndre Przywara next-level-cache = <&L2>; 87f267eff7SVasily Khoruzhick clocks = <&ccu 21>; 88f267eff7SVasily Khoruzhick clock-names = "cpu"; 89e1c3804aSVasily Khoruzhick #cooling-cells = <2>; 9039defc81SAndre Przywara }; 9139defc81SAndre Przywara 9239defc81SAndre Przywara L2: l2-cache { 9339defc81SAndre Przywara compatible = "cache"; 9439defc81SAndre Przywara cache-level = <2>; 956bc37facSAndre Przywara }; 966bc37facSAndre Przywara }; 976bc37facSAndre Przywara 98e85f28e0SJagan Teki de: display-engine { 99e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-display-engine"; 100e85f28e0SJagan Teki allwinner,pipelines = <&mixer0>, 101e85f28e0SJagan Teki <&mixer1>; 102e85f28e0SJagan Teki status = "disabled"; 103e85f28e0SJagan Teki }; 104e85f28e0SJagan Teki 1056bc37facSAndre Przywara osc24M: osc24M_clk { 1066bc37facSAndre Przywara #clock-cells = <0>; 1076bc37facSAndre Przywara compatible = "fixed-clock"; 1086bc37facSAndre Przywara clock-frequency = <24000000>; 1096bc37facSAndre Przywara clock-output-names = "osc24M"; 1106bc37facSAndre Przywara }; 1116bc37facSAndre Przywara 1126bc37facSAndre Przywara osc32k: osc32k_clk { 1136bc37facSAndre Przywara #clock-cells = <0>; 1146bc37facSAndre Przywara compatible = "fixed-clock"; 1156bc37facSAndre Przywara clock-frequency = <32768>; 11644ff3cafSChen-Yu Tsai clock-output-names = "ext-osc32k"; 117791a9e00SIcenowy Zheng }; 118791a9e00SIcenowy Zheng 11934a97fccSHarald Geyer pmu { 12034a97fccSHarald Geyer compatible = "arm,cortex-a53-pmu"; 1216b832a14SAndre Przywara interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1226b832a14SAndre Przywara <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1236b832a14SAndre Przywara <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1246b832a14SAndre Przywara <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 12534a97fccSHarald Geyer interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 12634a97fccSHarald Geyer }; 12734a97fccSHarald Geyer 1286bc37facSAndre Przywara psci { 1296bc37facSAndre Przywara compatible = "arm,psci-0.2"; 1306bc37facSAndre Przywara method = "smc"; 1316bc37facSAndre Przywara }; 1326bc37facSAndre Przywara 133ec4a9540SVasily Khoruzhick sound: sound { 134ec4a9540SVasily Khoruzhick compatible = "simple-audio-card"; 135ec4a9540SVasily Khoruzhick simple-audio-card,name = "sun50i-a64-audio"; 136ec4a9540SVasily Khoruzhick simple-audio-card,format = "i2s"; 137ec4a9540SVasily Khoruzhick simple-audio-card,frame-master = <&cpudai>; 138ec4a9540SVasily Khoruzhick simple-audio-card,bitclock-master = <&cpudai>; 139ec4a9540SVasily Khoruzhick simple-audio-card,mclk-fs = <128>; 140ec4a9540SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 141ec4a9540SVasily Khoruzhick simple-audio-card,routing = 142ec4a9540SVasily Khoruzhick "Left DAC", "AIF1 Slot 0 Left", 143ec4a9540SVasily Khoruzhick "Right DAC", "AIF1 Slot 0 Right", 144ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Left ADC", "Left ADC", 145ec4a9540SVasily Khoruzhick "AIF1 Slot 0 Right ADC", "Right ADC"; 146ec4a9540SVasily Khoruzhick status = "disabled"; 147ec4a9540SVasily Khoruzhick 148ec4a9540SVasily Khoruzhick cpudai: simple-audio-card,cpu { 149ec4a9540SVasily Khoruzhick sound-dai = <&dai>; 150ec4a9540SVasily Khoruzhick }; 151ec4a9540SVasily Khoruzhick 152ec4a9540SVasily Khoruzhick link_codec: simple-audio-card,codec { 153ec4a9540SVasily Khoruzhick sound-dai = <&codec>; 154ec4a9540SVasily Khoruzhick }; 155ec4a9540SVasily Khoruzhick }; 156ec4a9540SVasily Khoruzhick 15778e07137SMarcus Cooper sound_spdif { 15878e07137SMarcus Cooper compatible = "simple-audio-card"; 15978e07137SMarcus Cooper simple-audio-card,name = "On-board SPDIF"; 16078e07137SMarcus Cooper 16178e07137SMarcus Cooper simple-audio-card,cpu { 16278e07137SMarcus Cooper sound-dai = <&spdif>; 16378e07137SMarcus Cooper }; 16478e07137SMarcus Cooper 16578e07137SMarcus Cooper simple-audio-card,codec { 16678e07137SMarcus Cooper sound-dai = <&spdif_out>; 16778e07137SMarcus Cooper }; 16878e07137SMarcus Cooper }; 16978e07137SMarcus Cooper 17078e07137SMarcus Cooper spdif_out: spdif-out { 17178e07137SMarcus Cooper #sound-dai-cells = <0>; 17278e07137SMarcus Cooper compatible = "linux,spdif-dit"; 17378e07137SMarcus Cooper }; 17478e07137SMarcus Cooper 1756bc37facSAndre Przywara timer { 1766bc37facSAndre Przywara compatible = "arm,armv8-timer"; 17755ec26d6SSamuel Holland allwinner,erratum-unknown1; 1786bc37facSAndre Przywara interrupts = <GIC_PPI 13 1796bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1806bc37facSAndre Przywara <GIC_PPI 14 1816bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1826bc37facSAndre Przywara <GIC_PPI 11 1836bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1846bc37facSAndre Przywara <GIC_PPI 10 1856bc37facSAndre Przywara (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1866bc37facSAndre Przywara }; 1876bc37facSAndre Przywara 18859f5e9b9SVasily Khoruzhick thermal-zones { 18959f5e9b9SVasily Khoruzhick cpu_thermal: cpu0-thermal { 19059f5e9b9SVasily Khoruzhick /* milliseconds */ 19159f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 19259f5e9b9SVasily Khoruzhick polling-delay = <0>; 19359f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 0>; 194e1c3804aSVasily Khoruzhick 195e1c3804aSVasily Khoruzhick cooling-maps { 196e1c3804aSVasily Khoruzhick map0 { 197e1c3804aSVasily Khoruzhick trip = <&cpu_alert0>; 198e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 199e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 200e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 201e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 202e1c3804aSVasily Khoruzhick }; 203e1c3804aSVasily Khoruzhick map1 { 204e1c3804aSVasily Khoruzhick trip = <&cpu_alert1>; 205e1c3804aSVasily Khoruzhick cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206e1c3804aSVasily Khoruzhick <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207e1c3804aSVasily Khoruzhick <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208e1c3804aSVasily Khoruzhick <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209e1c3804aSVasily Khoruzhick }; 210e1c3804aSVasily Khoruzhick }; 211e1c3804aSVasily Khoruzhick 212e1c3804aSVasily Khoruzhick trips { 213e1c3804aSVasily Khoruzhick cpu_alert0: cpu_alert0 { 214e1c3804aSVasily Khoruzhick /* milliCelsius */ 215e1c3804aSVasily Khoruzhick temperature = <75000>; 216e1c3804aSVasily Khoruzhick hysteresis = <2000>; 217e1c3804aSVasily Khoruzhick type = "passive"; 218e1c3804aSVasily Khoruzhick }; 219e1c3804aSVasily Khoruzhick 220e1c3804aSVasily Khoruzhick cpu_alert1: cpu_alert1 { 221e1c3804aSVasily Khoruzhick /* milliCelsius */ 222e1c3804aSVasily Khoruzhick temperature = <90000>; 223e1c3804aSVasily Khoruzhick hysteresis = <2000>; 224e1c3804aSVasily Khoruzhick type = "hot"; 225e1c3804aSVasily Khoruzhick }; 226e1c3804aSVasily Khoruzhick 227e1c3804aSVasily Khoruzhick cpu_crit: cpu_crit { 228e1c3804aSVasily Khoruzhick /* milliCelsius */ 229e1c3804aSVasily Khoruzhick temperature = <110000>; 230e1c3804aSVasily Khoruzhick hysteresis = <2000>; 231e1c3804aSVasily Khoruzhick type = "critical"; 232e1c3804aSVasily Khoruzhick }; 233e1c3804aSVasily Khoruzhick }; 23459f5e9b9SVasily Khoruzhick }; 23559f5e9b9SVasily Khoruzhick 23659f5e9b9SVasily Khoruzhick gpu0_thermal: gpu0-thermal { 23759f5e9b9SVasily Khoruzhick /* milliseconds */ 23859f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 23959f5e9b9SVasily Khoruzhick polling-delay = <0>; 24059f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 1>; 24159f5e9b9SVasily Khoruzhick }; 24259f5e9b9SVasily Khoruzhick 24359f5e9b9SVasily Khoruzhick gpu1_thermal: gpu1-thermal { 24459f5e9b9SVasily Khoruzhick /* milliseconds */ 24559f5e9b9SVasily Khoruzhick polling-delay-passive = <0>; 24659f5e9b9SVasily Khoruzhick polling-delay = <0>; 24759f5e9b9SVasily Khoruzhick thermal-sensors = <&ths 2>; 24859f5e9b9SVasily Khoruzhick }; 24959f5e9b9SVasily Khoruzhick }; 25059f5e9b9SVasily Khoruzhick 2516bc37facSAndre Przywara soc { 2526bc37facSAndre Przywara compatible = "simple-bus"; 2536bc37facSAndre Przywara #address-cells = <1>; 2546bc37facSAndre Przywara #size-cells = <1>; 2556bc37facSAndre Przywara ranges; 2566bc37facSAndre Przywara 257275b6317SMaxime Ripard bus@1000000 { 2582c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2"; 2592c796fc8SIcenowy Zheng reg = <0x1000000 0x400000>; 2602c796fc8SIcenowy Zheng allwinner,sram = <&de2_sram 1>; 2612c796fc8SIcenowy Zheng #address-cells = <1>; 2622c796fc8SIcenowy Zheng #size-cells = <1>; 2632c796fc8SIcenowy Zheng ranges = <0 0x1000000 0x400000>; 2642c796fc8SIcenowy Zheng 2652c796fc8SIcenowy Zheng display_clocks: clock@0 { 2662c796fc8SIcenowy Zheng compatible = "allwinner,sun50i-a64-de2-clk"; 2673e9a1a8bSJernej Skrabec reg = <0x0 0x10000>; 2685ea40f71SMaxime Ripard clocks = <&ccu CLK_BUS_DE>, 2695ea40f71SMaxime Ripard <&ccu CLK_DE>; 2705ea40f71SMaxime Ripard clock-names = "bus", 2715ea40f71SMaxime Ripard "mod"; 2722c796fc8SIcenowy Zheng resets = <&ccu RST_BUS_DE>; 2732c796fc8SIcenowy Zheng #clock-cells = <1>; 2742c796fc8SIcenowy Zheng #reset-cells = <1>; 2752c796fc8SIcenowy Zheng }; 276e85f28e0SJagan Teki 277048cdfceSJernej Skrabec rotate: rotate@20000 { 278048cdfceSJernej Skrabec compatible = "allwinner,sun50i-a64-de2-rotate", 279048cdfceSJernej Skrabec "allwinner,sun8i-a83t-de2-rotate"; 280048cdfceSJernej Skrabec reg = <0x20000 0x10000>; 281048cdfceSJernej Skrabec interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 282048cdfceSJernej Skrabec clocks = <&display_clocks CLK_BUS_ROT>, 283048cdfceSJernej Skrabec <&display_clocks CLK_ROT>; 284048cdfceSJernej Skrabec clock-names = "bus", 285048cdfceSJernej Skrabec "mod"; 286048cdfceSJernej Skrabec resets = <&display_clocks RST_ROT>; 287048cdfceSJernej Skrabec }; 288048cdfceSJernej Skrabec 289e85f28e0SJagan Teki mixer0: mixer@100000 { 290e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-0"; 291e85f28e0SJagan Teki reg = <0x100000 0x100000>; 292e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER0>, 293e85f28e0SJagan Teki <&display_clocks CLK_MIXER0>; 294e85f28e0SJagan Teki clock-names = "bus", 295e85f28e0SJagan Teki "mod"; 296e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER0>; 297e85f28e0SJagan Teki 298e85f28e0SJagan Teki ports { 299e85f28e0SJagan Teki #address-cells = <1>; 300e85f28e0SJagan Teki #size-cells = <0>; 301e85f28e0SJagan Teki 302e85f28e0SJagan Teki mixer0_out: port@1 { 303a7f7047fSMaxime Ripard #address-cells = <1>; 304a7f7047fSMaxime Ripard #size-cells = <0>; 305e85f28e0SJagan Teki reg = <1>; 306e85f28e0SJagan Teki 307a7f7047fSMaxime Ripard mixer0_out_tcon0: endpoint@0 { 308a7f7047fSMaxime Ripard reg = <0>; 309e85f28e0SJagan Teki remote-endpoint = <&tcon0_in_mixer0>; 310e85f28e0SJagan Teki }; 311a7f7047fSMaxime Ripard 312a7f7047fSMaxime Ripard mixer0_out_tcon1: endpoint@1 { 313a7f7047fSMaxime Ripard reg = <1>; 314a7f7047fSMaxime Ripard remote-endpoint = <&tcon1_in_mixer0>; 315a7f7047fSMaxime Ripard }; 316e85f28e0SJagan Teki }; 317e85f28e0SJagan Teki }; 318e85f28e0SJagan Teki }; 319e85f28e0SJagan Teki 320e85f28e0SJagan Teki mixer1: mixer@200000 { 321e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-de2-mixer-1"; 322e85f28e0SJagan Teki reg = <0x200000 0x100000>; 323e85f28e0SJagan Teki clocks = <&display_clocks CLK_BUS_MIXER1>, 324e85f28e0SJagan Teki <&display_clocks CLK_MIXER1>; 325e85f28e0SJagan Teki clock-names = "bus", 326e85f28e0SJagan Teki "mod"; 327e85f28e0SJagan Teki resets = <&display_clocks RST_MIXER1>; 328e85f28e0SJagan Teki 329e85f28e0SJagan Teki ports { 330e85f28e0SJagan Teki #address-cells = <1>; 331e85f28e0SJagan Teki #size-cells = <0>; 332e85f28e0SJagan Teki 333e85f28e0SJagan Teki mixer1_out: port@1 { 334d41a43a0SMaxime Ripard #address-cells = <1>; 335d41a43a0SMaxime Ripard #size-cells = <0>; 336e85f28e0SJagan Teki reg = <1>; 337e85f28e0SJagan Teki 338a7f7047fSMaxime Ripard mixer1_out_tcon0: endpoint@0 { 339a7f7047fSMaxime Ripard reg = <0>; 340a7f7047fSMaxime Ripard remote-endpoint = <&tcon0_in_mixer1>; 341a7f7047fSMaxime Ripard }; 342a7f7047fSMaxime Ripard 343a7f7047fSMaxime Ripard mixer1_out_tcon1: endpoint@1 { 344a7f7047fSMaxime Ripard reg = <1>; 345e85f28e0SJagan Teki remote-endpoint = <&tcon1_in_mixer1>; 346e85f28e0SJagan Teki }; 347e85f28e0SJagan Teki }; 348e85f28e0SJagan Teki }; 349e85f28e0SJagan Teki }; 3502c796fc8SIcenowy Zheng }; 3512c796fc8SIcenowy Zheng 35279b95360SCorentin Labbe syscon: syscon@1c00000 { 3531f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-system-control"; 35479b95360SCorentin Labbe reg = <0x01c00000 0x1000>; 3551f1f5183SIcenowy Zheng #address-cells = <1>; 3561f1f5183SIcenowy Zheng #size-cells = <1>; 3571f1f5183SIcenowy Zheng ranges; 3581f1f5183SIcenowy Zheng 3591f1f5183SIcenowy Zheng sram_c: sram@18000 { 3601f1f5183SIcenowy Zheng compatible = "mmio-sram"; 3611f1f5183SIcenowy Zheng reg = <0x00018000 0x28000>; 3621f1f5183SIcenowy Zheng #address-cells = <1>; 3631f1f5183SIcenowy Zheng #size-cells = <1>; 3641f1f5183SIcenowy Zheng ranges = <0 0x00018000 0x28000>; 3651f1f5183SIcenowy Zheng 3661f1f5183SIcenowy Zheng de2_sram: sram-section@0 { 3671f1f5183SIcenowy Zheng compatible = "allwinner,sun50i-a64-sram-c"; 3681f1f5183SIcenowy Zheng reg = <0x0000 0x28000>; 3691f1f5183SIcenowy Zheng }; 3701f1f5183SIcenowy Zheng }; 371106deea8SPaul Kocialkowski 372106deea8SPaul Kocialkowski sram_c1: sram@1d00000 { 373106deea8SPaul Kocialkowski compatible = "mmio-sram"; 374106deea8SPaul Kocialkowski reg = <0x01d00000 0x40000>; 375106deea8SPaul Kocialkowski #address-cells = <1>; 376106deea8SPaul Kocialkowski #size-cells = <1>; 377106deea8SPaul Kocialkowski ranges = <0 0x01d00000 0x40000>; 378106deea8SPaul Kocialkowski 379106deea8SPaul Kocialkowski ve_sram: sram-section@0 { 380106deea8SPaul Kocialkowski compatible = "allwinner,sun50i-a64-sram-c1", 381106deea8SPaul Kocialkowski "allwinner,sun4i-a10-sram-c1"; 382106deea8SPaul Kocialkowski reg = <0x000000 0x40000>; 383106deea8SPaul Kocialkowski }; 384106deea8SPaul Kocialkowski }; 38579b95360SCorentin Labbe }; 38679b95360SCorentin Labbe 387c32637e0SStefan Brüns dma: dma-controller@1c02000 { 388c32637e0SStefan Brüns compatible = "allwinner,sun50i-a64-dma"; 389c32637e0SStefan Brüns reg = <0x01c02000 0x1000>; 390c32637e0SStefan Brüns interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 391c32637e0SStefan Brüns clocks = <&ccu CLK_BUS_DMA>; 392c32637e0SStefan Brüns dma-channels = <8>; 393c32637e0SStefan Brüns dma-requests = <27>; 394c32637e0SStefan Brüns resets = <&ccu RST_BUS_DMA>; 395c32637e0SStefan Brüns #dma-cells = <1>; 396c32637e0SStefan Brüns }; 397c32637e0SStefan Brüns 398e85f28e0SJagan Teki tcon0: lcd-controller@1c0c000 { 399e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-lcd", 400e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-lcd"; 401e85f28e0SJagan Teki reg = <0x01c0c000 0x1000>; 402e85f28e0SJagan Teki interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 403e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 404e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch0"; 405e85f28e0SJagan Teki clock-output-names = "tcon-pixel-clock"; 40626c609d5SMaxime Ripard #clock-cells = <0>; 407e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 408e85f28e0SJagan Teki reset-names = "lcd", "lvds"; 409e85f28e0SJagan Teki 410e85f28e0SJagan Teki ports { 411e85f28e0SJagan Teki #address-cells = <1>; 412e85f28e0SJagan Teki #size-cells = <0>; 413e85f28e0SJagan Teki 414e85f28e0SJagan Teki tcon0_in: port@0 { 415e85f28e0SJagan Teki #address-cells = <1>; 416e85f28e0SJagan Teki #size-cells = <0>; 417e85f28e0SJagan Teki reg = <0>; 418e85f28e0SJagan Teki 419e85f28e0SJagan Teki tcon0_in_mixer0: endpoint@0 { 420e85f28e0SJagan Teki reg = <0>; 421e85f28e0SJagan Teki remote-endpoint = <&mixer0_out_tcon0>; 422e85f28e0SJagan Teki }; 423a7f7047fSMaxime Ripard 424a7f7047fSMaxime Ripard tcon0_in_mixer1: endpoint@1 { 425a7f7047fSMaxime Ripard reg = <1>; 426d41a43a0SMaxime Ripard remote-endpoint = <&mixer1_out_tcon0>; 427a7f7047fSMaxime Ripard }; 428e85f28e0SJagan Teki }; 429e85f28e0SJagan Teki 430e85f28e0SJagan Teki tcon0_out: port@1 { 431e85f28e0SJagan Teki #address-cells = <1>; 432e85f28e0SJagan Teki #size-cells = <0>; 433e85f28e0SJagan Teki reg = <1>; 43416c8ff57SJagan Teki 43516c8ff57SJagan Teki tcon0_out_dsi: endpoint@1 { 43616c8ff57SJagan Teki reg = <1>; 43716c8ff57SJagan Teki remote-endpoint = <&dsi_in_tcon0>; 43816c8ff57SJagan Teki allwinner,tcon-channel = <1>; 43916c8ff57SJagan Teki }; 440e85f28e0SJagan Teki }; 441e85f28e0SJagan Teki }; 442e85f28e0SJagan Teki }; 443e85f28e0SJagan Teki 444e85f28e0SJagan Teki tcon1: lcd-controller@1c0d000 { 445e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-tcon-tv", 446e85f28e0SJagan Teki "allwinner,sun8i-a83t-tcon-tv"; 447e85f28e0SJagan Teki reg = <0x01c0d000 0x1000>; 448e85f28e0SJagan Teki interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 449e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 450e85f28e0SJagan Teki clock-names = "ahb", "tcon-ch1"; 451e85f28e0SJagan Teki resets = <&ccu RST_BUS_TCON1>; 452e85f28e0SJagan Teki reset-names = "lcd"; 453e85f28e0SJagan Teki 454e85f28e0SJagan Teki ports { 455e85f28e0SJagan Teki #address-cells = <1>; 456e85f28e0SJagan Teki #size-cells = <0>; 457e85f28e0SJagan Teki 458e85f28e0SJagan Teki tcon1_in: port@0 { 459a7f7047fSMaxime Ripard #address-cells = <1>; 460a7f7047fSMaxime Ripard #size-cells = <0>; 461e85f28e0SJagan Teki reg = <0>; 462e85f28e0SJagan Teki 463a7f7047fSMaxime Ripard tcon1_in_mixer0: endpoint@0 { 464a7f7047fSMaxime Ripard reg = <0>; 465a7f7047fSMaxime Ripard remote-endpoint = <&mixer0_out_tcon1>; 466a7f7047fSMaxime Ripard }; 467a7f7047fSMaxime Ripard 468a7f7047fSMaxime Ripard tcon1_in_mixer1: endpoint@1 { 469a7f7047fSMaxime Ripard reg = <1>; 470e85f28e0SJagan Teki remote-endpoint = <&mixer1_out_tcon1>; 471e85f28e0SJagan Teki }; 472e85f28e0SJagan Teki }; 473e85f28e0SJagan Teki 474e85f28e0SJagan Teki tcon1_out: port@1 { 475e85f28e0SJagan Teki #address-cells = <1>; 476e85f28e0SJagan Teki #size-cells = <0>; 477e85f28e0SJagan Teki reg = <1>; 478e85f28e0SJagan Teki 479e85f28e0SJagan Teki tcon1_out_hdmi: endpoint@1 { 480e85f28e0SJagan Teki reg = <1>; 481e85f28e0SJagan Teki remote-endpoint = <&hdmi_in_tcon1>; 482e85f28e0SJagan Teki }; 483e85f28e0SJagan Teki }; 484e85f28e0SJagan Teki }; 485e85f28e0SJagan Teki }; 486e85f28e0SJagan Teki 487d60ce247SPaul Kocialkowski video-codec@1c0e000 { 4884ab88516SPaul Kocialkowski compatible = "allwinner,sun50i-a64-video-engine"; 489d60ce247SPaul Kocialkowski reg = <0x01c0e000 0x1000>; 490d60ce247SPaul Kocialkowski clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 491d60ce247SPaul Kocialkowski <&ccu CLK_DRAM_VE>; 492d60ce247SPaul Kocialkowski clock-names = "ahb", "mod", "ram"; 493d60ce247SPaul Kocialkowski resets = <&ccu RST_BUS_VE>; 494d60ce247SPaul Kocialkowski interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 495d60ce247SPaul Kocialkowski allwinner,sram = <&ve_sram 1>; 496d60ce247SPaul Kocialkowski }; 497d60ce247SPaul Kocialkowski 498f3dff347SAndre Przywara mmc0: mmc@1c0f000 { 499f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 500f3dff347SAndre Przywara reg = <0x01c0f000 0x1000>; 501f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 502f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 503f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC0>; 504f3dff347SAndre Przywara reset-names = "ahb"; 505f3dff347SAndre Przywara interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 50622be992fSMaxime Ripard max-frequency = <150000000>; 507f3dff347SAndre Przywara status = "disabled"; 508f3dff347SAndre Przywara #address-cells = <1>; 509f3dff347SAndre Przywara #size-cells = <0>; 510f3dff347SAndre Przywara }; 511f3dff347SAndre Przywara 512f3dff347SAndre Przywara mmc1: mmc@1c10000 { 513f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-mmc"; 514f3dff347SAndre Przywara reg = <0x01c10000 0x1000>; 515f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 516f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 517f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC1>; 518f3dff347SAndre Przywara reset-names = "ahb"; 519f3dff347SAndre Przywara interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 52022be992fSMaxime Ripard max-frequency = <150000000>; 521f3dff347SAndre Przywara status = "disabled"; 522f3dff347SAndre Przywara #address-cells = <1>; 523f3dff347SAndre Przywara #size-cells = <0>; 524f3dff347SAndre Przywara }; 525f3dff347SAndre Przywara 526f3dff347SAndre Przywara mmc2: mmc@1c11000 { 527f3dff347SAndre Przywara compatible = "allwinner,sun50i-a64-emmc"; 528f3dff347SAndre Przywara reg = <0x01c11000 0x1000>; 529f3dff347SAndre Przywara clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 530f3dff347SAndre Przywara clock-names = "ahb", "mmc"; 531f3dff347SAndre Przywara resets = <&ccu RST_BUS_MMC2>; 532f3dff347SAndre Przywara reset-names = "ahb"; 533f3dff347SAndre Przywara interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 53422be992fSMaxime Ripard max-frequency = <200000000>; 535f3dff347SAndre Przywara status = "disabled"; 536f3dff347SAndre Przywara #address-cells = <1>; 537f3dff347SAndre Przywara #size-cells = <0>; 538f3dff347SAndre Przywara }; 539f3dff347SAndre Przywara 540ac947b17SEmmanuel Vadot sid: eeprom@1c14000 { 541ac947b17SEmmanuel Vadot compatible = "allwinner,sun50i-a64-sid"; 542ac947b17SEmmanuel Vadot reg = <0x1c14000 0x400>; 54359f5e9b9SVasily Khoruzhick #address-cells = <1>; 54459f5e9b9SVasily Khoruzhick #size-cells = <1>; 54559f5e9b9SVasily Khoruzhick 54659f5e9b9SVasily Khoruzhick ths_calibration: thermal-sensor-calibration@34 { 54759f5e9b9SVasily Khoruzhick reg = <0x34 0x8>; 54859f5e9b9SVasily Khoruzhick }; 549ac947b17SEmmanuel Vadot }; 550ac947b17SEmmanuel Vadot 5510f5fc158SCorentin Labbe crypto: crypto@1c15000 { 5520f5fc158SCorentin Labbe compatible = "allwinner,sun50i-a64-crypto"; 5530f5fc158SCorentin Labbe reg = <0x01c15000 0x1000>; 5540f5fc158SCorentin Labbe interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 5550f5fc158SCorentin Labbe clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 5560f5fc158SCorentin Labbe clock-names = "bus", "mod"; 5570f5fc158SCorentin Labbe resets = <&ccu RST_BUS_CE>; 5580f5fc158SCorentin Labbe }; 5590f5fc158SCorentin Labbe 560d6c9da12SCorentin LABBE usb_otg: usb@1c19000 { 561972a3ecdSIcenowy Zheng compatible = "allwinner,sun8i-a33-musb"; 562972a3ecdSIcenowy Zheng reg = <0x01c19000 0x0400>; 563972a3ecdSIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 564972a3ecdSIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 565972a3ecdSIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 566972a3ecdSIcenowy Zheng interrupt-names = "mc"; 567972a3ecdSIcenowy Zheng phys = <&usbphy 0>; 568972a3ecdSIcenowy Zheng phy-names = "usb"; 569972a3ecdSIcenowy Zheng extcon = <&usbphy 0>; 5700973c06bSMaxime Ripard dr_mode = "otg"; 571972a3ecdSIcenowy Zheng status = "disabled"; 572972a3ecdSIcenowy Zheng }; 573972a3ecdSIcenowy Zheng 574d6c9da12SCorentin LABBE usbphy: phy@1c19400 { 575a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-usb-phy"; 576a004ee35SIcenowy Zheng reg = <0x01c19400 0x14>, 5770d984797SIcenowy Zheng <0x01c1a800 0x4>, 578a004ee35SIcenowy Zheng <0x01c1b800 0x4>; 579a004ee35SIcenowy Zheng reg-names = "phy_ctrl", 5800d984797SIcenowy Zheng "pmu0", 581a004ee35SIcenowy Zheng "pmu1"; 582a004ee35SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>, 583a004ee35SIcenowy Zheng <&ccu CLK_USB_PHY1>; 584a004ee35SIcenowy Zheng clock-names = "usb0_phy", 585a004ee35SIcenowy Zheng "usb1_phy"; 586a004ee35SIcenowy Zheng resets = <&ccu RST_USB_PHY0>, 587a004ee35SIcenowy Zheng <&ccu RST_USB_PHY1>; 588a004ee35SIcenowy Zheng reset-names = "usb0_reset", 589a004ee35SIcenowy Zheng "usb1_reset"; 590a004ee35SIcenowy Zheng status = "disabled"; 591a004ee35SIcenowy Zheng #phy-cells = <1>; 592a004ee35SIcenowy Zheng }; 593a004ee35SIcenowy Zheng 594d6c9da12SCorentin LABBE ehci0: usb@1c1a000 { 595dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 596dc03a047SIcenowy Zheng reg = <0x01c1a000 0x100>; 597dc03a047SIcenowy Zheng interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 598dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 599dc03a047SIcenowy Zheng <&ccu CLK_BUS_EHCI0>, 600dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 601dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>, 602dc03a047SIcenowy Zheng <&ccu RST_BUS_EHCI0>; 603dc03a047SIcenowy Zheng status = "disabled"; 604dc03a047SIcenowy Zheng }; 605dc03a047SIcenowy Zheng 606d6c9da12SCorentin LABBE ohci0: usb@1c1a400 { 607dc03a047SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 608dc03a047SIcenowy Zheng reg = <0x01c1a400 0x100>; 609dc03a047SIcenowy Zheng interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 610dc03a047SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI0>, 611dc03a047SIcenowy Zheng <&ccu CLK_USB_OHCI0>; 612dc03a047SIcenowy Zheng resets = <&ccu RST_BUS_OHCI0>; 613dc03a047SIcenowy Zheng status = "disabled"; 614dc03a047SIcenowy Zheng }; 615dc03a047SIcenowy Zheng 616d6c9da12SCorentin LABBE ehci1: usb@1c1b000 { 617a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 618a004ee35SIcenowy Zheng reg = <0x01c1b000 0x100>; 619a004ee35SIcenowy Zheng interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 620a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 621a004ee35SIcenowy Zheng <&ccu CLK_BUS_EHCI1>, 622a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 623a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>, 624a004ee35SIcenowy Zheng <&ccu RST_BUS_EHCI1>; 625a004ee35SIcenowy Zheng phys = <&usbphy 1>; 626e6064cf4SMaxime Ripard phy-names = "usb"; 627a004ee35SIcenowy Zheng status = "disabled"; 628a004ee35SIcenowy Zheng }; 629a004ee35SIcenowy Zheng 630d6c9da12SCorentin LABBE ohci1: usb@1c1b400 { 631a004ee35SIcenowy Zheng compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 632a004ee35SIcenowy Zheng reg = <0x01c1b400 0x100>; 633a004ee35SIcenowy Zheng interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 634a004ee35SIcenowy Zheng clocks = <&ccu CLK_BUS_OHCI1>, 635a004ee35SIcenowy Zheng <&ccu CLK_USB_OHCI1>; 636a004ee35SIcenowy Zheng resets = <&ccu RST_BUS_OHCI1>; 637a004ee35SIcenowy Zheng phys = <&usbphy 1>; 638e6064cf4SMaxime Ripard phy-names = "usb"; 639a004ee35SIcenowy Zheng status = "disabled"; 640a004ee35SIcenowy Zheng }; 641a004ee35SIcenowy Zheng 642d6c9da12SCorentin LABBE ccu: clock@1c20000 { 6436bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-ccu"; 6446bc37facSAndre Przywara reg = <0x01c20000 0x400>; 64544ff3cafSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>; 6466bc37facSAndre Przywara clock-names = "hosc", "losc"; 6476bc37facSAndre Przywara #clock-cells = <1>; 6486bc37facSAndre Przywara #reset-cells = <1>; 6496bc37facSAndre Przywara }; 6506bc37facSAndre Przywara 6516bc37facSAndre Przywara pio: pinctrl@1c20800 { 6526bc37facSAndre Przywara compatible = "allwinner,sun50i-a64-pinctrl"; 6536bc37facSAndre Przywara reg = <0x01c20800 0x400>; 6546bc37facSAndre Przywara interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 6556bc37facSAndre Przywara <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 6566bc37facSAndre Przywara <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 657b71818cbSChen-Yu Tsai clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 658562bf196SMaxime Ripard clock-names = "apb", "hosc", "losc"; 6596bc37facSAndre Przywara gpio-controller; 6606bc37facSAndre Przywara #gpio-cells = <3>; 6616bc37facSAndre Przywara interrupt-controller; 6626bc37facSAndre Przywara #interrupt-cells = <3>; 6636bc37facSAndre Przywara 664ff29f13eSJagan Teki csi_pins: csi-pins { 665ff29f13eSJagan Teki pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 666ff29f13eSJagan Teki "PE7", "PE8", "PE9", "PE10", "PE11"; 667ff29f13eSJagan Teki function = "csi"; 668ff29f13eSJagan Teki }; 669ff29f13eSJagan Teki 670f7056b28SJagan Teki /omit-if-no-ref/ 671f7056b28SJagan Teki csi_mclk_pin: csi-mclk-pin { 672f7056b28SJagan Teki pins = "PE1"; 673f7056b28SJagan Teki function = "csi"; 674f7056b28SJagan Teki }; 675f7056b28SJagan Teki 67654eac67bSMaxime Ripard i2c0_pins: i2c0-pins { 67711239fe6SHarald Geyer pins = "PH0", "PH1"; 67811239fe6SHarald Geyer function = "i2c0"; 67911239fe6SHarald Geyer }; 68011239fe6SHarald Geyer 68154eac67bSMaxime Ripard i2c1_pins: i2c1-pins { 6826bc37facSAndre Przywara pins = "PH2", "PH3"; 6836bc37facSAndre Przywara function = "i2c1"; 6846bc37facSAndre Przywara }; 6856bc37facSAndre Przywara 68629b2c68bSOndrej Jirman i2c2_pins: i2c2-pins { 68729b2c68bSOndrej Jirman pins = "PE14", "PE15"; 68829b2c68bSOndrej Jirman function = "i2c2"; 68929b2c68bSOndrej Jirman }; 69029b2c68bSOndrej Jirman 691c478a12eSIcenowy Zheng /omit-if-no-ref/ 692c478a12eSIcenowy Zheng lcd_rgb666_pins: lcd-rgb666-pins { 693c478a12eSIcenowy Zheng pins = "PD0", "PD1", "PD2", "PD3", "PD4", 694c478a12eSIcenowy Zheng "PD5", "PD6", "PD7", "PD8", "PD9", 695c478a12eSIcenowy Zheng "PD10", "PD11", "PD12", "PD13", 696c478a12eSIcenowy Zheng "PD14", "PD15", "PD16", "PD17", 697c478a12eSIcenowy Zheng "PD18", "PD19", "PD20", "PD21"; 698c478a12eSIcenowy Zheng function = "lcd0"; 699c478a12eSIcenowy Zheng }; 700c478a12eSIcenowy Zheng 701a3e8f492SMaxime Ripard mmc0_pins: mmc0-pins { 702a3e8f492SMaxime Ripard pins = "PF0", "PF1", "PF2", "PF3", 703a3e8f492SMaxime Ripard "PF4", "PF5"; 704a3e8f492SMaxime Ripard function = "mmc0"; 705a3e8f492SMaxime Ripard drive-strength = <30>; 706a3e8f492SMaxime Ripard bias-pull-up; 707a3e8f492SMaxime Ripard }; 708a3e8f492SMaxime Ripard 709a3e8f492SMaxime Ripard mmc1_pins: mmc1-pins { 710a3e8f492SMaxime Ripard pins = "PG0", "PG1", "PG2", "PG3", 711a3e8f492SMaxime Ripard "PG4", "PG5"; 712a3e8f492SMaxime Ripard function = "mmc1"; 713a3e8f492SMaxime Ripard drive-strength = <30>; 714a3e8f492SMaxime Ripard bias-pull-up; 715a3e8f492SMaxime Ripard }; 716a3e8f492SMaxime Ripard 717a3e8f492SMaxime Ripard mmc2_pins: mmc2-pins { 718fa59dd2eSChen-Yu Tsai pins = "PC5", "PC6", "PC8", "PC9", 719a3e8f492SMaxime Ripard "PC10","PC11", "PC12", "PC13", 720a3e8f492SMaxime Ripard "PC14", "PC15", "PC16"; 721a3e8f492SMaxime Ripard function = "mmc2"; 722a3e8f492SMaxime Ripard drive-strength = <30>; 723a3e8f492SMaxime Ripard bias-pull-up; 724a3e8f492SMaxime Ripard }; 725a3e8f492SMaxime Ripard 726fa59dd2eSChen-Yu Tsai mmc2_ds_pin: mmc2-ds-pin { 727fa59dd2eSChen-Yu Tsai pins = "PC1"; 728fa59dd2eSChen-Yu Tsai function = "mmc2"; 729fa59dd2eSChen-Yu Tsai drive-strength = <30>; 730fa59dd2eSChen-Yu Tsai bias-pull-up; 731fa59dd2eSChen-Yu Tsai }; 732fa59dd2eSChen-Yu Tsai 73354eac67bSMaxime Ripard pwm_pin: pwm-pin { 734b5df280bSAndre Przywara pins = "PD22"; 735b5df280bSAndre Przywara function = "pwm"; 736b5df280bSAndre Przywara }; 737b5df280bSAndre Przywara 73854eac67bSMaxime Ripard rmii_pins: rmii-pins { 739e53f67e9SCorentin Labbe pins = "PD10", "PD11", "PD13", "PD14", "PD17", 740e53f67e9SCorentin Labbe "PD18", "PD19", "PD20", "PD22", "PD23"; 741e53f67e9SCorentin Labbe function = "emac"; 742e53f67e9SCorentin Labbe drive-strength = <40>; 743e53f67e9SCorentin Labbe }; 744e53f67e9SCorentin Labbe 74554eac67bSMaxime Ripard rgmii_pins: rgmii-pins { 746e53f67e9SCorentin Labbe pins = "PD8", "PD9", "PD10", "PD11", "PD12", 747e53f67e9SCorentin Labbe "PD13", "PD15", "PD16", "PD17", "PD18", 748e53f67e9SCorentin Labbe "PD19", "PD20", "PD21", "PD22", "PD23"; 749e53f67e9SCorentin Labbe function = "emac"; 750e53f67e9SCorentin Labbe drive-strength = <40>; 751e53f67e9SCorentin Labbe }; 752e53f67e9SCorentin Labbe 75354eac67bSMaxime Ripard spdif_tx_pin: spdif-tx-pin { 754b399d2acSMarcus Cooper pins = "PH8"; 755b399d2acSMarcus Cooper function = "spdif"; 756b399d2acSMarcus Cooper }; 757b399d2acSMarcus Cooper 75854eac67bSMaxime Ripard spi0_pins: spi0-pins { 759b518bb15SStefan Brüns pins = "PC0", "PC1", "PC2", "PC3"; 760b518bb15SStefan Brüns function = "spi0"; 761b518bb15SStefan Brüns }; 762b518bb15SStefan Brüns 76354eac67bSMaxime Ripard spi1_pins: spi1-pins { 764b518bb15SStefan Brüns pins = "PD0", "PD1", "PD2", "PD3"; 765b518bb15SStefan Brüns function = "spi1"; 766b518bb15SStefan Brüns }; 767b518bb15SStefan Brüns 768d91ebb95SChen-Yu Tsai uart0_pb_pins: uart0-pb-pins { 7696bc37facSAndre Przywara pins = "PB8", "PB9"; 7706bc37facSAndre Przywara function = "uart0"; 7716bc37facSAndre Przywara }; 772e7ba733dSAndre Przywara 77354eac67bSMaxime Ripard uart1_pins: uart1-pins { 774e7ba733dSAndre Przywara pins = "PG6", "PG7"; 775e7ba733dSAndre Przywara function = "uart1"; 776e7ba733dSAndre Przywara }; 777e7ba733dSAndre Przywara 77854eac67bSMaxime Ripard uart1_rts_cts_pins: uart1-rts-cts-pins { 779e7ba733dSAndre Przywara pins = "PG8", "PG9"; 780e7ba733dSAndre Przywara function = "uart1"; 781e7ba733dSAndre Przywara }; 78279825719SAndreas Färber 78379825719SAndreas Färber uart2_pins: uart2-pins { 78479825719SAndreas Färber pins = "PB0", "PB1"; 78579825719SAndreas Färber function = "uart2"; 78679825719SAndreas Färber }; 7872273aa16SAndreas Färber 7882273aa16SAndreas Färber uart3_pins: uart3-pins { 7892273aa16SAndreas Färber pins = "PD0", "PD1"; 7902273aa16SAndreas Färber function = "uart3"; 7912273aa16SAndreas Färber }; 7922273aa16SAndreas Färber 7932273aa16SAndreas Färber uart4_pins: uart4-pins { 7942273aa16SAndreas Färber pins = "PD2", "PD3"; 7952273aa16SAndreas Färber function = "uart4"; 7962273aa16SAndreas Färber }; 7972273aa16SAndreas Färber 7982273aa16SAndreas Färber uart4_rts_cts_pins: uart4-rts-cts-pins { 7992273aa16SAndreas Färber pins = "PD4", "PD5"; 8002273aa16SAndreas Färber function = "uart4"; 8012273aa16SAndreas Färber }; 8026bc37facSAndre Przywara }; 8036bc37facSAndre Przywara 804b399d2acSMarcus Cooper spdif: spdif@1c21000 { 805b399d2acSMarcus Cooper #sound-dai-cells = <0>; 806b399d2acSMarcus Cooper compatible = "allwinner,sun50i-a64-spdif", 807b399d2acSMarcus Cooper "allwinner,sun8i-h3-spdif"; 808b399d2acSMarcus Cooper reg = <0x01c21000 0x400>; 809b399d2acSMarcus Cooper interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 810b399d2acSMarcus Cooper clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 811b399d2acSMarcus Cooper resets = <&ccu RST_BUS_SPDIF>; 812b399d2acSMarcus Cooper clock-names = "apb", "spdif"; 813b399d2acSMarcus Cooper dmas = <&dma 2>; 814b399d2acSMarcus Cooper dma-names = "tx"; 815b399d2acSMarcus Cooper pinctrl-names = "default"; 816b399d2acSMarcus Cooper pinctrl-0 = <&spdif_tx_pin>; 817b399d2acSMarcus Cooper status = "disabled"; 818b399d2acSMarcus Cooper }; 819b399d2acSMarcus Cooper 82084204fb6SLuca Weiss lradc: lradc@1c21800 { 82184204fb6SLuca Weiss compatible = "allwinner,sun50i-a64-lradc", 82284204fb6SLuca Weiss "allwinner,sun8i-a83t-r-lradc"; 82384204fb6SLuca Weiss reg = <0x01c21800 0x400>; 82484204fb6SLuca Weiss interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 82584204fb6SLuca Weiss status = "disabled"; 82684204fb6SLuca Weiss }; 82784204fb6SLuca Weiss 8281c92c009SMarcus Cooper i2s0: i2s@1c22000 { 8291c92c009SMarcus Cooper #sound-dai-cells = <0>; 8301c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8311c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8321c92c009SMarcus Cooper reg = <0x01c22000 0x400>; 8331c92c009SMarcus Cooper interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8341c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 8351c92c009SMarcus Cooper clock-names = "apb", "mod"; 8361c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S0>; 8371c92c009SMarcus Cooper dma-names = "rx", "tx"; 8381c92c009SMarcus Cooper dmas = <&dma 3>, <&dma 3>; 8391c92c009SMarcus Cooper status = "disabled"; 8401c92c009SMarcus Cooper }; 8411c92c009SMarcus Cooper 8421c92c009SMarcus Cooper i2s1: i2s@1c22400 { 8431c92c009SMarcus Cooper #sound-dai-cells = <0>; 8441c92c009SMarcus Cooper compatible = "allwinner,sun50i-a64-i2s", 8451c92c009SMarcus Cooper "allwinner,sun8i-h3-i2s"; 8461c92c009SMarcus Cooper reg = <0x01c22400 0x400>; 8471c92c009SMarcus Cooper interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8481c92c009SMarcus Cooper clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 8491c92c009SMarcus Cooper clock-names = "apb", "mod"; 8501c92c009SMarcus Cooper resets = <&ccu RST_BUS_I2S1>; 8511c92c009SMarcus Cooper dma-names = "rx", "tx"; 8521c92c009SMarcus Cooper dmas = <&dma 4>, <&dma 4>; 8531c92c009SMarcus Cooper status = "disabled"; 8541c92c009SMarcus Cooper }; 8551c92c009SMarcus Cooper 856ec4a9540SVasily Khoruzhick dai: dai@1c22c00 { 857ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 858ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-i2s"; 859ec4a9540SVasily Khoruzhick reg = <0x01c22c00 0x200>; 860ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 861ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 862ec4a9540SVasily Khoruzhick clock-names = "apb", "mod"; 863ec4a9540SVasily Khoruzhick resets = <&ccu RST_BUS_CODEC>; 864ec4a9540SVasily Khoruzhick dmas = <&dma 15>, <&dma 15>; 865ec4a9540SVasily Khoruzhick dma-names = "rx", "tx"; 866ec4a9540SVasily Khoruzhick status = "disabled"; 867ec4a9540SVasily Khoruzhick }; 868ec4a9540SVasily Khoruzhick 869ec4a9540SVasily Khoruzhick codec: codec@1c22e00 { 870ec4a9540SVasily Khoruzhick #sound-dai-cells = <0>; 871ec4a9540SVasily Khoruzhick compatible = "allwinner,sun8i-a33-codec"; 872ec4a9540SVasily Khoruzhick reg = <0x01c22e00 0x600>; 873ec4a9540SVasily Khoruzhick interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 874ec4a9540SVasily Khoruzhick clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 875ec4a9540SVasily Khoruzhick clock-names = "bus", "mod"; 876ec4a9540SVasily Khoruzhick status = "disabled"; 877ec4a9540SVasily Khoruzhick }; 878ec4a9540SVasily Khoruzhick 87959f5e9b9SVasily Khoruzhick ths: thermal-sensor@1c25000 { 88059f5e9b9SVasily Khoruzhick compatible = "allwinner,sun50i-a64-ths"; 88159f5e9b9SVasily Khoruzhick reg = <0x01c25000 0x100>; 88259f5e9b9SVasily Khoruzhick clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 88359f5e9b9SVasily Khoruzhick clock-names = "bus", "mod"; 88459f5e9b9SVasily Khoruzhick interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 88559f5e9b9SVasily Khoruzhick resets = <&ccu RST_BUS_THS>; 88659f5e9b9SVasily Khoruzhick nvmem-cells = <&ths_calibration>; 88759f5e9b9SVasily Khoruzhick nvmem-cell-names = "calibration"; 88859f5e9b9SVasily Khoruzhick #thermal-sensor-cells = <1>; 88959f5e9b9SVasily Khoruzhick }; 89059f5e9b9SVasily Khoruzhick 8916bc37facSAndre Przywara uart0: serial@1c28000 { 8926bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 8936bc37facSAndre Przywara reg = <0x01c28000 0x400>; 8946bc37facSAndre Przywara interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8956bc37facSAndre Przywara reg-shift = <2>; 8966bc37facSAndre Przywara reg-io-width = <4>; 897494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART0>; 898494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART0>; 8996bc37facSAndre Przywara status = "disabled"; 9006bc37facSAndre Przywara }; 9016bc37facSAndre Przywara 9026bc37facSAndre Przywara uart1: serial@1c28400 { 9036bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9046bc37facSAndre Przywara reg = <0x01c28400 0x400>; 9056bc37facSAndre Przywara interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 9066bc37facSAndre Przywara reg-shift = <2>; 9076bc37facSAndre Przywara reg-io-width = <4>; 908494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART1>; 909494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART1>; 9106bc37facSAndre Przywara status = "disabled"; 9116bc37facSAndre Przywara }; 9126bc37facSAndre Przywara 9136bc37facSAndre Przywara uart2: serial@1c28800 { 9146bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9156bc37facSAndre Przywara reg = <0x01c28800 0x400>; 9166bc37facSAndre Przywara interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 9176bc37facSAndre Przywara reg-shift = <2>; 9186bc37facSAndre Przywara reg-io-width = <4>; 919494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART2>; 920494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART2>; 9216bc37facSAndre Przywara status = "disabled"; 9226bc37facSAndre Przywara }; 9236bc37facSAndre Przywara 9246bc37facSAndre Przywara uart3: serial@1c28c00 { 9256bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9266bc37facSAndre Przywara reg = <0x01c28c00 0x400>; 9276bc37facSAndre Przywara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 9286bc37facSAndre Przywara reg-shift = <2>; 9296bc37facSAndre Przywara reg-io-width = <4>; 930494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART3>; 931494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART3>; 9326bc37facSAndre Przywara status = "disabled"; 9336bc37facSAndre Przywara }; 9346bc37facSAndre Przywara 9356bc37facSAndre Przywara uart4: serial@1c29000 { 9366bc37facSAndre Przywara compatible = "snps,dw-apb-uart"; 9376bc37facSAndre Przywara reg = <0x01c29000 0x400>; 9386bc37facSAndre Przywara interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 9396bc37facSAndre Przywara reg-shift = <2>; 9406bc37facSAndre Przywara reg-io-width = <4>; 941494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_UART4>; 942494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_UART4>; 9436bc37facSAndre Przywara status = "disabled"; 9446bc37facSAndre Przywara }; 9456bc37facSAndre Przywara 9466bc37facSAndre Przywara i2c0: i2c@1c2ac00 { 9476bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9486bc37facSAndre Przywara reg = <0x01c2ac00 0x400>; 9496bc37facSAndre Przywara interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 950494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C0>; 951494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C0>; 95270f76289SJagan Teki pinctrl-names = "default"; 95370f76289SJagan Teki pinctrl-0 = <&i2c0_pins>; 9546bc37facSAndre Przywara status = "disabled"; 9556bc37facSAndre Przywara #address-cells = <1>; 9566bc37facSAndre Przywara #size-cells = <0>; 9576bc37facSAndre Przywara }; 9586bc37facSAndre Przywara 9596bc37facSAndre Przywara i2c1: i2c@1c2b000 { 9606bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9616bc37facSAndre Przywara reg = <0x01c2b000 0x400>; 9626bc37facSAndre Przywara interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 963494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C1>; 964494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C1>; 96570f76289SJagan Teki pinctrl-names = "default"; 96670f76289SJagan Teki pinctrl-0 = <&i2c1_pins>; 9676bc37facSAndre Przywara status = "disabled"; 9686bc37facSAndre Przywara #address-cells = <1>; 9696bc37facSAndre Przywara #size-cells = <0>; 9706bc37facSAndre Przywara }; 9716bc37facSAndre Przywara 9726bc37facSAndre Przywara i2c2: i2c@1c2b400 { 9736bc37facSAndre Przywara compatible = "allwinner,sun6i-a31-i2c"; 9746bc37facSAndre Przywara reg = <0x01c2b400 0x400>; 9756bc37facSAndre Przywara interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 976494d8a2cSChen-Yu Tsai clocks = <&ccu CLK_BUS_I2C2>; 977494d8a2cSChen-Yu Tsai resets = <&ccu RST_BUS_I2C2>; 97829b2c68bSOndrej Jirman pinctrl-names = "default"; 97929b2c68bSOndrej Jirman pinctrl-0 = <&i2c2_pins>; 9806bc37facSAndre Przywara status = "disabled"; 9816bc37facSAndre Przywara #address-cells = <1>; 9826bc37facSAndre Przywara #size-cells = <0>; 9836bc37facSAndre Przywara }; 9846bc37facSAndre Przywara 985d6c9da12SCorentin LABBE spi0: spi@1c68000 { 986b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 987b518bb15SStefan Brüns reg = <0x01c68000 0x1000>; 988b518bb15SStefan Brüns interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 989b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 990b518bb15SStefan Brüns clock-names = "ahb", "mod"; 99106c1258aSStefan Brüns dmas = <&dma 23>, <&dma 23>; 99206c1258aSStefan Brüns dma-names = "rx", "tx"; 993b518bb15SStefan Brüns pinctrl-names = "default"; 994b518bb15SStefan Brüns pinctrl-0 = <&spi0_pins>; 995b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI0>; 996b518bb15SStefan Brüns status = "disabled"; 997b518bb15SStefan Brüns num-cs = <1>; 998b518bb15SStefan Brüns #address-cells = <1>; 999b518bb15SStefan Brüns #size-cells = <0>; 1000b518bb15SStefan Brüns }; 1001b518bb15SStefan Brüns 1002d6c9da12SCorentin LABBE spi1: spi@1c69000 { 1003b518bb15SStefan Brüns compatible = "allwinner,sun8i-h3-spi"; 1004b518bb15SStefan Brüns reg = <0x01c69000 0x1000>; 1005b518bb15SStefan Brüns interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1006b518bb15SStefan Brüns clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1007b518bb15SStefan Brüns clock-names = "ahb", "mod"; 100806c1258aSStefan Brüns dmas = <&dma 24>, <&dma 24>; 100906c1258aSStefan Brüns dma-names = "rx", "tx"; 1010b518bb15SStefan Brüns pinctrl-names = "default"; 1011b518bb15SStefan Brüns pinctrl-0 = <&spi1_pins>; 1012b518bb15SStefan Brüns resets = <&ccu RST_BUS_SPI1>; 1013b518bb15SStefan Brüns status = "disabled"; 1014b518bb15SStefan Brüns num-cs = <1>; 1015b518bb15SStefan Brüns #address-cells = <1>; 1016b518bb15SStefan Brüns #size-cells = <0>; 1017b518bb15SStefan Brüns }; 1018b518bb15SStefan Brüns 101994f44288SCorentin Labbe emac: ethernet@1c30000 { 102094f44288SCorentin Labbe compatible = "allwinner,sun50i-a64-emac"; 102194f44288SCorentin Labbe syscon = <&syscon>; 102294f44288SCorentin Labbe reg = <0x01c30000 0x10000>; 102394f44288SCorentin Labbe interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 102494f44288SCorentin Labbe interrupt-names = "macirq"; 102594f44288SCorentin Labbe resets = <&ccu RST_BUS_EMAC>; 102694f44288SCorentin Labbe reset-names = "stmmaceth"; 102794f44288SCorentin Labbe clocks = <&ccu CLK_BUS_EMAC>; 102894f44288SCorentin Labbe clock-names = "stmmaceth"; 102994f44288SCorentin Labbe status = "disabled"; 103094f44288SCorentin Labbe 103194f44288SCorentin Labbe mdio: mdio { 103216416084SCorentin Labbe compatible = "snps,dwmac-mdio"; 103394f44288SCorentin Labbe #address-cells = <1>; 103494f44288SCorentin Labbe #size-cells = <0>; 103594f44288SCorentin Labbe }; 103694f44288SCorentin Labbe }; 103794f44288SCorentin Labbe 10386b683d76SJagan Teki mali: gpu@1c40000 { 10396b683d76SJagan Teki compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 10406b683d76SJagan Teki reg = <0x01c40000 0x10000>; 10416b683d76SJagan Teki interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 10426b683d76SJagan Teki <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 10436b683d76SJagan Teki <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 10446b683d76SJagan Teki <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 10456b683d76SJagan Teki <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 10466b683d76SJagan Teki <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 10476b683d76SJagan Teki <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 10486b683d76SJagan Teki interrupt-names = "gp", 10496b683d76SJagan Teki "gpmmu", 10506b683d76SJagan Teki "pp0", 10516b683d76SJagan Teki "ppmmu0", 10526b683d76SJagan Teki "pp1", 10536b683d76SJagan Teki "ppmmu1", 10546b683d76SJagan Teki "pmu"; 10556b683d76SJagan Teki clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 10566b683d76SJagan Teki clock-names = "bus", "core"; 10576b683d76SJagan Teki resets = <&ccu RST_BUS_GPU>; 10586b683d76SJagan Teki }; 10596b683d76SJagan Teki 10606bc37facSAndre Przywara gic: interrupt-controller@1c81000 { 10616bc37facSAndre Przywara compatible = "arm,gic-400"; 10626bc37facSAndre Przywara reg = <0x01c81000 0x1000>, 10636bc37facSAndre Przywara <0x01c82000 0x2000>, 10646bc37facSAndre Przywara <0x01c84000 0x2000>, 10656bc37facSAndre Przywara <0x01c86000 0x2000>; 10666bc37facSAndre Przywara interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 10676bc37facSAndre Przywara interrupt-controller; 10686bc37facSAndre Przywara #interrupt-cells = <3>; 10696bc37facSAndre Przywara }; 10706bc37facSAndre Przywara 1071b5df280bSAndre Przywara pwm: pwm@1c21400 { 1072b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1073b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1074b5df280bSAndre Przywara reg = <0x01c21400 0x400>; 1075b5df280bSAndre Przywara clocks = <&osc24M>; 1076b5df280bSAndre Przywara pinctrl-names = "default"; 1077b5df280bSAndre Przywara pinctrl-0 = <&pwm_pin>; 1078b5df280bSAndre Przywara #pwm-cells = <3>; 1079b5df280bSAndre Przywara status = "disabled"; 1080b5df280bSAndre Przywara }; 1081b5df280bSAndre Przywara 1082fc7c2bfbSJernej Skrabec mbus: dram-controller@1c62000 { 1083fc7c2bfbSJernej Skrabec compatible = "allwinner,sun50i-a64-mbus"; 1084fc7c2bfbSJernej Skrabec reg = <0x01c62000 0x1000>; 1085fc7c2bfbSJernej Skrabec clocks = <&ccu 112>; 1086fc7c2bfbSJernej Skrabec dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1087fc7c2bfbSJernej Skrabec #interconnect-cells = <1>; 1088fc7c2bfbSJernej Skrabec }; 1089fc7c2bfbSJernej Skrabec 1090ff29f13eSJagan Teki csi: csi@1cb0000 { 1091ff29f13eSJagan Teki compatible = "allwinner,sun50i-a64-csi"; 1092ff29f13eSJagan Teki reg = <0x01cb0000 0x1000>; 1093ff29f13eSJagan Teki interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1094ff29f13eSJagan Teki clocks = <&ccu CLK_BUS_CSI>, 1095ff29f13eSJagan Teki <&ccu CLK_CSI_SCLK>, 1096ff29f13eSJagan Teki <&ccu CLK_DRAM_CSI>; 1097ff29f13eSJagan Teki clock-names = "bus", "mod", "ram"; 1098ff29f13eSJagan Teki resets = <&ccu RST_BUS_CSI>; 1099ff29f13eSJagan Teki pinctrl-names = "default"; 1100ff29f13eSJagan Teki pinctrl-0 = <&csi_pins>; 1101ff29f13eSJagan Teki status = "disabled"; 1102ff29f13eSJagan Teki }; 1103ff29f13eSJagan Teki 110416c8ff57SJagan Teki dsi: dsi@1ca0000 { 110516c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dsi"; 110616c8ff57SJagan Teki reg = <0x01ca0000 0x1000>; 110716c8ff57SJagan Teki interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 110816c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>; 110916c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 111016c8ff57SJagan Teki phys = <&dphy>; 111116c8ff57SJagan Teki phy-names = "dphy"; 111216c8ff57SJagan Teki status = "disabled"; 111316c8ff57SJagan Teki #address-cells = <1>; 111416c8ff57SJagan Teki #size-cells = <0>; 111516c8ff57SJagan Teki 111616c8ff57SJagan Teki port { 111716c8ff57SJagan Teki dsi_in_tcon0: endpoint { 111816c8ff57SJagan Teki remote-endpoint = <&tcon0_out_dsi>; 111916c8ff57SJagan Teki }; 112016c8ff57SJagan Teki }; 112116c8ff57SJagan Teki }; 112216c8ff57SJagan Teki 112316c8ff57SJagan Teki dphy: d-phy@1ca1000 { 112416c8ff57SJagan Teki compatible = "allwinner,sun50i-a64-mipi-dphy", 112516c8ff57SJagan Teki "allwinner,sun6i-a31-mipi-dphy"; 112616c8ff57SJagan Teki reg = <0x01ca1000 0x1000>; 112716c8ff57SJagan Teki clocks = <&ccu CLK_BUS_MIPI_DSI>, 112816c8ff57SJagan Teki <&ccu CLK_DSI_DPHY>; 112916c8ff57SJagan Teki clock-names = "bus", "mod"; 113016c8ff57SJagan Teki resets = <&ccu RST_BUS_MIPI_DSI>; 113116c8ff57SJagan Teki status = "disabled"; 113216c8ff57SJagan Teki #phy-cells = <0>; 113316c8ff57SJagan Teki }; 113416c8ff57SJagan Teki 1135dd00d78dSJernej Skrabec deinterlace: deinterlace@1e00000 { 1136dd00d78dSJernej Skrabec compatible = "allwinner,sun50i-a64-deinterlace", 1137dd00d78dSJernej Skrabec "allwinner,sun8i-h3-deinterlace"; 1138dd00d78dSJernej Skrabec reg = <0x01e00000 0x20000>; 1139dd00d78dSJernej Skrabec clocks = <&ccu CLK_BUS_DEINTERLACE>, 1140dd00d78dSJernej Skrabec <&ccu CLK_DEINTERLACE>, 1141dd00d78dSJernej Skrabec <&ccu CLK_DRAM_DEINTERLACE>; 1142dd00d78dSJernej Skrabec clock-names = "bus", "mod", "ram"; 1143dd00d78dSJernej Skrabec resets = <&ccu RST_BUS_DEINTERLACE>; 1144dd00d78dSJernej Skrabec interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1145dd00d78dSJernej Skrabec interconnects = <&mbus 9>; 1146dd00d78dSJernej Skrabec interconnect-names = "dma-mem"; 1147dd00d78dSJernej Skrabec }; 1148dd00d78dSJernej Skrabec 1149e85f28e0SJagan Teki hdmi: hdmi@1ee0000 { 1150e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-dw-hdmi", 1151e85f28e0SJagan Teki "allwinner,sun8i-a83t-dw-hdmi"; 1152e85f28e0SJagan Teki reg = <0x01ee0000 0x10000>; 1153e85f28e0SJagan Teki reg-io-width = <1>; 1154e85f28e0SJagan Teki interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1155e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1156e85f28e0SJagan Teki <&ccu CLK_HDMI>; 1157e85f28e0SJagan Teki clock-names = "iahb", "isfr", "tmds"; 1158e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI1>; 1159e85f28e0SJagan Teki reset-names = "ctrl"; 1160e85f28e0SJagan Teki phys = <&hdmi_phy>; 1161d40113fbSMaxime Ripard phy-names = "phy"; 1162e85f28e0SJagan Teki status = "disabled"; 1163e85f28e0SJagan Teki 1164e85f28e0SJagan Teki ports { 1165e85f28e0SJagan Teki #address-cells = <1>; 1166e85f28e0SJagan Teki #size-cells = <0>; 1167e85f28e0SJagan Teki 1168e85f28e0SJagan Teki hdmi_in: port@0 { 1169e85f28e0SJagan Teki reg = <0>; 1170e85f28e0SJagan Teki 1171e85f28e0SJagan Teki hdmi_in_tcon1: endpoint { 1172e85f28e0SJagan Teki remote-endpoint = <&tcon1_out_hdmi>; 1173e85f28e0SJagan Teki }; 1174e85f28e0SJagan Teki }; 1175e85f28e0SJagan Teki 1176e85f28e0SJagan Teki hdmi_out: port@1 { 1177e85f28e0SJagan Teki reg = <1>; 1178e85f28e0SJagan Teki }; 1179e85f28e0SJagan Teki }; 1180e85f28e0SJagan Teki }; 1181e85f28e0SJagan Teki 1182e85f28e0SJagan Teki hdmi_phy: hdmi-phy@1ef0000 { 1183e85f28e0SJagan Teki compatible = "allwinner,sun50i-a64-hdmi-phy"; 1184e85f28e0SJagan Teki reg = <0x01ef0000 0x10000>; 1185e85f28e0SJagan Teki clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1186b71818cbSChen-Yu Tsai <&ccu CLK_PLL_VIDEO0>; 1187e85f28e0SJagan Teki clock-names = "bus", "mod", "pll-0"; 1188e85f28e0SJagan Teki resets = <&ccu RST_BUS_HDMI0>; 1189e85f28e0SJagan Teki reset-names = "phy"; 1190e85f28e0SJagan Teki #phy-cells = <0>; 1191e85f28e0SJagan Teki }; 1192e85f28e0SJagan Teki 11936bc37facSAndre Przywara rtc: rtc@1f00000 { 119444ff3cafSChen-Yu Tsai compatible = "allwinner,sun50i-a64-rtc", 119544ff3cafSChen-Yu Tsai "allwinner,sun8i-h3-rtc"; 119644ff3cafSChen-Yu Tsai reg = <0x01f00000 0x400>; 11976bc37facSAndre Przywara interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 11986bc37facSAndre Przywara <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 119944ff3cafSChen-Yu Tsai clock-output-names = "osc32k", "osc32k-out", "iosc"; 1200e1a9a474SJagan Teki clocks = <&osc32k>; 1201e1a9a474SJagan Teki #clock-cells = <1>; 12026bc37facSAndre Przywara }; 1203791a9e00SIcenowy Zheng 1204535ca508SIcenowy Zheng r_intc: interrupt-controller@1f00c00 { 1205535ca508SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-intc", 1206535ca508SIcenowy Zheng "allwinner,sun6i-a31-r-intc"; 1207535ca508SIcenowy Zheng interrupt-controller; 1208535ca508SIcenowy Zheng #interrupt-cells = <2>; 1209535ca508SIcenowy Zheng reg = <0x01f00c00 0x400>; 1210535ca508SIcenowy Zheng interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1211535ca508SIcenowy Zheng }; 1212535ca508SIcenowy Zheng 1213791a9e00SIcenowy Zheng r_ccu: clock@1f01400 { 1214791a9e00SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-ccu"; 1215791a9e00SIcenowy Zheng reg = <0x01f01400 0x100>; 1216b71818cbSChen-Yu Tsai clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 1217b71818cbSChen-Yu Tsai <&ccu CLK_PLL_PERIPH0>; 1218f74994a9SChen-Yu Tsai clock-names = "hosc", "losc", "iosc", "pll-periph"; 1219791a9e00SIcenowy Zheng #clock-cells = <1>; 1220791a9e00SIcenowy Zheng #reset-cells = <1>; 1221791a9e00SIcenowy Zheng }; 1222ec427905SIcenowy Zheng 1223ec4a9540SVasily Khoruzhick codec_analog: codec-analog@1f015c0 { 1224ec4a9540SVasily Khoruzhick compatible = "allwinner,sun50i-a64-codec-analog"; 1225ec4a9540SVasily Khoruzhick reg = <0x01f015c0 0x4>; 1226ec4a9540SVasily Khoruzhick status = "disabled"; 1227ec4a9540SVasily Khoruzhick }; 1228ec4a9540SVasily Khoruzhick 1229871b5352SIcenowy Zheng r_i2c: i2c@1f02400 { 1230871b5352SIcenowy Zheng compatible = "allwinner,sun50i-a64-i2c", 1231871b5352SIcenowy Zheng "allwinner,sun6i-a31-i2c"; 1232871b5352SIcenowy Zheng reg = <0x01f02400 0x400>; 1233871b5352SIcenowy Zheng interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1234871b5352SIcenowy Zheng clocks = <&r_ccu CLK_APB0_I2C>; 1235871b5352SIcenowy Zheng resets = <&r_ccu RST_APB0_I2C>; 1236871b5352SIcenowy Zheng status = "disabled"; 1237871b5352SIcenowy Zheng #address-cells = <1>; 1238871b5352SIcenowy Zheng #size-cells = <0>; 1239871b5352SIcenowy Zheng }; 1240871b5352SIcenowy Zheng 124144a4f416SIgors Makejevs r_ir: ir@1f02000 { 124244a4f416SIgors Makejevs compatible = "allwinner,sun50i-a64-ir", 124344a4f416SIgors Makejevs "allwinner,sun6i-a31-ir"; 124444a4f416SIgors Makejevs reg = <0x01f02000 0x400>; 124544a4f416SIgors Makejevs clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 124644a4f416SIgors Makejevs clock-names = "apb", "ir"; 124744a4f416SIgors Makejevs resets = <&r_ccu RST_APB0_IR>; 124844a4f416SIgors Makejevs interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 124944a4f416SIgors Makejevs pinctrl-names = "default"; 125044a4f416SIgors Makejevs pinctrl-0 = <&r_ir_rx_pin>; 125144a4f416SIgors Makejevs status = "disabled"; 125244a4f416SIgors Makejevs }; 125344a4f416SIgors Makejevs 1254b5df280bSAndre Przywara r_pwm: pwm@1f03800 { 1255b5df280bSAndre Przywara compatible = "allwinner,sun50i-a64-pwm", 1256b5df280bSAndre Przywara "allwinner,sun5i-a13-pwm"; 1257b5df280bSAndre Przywara reg = <0x01f03800 0x400>; 1258b5df280bSAndre Przywara clocks = <&osc24M>; 1259b5df280bSAndre Przywara pinctrl-names = "default"; 1260b5df280bSAndre Przywara pinctrl-0 = <&r_pwm_pin>; 1261b5df280bSAndre Przywara #pwm-cells = <3>; 1262b5df280bSAndre Przywara status = "disabled"; 1263b5df280bSAndre Przywara }; 1264b5df280bSAndre Przywara 1265d6c9da12SCorentin LABBE r_pio: pinctrl@1f02c00 { 1266ec427905SIcenowy Zheng compatible = "allwinner,sun50i-a64-r-pinctrl"; 1267ec427905SIcenowy Zheng reg = <0x01f02c00 0x400>; 1268ec427905SIcenowy Zheng interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1269494d8a2cSChen-Yu Tsai clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1270ec427905SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 1271ec427905SIcenowy Zheng gpio-controller; 1272ec427905SIcenowy Zheng #gpio-cells = <3>; 1273ec427905SIcenowy Zheng interrupt-controller; 1274ec427905SIcenowy Zheng #interrupt-cells = <3>; 12753b38fdedSIcenowy Zheng 12761b6ff1cbSChen-Yu Tsai r_i2c_pl89_pins: r-i2c-pl89-pins { 1277871b5352SIcenowy Zheng pins = "PL8", "PL9"; 1278871b5352SIcenowy Zheng function = "s_i2c"; 1279871b5352SIcenowy Zheng }; 1280871b5352SIcenowy Zheng 128144a4f416SIgors Makejevs r_ir_rx_pin: r-ir-rx-pin { 128244a4f416SIgors Makejevs pins = "PL11"; 128344a4f416SIgors Makejevs function = "s_cir_rx"; 128444a4f416SIgors Makejevs }; 128544a4f416SIgors Makejevs 128654eac67bSMaxime Ripard r_pwm_pin: r-pwm-pin { 1287b5df280bSAndre Przywara pins = "PL10"; 1288b5df280bSAndre Przywara function = "s_pwm"; 1289b5df280bSAndre Przywara }; 1290b5df280bSAndre Przywara 129154eac67bSMaxime Ripard r_rsb_pins: r-rsb-pins { 12923b38fdedSIcenowy Zheng pins = "PL0", "PL1"; 12933b38fdedSIcenowy Zheng function = "s_rsb"; 12943b38fdedSIcenowy Zheng }; 12953b38fdedSIcenowy Zheng }; 12963b38fdedSIcenowy Zheng 12973b38fdedSIcenowy Zheng r_rsb: rsb@1f03400 { 12983b38fdedSIcenowy Zheng compatible = "allwinner,sun8i-a23-rsb"; 12993b38fdedSIcenowy Zheng reg = <0x01f03400 0x400>; 13003b38fdedSIcenowy Zheng interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 13013b38fdedSIcenowy Zheng clocks = <&r_ccu 6>; 13023b38fdedSIcenowy Zheng clock-frequency = <3000000>; 13033b38fdedSIcenowy Zheng resets = <&r_ccu 2>; 13043b38fdedSIcenowy Zheng pinctrl-names = "default"; 13053b38fdedSIcenowy Zheng pinctrl-0 = <&r_rsb_pins>; 13063b38fdedSIcenowy Zheng status = "disabled"; 13073b38fdedSIcenowy Zheng #address-cells = <1>; 13083b38fdedSIcenowy Zheng #size-cells = <0>; 1309ec427905SIcenowy Zheng }; 1310d4185043SHarald Geyer 1311d4185043SHarald Geyer wdt0: watchdog@1c20ca0 { 1312d4185043SHarald Geyer compatible = "allwinner,sun50i-a64-wdt", 1313d4185043SHarald Geyer "allwinner,sun6i-a31-wdt"; 1314d4185043SHarald Geyer reg = <0x01c20ca0 0x20>; 1315d4185043SHarald Geyer interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 13169e1975f0SMaxime Ripard clocks = <&osc24M>; 1317d4185043SHarald Geyer }; 13186bc37facSAndre Przywara }; 13196bc37facSAndre Przywara}; 1320