14e388608SAndre Przywara/*
24e388608SAndre Przywara * Copyright (c) 2016 ARM Ltd.
34e388608SAndre Przywara *
44e388608SAndre Przywara * This file is dual-licensed: you can use it either under the terms
54e388608SAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual
64e388608SAndre Przywara * licensing only applies to this file, and not this project as a
74e388608SAndre Przywara * whole.
84e388608SAndre Przywara *
94e388608SAndre Przywara *  a) This library is free software; you can redistribute it and/or
104e388608SAndre Przywara *     modify it under the terms of the GNU General Public License as
114e388608SAndre Przywara *     published by the Free Software Foundation; either version 2 of the
124e388608SAndre Przywara *     License, or (at your option) any later version.
134e388608SAndre Przywara *
144e388608SAndre Przywara *     This library is distributed in the hope that it will be useful,
154e388608SAndre Przywara *     but WITHOUT ANY WARRANTY; without even the implied warranty of
164e388608SAndre Przywara *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
174e388608SAndre Przywara *     GNU General Public License for more details.
184e388608SAndre Przywara *
194e388608SAndre Przywara * Or, alternatively,
204e388608SAndre Przywara *
214e388608SAndre Przywara *  b) Permission is hereby granted, free of charge, to any person
224e388608SAndre Przywara *     obtaining a copy of this software and associated documentation
234e388608SAndre Przywara *     files (the "Software"), to deal in the Software without
244e388608SAndre Przywara *     restriction, including without limitation the rights to use,
254e388608SAndre Przywara *     copy, modify, merge, publish, distribute, sublicense, and/or
264e388608SAndre Przywara *     sell copies of the Software, and to permit persons to whom the
274e388608SAndre Przywara *     Software is furnished to do so, subject to the following
284e388608SAndre Przywara *     conditions:
294e388608SAndre Przywara *
304e388608SAndre Przywara *     The above copyright notice and this permission notice shall be
314e388608SAndre Przywara *     included in all copies or substantial portions of the Software.
324e388608SAndre Przywara *
334e388608SAndre Przywara *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
344e388608SAndre Przywara *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
354e388608SAndre Przywara *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
364e388608SAndre Przywara *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
374e388608SAndre Przywara *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
384e388608SAndre Przywara *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
394e388608SAndre Przywara *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
404e388608SAndre Przywara *     OTHER DEALINGS IN THE SOFTWARE.
414e388608SAndre Przywara */
424e388608SAndre Przywara
434e388608SAndre Przywara/dts-v1/;
444e388608SAndre Przywara
454e388608SAndre Przywara#include "sun50i-a64.dtsi"
464e388608SAndre Przywara
47ebe3ae29SAndre Przywara#include <dt-bindings/gpio/gpio.h>
48ebe3ae29SAndre Przywara
494e388608SAndre Przywara/ {
504e388608SAndre Przywara	model = "Pine64";
514e388608SAndre Przywara	compatible = "pine64,pine64", "allwinner,sun50i-a64";
524e388608SAndre Przywara
534e388608SAndre Przywara	aliases {
5494f44288SCorentin Labbe		ethernet0 = &emac;
554e388608SAndre Przywara		serial0 = &uart0;
56226ab099SAndreas Färber		serial1 = &uart1;
57226ab099SAndreas Färber		serial2 = &uart2;
58226ab099SAndreas Färber		serial3 = &uart3;
59226ab099SAndreas Färber		serial4 = &uart4;
604e388608SAndre Przywara	};
614e388608SAndre Przywara
624e388608SAndre Przywara	chosen {
634e388608SAndre Przywara		stdout-path = "serial0:115200n8";
644e388608SAndre Przywara	};
65f4e4453aSJagan Teki
66f4e4453aSJagan Teki	hdmi-connector {
67f4e4453aSJagan Teki		compatible = "hdmi-connector";
68f4e4453aSJagan Teki		type = "a";
69f4e4453aSJagan Teki
70f4e4453aSJagan Teki		port {
71f4e4453aSJagan Teki			hdmi_con_in: endpoint {
72f4e4453aSJagan Teki				remote-endpoint = <&hdmi_out_con>;
73f4e4453aSJagan Teki			};
74f4e4453aSJagan Teki		};
75f4e4453aSJagan Teki	};
76f4e4453aSJagan Teki};
77f4e4453aSJagan Teki
78f4e4453aSJagan Teki&de {
79f4e4453aSJagan Teki	status = "okay";
804e388608SAndre Przywara};
814e388608SAndre Przywara
828543e620SIcenowy Zheng&ehci0 {
838543e620SIcenowy Zheng	status = "okay";
848543e620SIcenowy Zheng};
858543e620SIcenowy Zheng
86d49f9dbcSIcenowy Zheng&ehci1 {
87d49f9dbcSIcenowy Zheng	status = "okay";
88d49f9dbcSIcenowy Zheng};
89d49f9dbcSIcenowy Zheng
9094f44288SCorentin Labbe&emac {
9194f44288SCorentin Labbe	pinctrl-names = "default";
9294f44288SCorentin Labbe	pinctrl-0 = <&rmii_pins>;
9394f44288SCorentin Labbe	phy-mode = "rmii";
9494f44288SCorentin Labbe	phy-handle = <&ext_rmii_phy1>;
95bdfe4cebSIcenowy Zheng	phy-supply = <&reg_dc1sw>;
9694f44288SCorentin Labbe	status = "okay";
9794f44288SCorentin Labbe
9894f44288SCorentin Labbe};
9994f44288SCorentin Labbe
100f4e4453aSJagan Teki&hdmi {
101f4e4453aSJagan Teki	hvcc-supply = <&reg_dldo1>;
102f4e4453aSJagan Teki	status = "okay";
103f4e4453aSJagan Teki};
104f4e4453aSJagan Teki
105f4e4453aSJagan Teki&hdmi_out {
106f4e4453aSJagan Teki	hdmi_out_con: endpoint {
107f4e4453aSJagan Teki		remote-endpoint = <&hdmi_con_in>;
108f4e4453aSJagan Teki	};
109f4e4453aSJagan Teki};
110f4e4453aSJagan Teki
1114e388608SAndre Przywara&i2c1 {
1124e388608SAndre Przywara	pinctrl-names = "default";
1134e388608SAndre Przywara	pinctrl-0 = <&i2c1_pins>;
1144e388608SAndre Przywara	status = "okay";
1154e388608SAndre Przywara};
1164e388608SAndre Przywara
1174e388608SAndre Przywara&i2c1_pins {
1184e388608SAndre Przywara	bias-pull-up;
1194e388608SAndre Przywara};
120ac93c09cSIcenowy Zheng
12194f44288SCorentin Labbe&mdio {
12294f44288SCorentin Labbe	ext_rmii_phy1: ethernet-phy@1 {
12394f44288SCorentin Labbe		compatible = "ethernet-phy-ieee802.3-c22";
12494f44288SCorentin Labbe		reg = <1>;
12594f44288SCorentin Labbe	};
12694f44288SCorentin Labbe};
12794f44288SCorentin Labbe
128ebe3ae29SAndre Przywara&mmc0 {
129ebe3ae29SAndre Przywara	pinctrl-names = "default";
130ebe3ae29SAndre Przywara	pinctrl-0 = <&mmc0_pins>;
1313f241bfaSJagan Teki	vmmc-supply = <&reg_dcdc1>;
132b75cb68dSTuomas Tynkkynen	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
133ebe3ae29SAndre Przywara	disable-wp;
134ebe3ae29SAndre Przywara	bus-width = <4>;
135ebe3ae29SAndre Przywara	status = "okay";
136ebe3ae29SAndre Przywara};
137ebe3ae29SAndre Przywara
1388543e620SIcenowy Zheng&ohci0 {
1398543e620SIcenowy Zheng	status = "okay";
1408543e620SIcenowy Zheng};
1418543e620SIcenowy Zheng
142d49f9dbcSIcenowy Zheng&ohci1 {
143d49f9dbcSIcenowy Zheng	status = "okay";
144d49f9dbcSIcenowy Zheng};
145d49f9dbcSIcenowy Zheng
1461b3010cdSIcenowy Zheng&r_rsb {
1471b3010cdSIcenowy Zheng	status = "okay";
1481b3010cdSIcenowy Zheng
1491b3010cdSIcenowy Zheng	axp803: pmic@3a3 {
1501b3010cdSIcenowy Zheng		compatible = "x-powers,axp803";
1511b3010cdSIcenowy Zheng		reg = <0x3a3>;
1521b3010cdSIcenowy Zheng		interrupt-parent = <&r_intc>;
1531b3010cdSIcenowy Zheng		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
1541b3010cdSIcenowy Zheng	};
1551b3010cdSIcenowy Zheng};
1561b3010cdSIcenowy Zheng
1572f005b44SIcenowy Zheng#include "axp803.dtsi"
1582f005b44SIcenowy Zheng
1592f005b44SIcenowy Zheng&reg_aldo2 {
1602f005b44SIcenowy Zheng	regulator-always-on;
1612f005b44SIcenowy Zheng	regulator-min-microvolt = <1800000>;
1622f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1632f005b44SIcenowy Zheng	regulator-name = "vcc-pl";
1642f005b44SIcenowy Zheng};
1652f005b44SIcenowy Zheng
1662f005b44SIcenowy Zheng&reg_aldo3 {
1672f005b44SIcenowy Zheng	regulator-always-on;
1682f005b44SIcenowy Zheng	regulator-min-microvolt = <3000000>;
1692f005b44SIcenowy Zheng	regulator-max-microvolt = <3000000>;
1702f005b44SIcenowy Zheng	regulator-name = "vcc-pll-avcc";
1712f005b44SIcenowy Zheng};
1722f005b44SIcenowy Zheng
1732f005b44SIcenowy Zheng&reg_dc1sw {
1742f005b44SIcenowy Zheng	regulator-name = "vcc-phy";
1752f005b44SIcenowy Zheng};
1762f005b44SIcenowy Zheng
1772f005b44SIcenowy Zheng&reg_dcdc1 {
1782f005b44SIcenowy Zheng	regulator-always-on;
1792f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
1802f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1812f005b44SIcenowy Zheng	regulator-name = "vcc-3v3";
1822f005b44SIcenowy Zheng};
1832f005b44SIcenowy Zheng
1842f005b44SIcenowy Zheng&reg_dcdc2 {
1852f005b44SIcenowy Zheng	regulator-always-on;
1862f005b44SIcenowy Zheng	regulator-min-microvolt = <1040000>;
1872f005b44SIcenowy Zheng	regulator-max-microvolt = <1300000>;
1882f005b44SIcenowy Zheng	regulator-name = "vdd-cpux";
1892f005b44SIcenowy Zheng};
1902f005b44SIcenowy Zheng
1912f005b44SIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */
1922f005b44SIcenowy Zheng
1932f005b44SIcenowy Zheng/*
1942f005b44SIcenowy Zheng * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
1952f005b44SIcenowy Zheng * work at 1.35V with less power consumption.
1962f005b44SIcenowy Zheng * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead.
1972f005b44SIcenowy Zheng */
1982f005b44SIcenowy Zheng&reg_dcdc5 {
1992f005b44SIcenowy Zheng	regulator-always-on;
2002f005b44SIcenowy Zheng	regulator-min-microvolt = <1360000>;
2012f005b44SIcenowy Zheng	regulator-max-microvolt = <1360000>;
2022f005b44SIcenowy Zheng	regulator-name = "vcc-dram";
2032f005b44SIcenowy Zheng};
2042f005b44SIcenowy Zheng
2052f005b44SIcenowy Zheng&reg_dcdc6 {
2062f005b44SIcenowy Zheng	regulator-always-on;
2072f005b44SIcenowy Zheng	regulator-min-microvolt = <1100000>;
2082f005b44SIcenowy Zheng	regulator-max-microvolt = <1100000>;
2092f005b44SIcenowy Zheng	regulator-name = "vdd-sys";
2102f005b44SIcenowy Zheng};
2112f005b44SIcenowy Zheng
2122f005b44SIcenowy Zheng&reg_dldo1 {
2132f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2142f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2152f005b44SIcenowy Zheng	regulator-name = "vcc-hdmi";
2162f005b44SIcenowy Zheng};
2172f005b44SIcenowy Zheng
2182f005b44SIcenowy Zheng&reg_dldo2 {
2192f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2202f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2212f005b44SIcenowy Zheng	regulator-name = "vcc-mipi";
2222f005b44SIcenowy Zheng};
2232f005b44SIcenowy Zheng
2242f005b44SIcenowy Zheng&reg_dldo4 {
2252f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2262f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2272f005b44SIcenowy Zheng	regulator-name = "vcc-wifi";
2282f005b44SIcenowy Zheng};
2292f005b44SIcenowy Zheng
2302f005b44SIcenowy Zheng&reg_eldo1 {
2312f005b44SIcenowy Zheng	regulator-min-microvolt = <1800000>;
2322f005b44SIcenowy Zheng	regulator-max-microvolt = <1800000>;
2332f005b44SIcenowy Zheng	regulator-name = "cpvdd";
2342f005b44SIcenowy Zheng};
2352f005b44SIcenowy Zheng
2362f005b44SIcenowy Zheng&reg_fldo1 {
2372f005b44SIcenowy Zheng	regulator-min-microvolt = <1200000>;
2382f005b44SIcenowy Zheng	regulator-max-microvolt = <1200000>;
2392f005b44SIcenowy Zheng	regulator-name = "vcc-1v2-hsic";
2402f005b44SIcenowy Zheng};
2412f005b44SIcenowy Zheng
2422f005b44SIcenowy Zheng/*
2432f005b44SIcenowy Zheng * The A64 chip cannot work without this regulator off, although
2442f005b44SIcenowy Zheng * it seems to be only driving the AR100 core.
2452f005b44SIcenowy Zheng * Maybe we don't still know well about CPUs domain.
2462f005b44SIcenowy Zheng */
2472f005b44SIcenowy Zheng&reg_fldo2 {
2482f005b44SIcenowy Zheng	regulator-always-on;
2492f005b44SIcenowy Zheng	regulator-min-microvolt = <1100000>;
2502f005b44SIcenowy Zheng	regulator-max-microvolt = <1100000>;
2512f005b44SIcenowy Zheng	regulator-name = "vdd-cpus";
2522f005b44SIcenowy Zheng};
2532f005b44SIcenowy Zheng
2542f005b44SIcenowy Zheng&reg_rtc_ldo {
2552f005b44SIcenowy Zheng	regulator-name = "vcc-rtc";
2562f005b44SIcenowy Zheng};
2572f005b44SIcenowy Zheng
2585cbef9f9SIcenowy Zheng&simplefb_hdmi {
2595cbef9f9SIcenowy Zheng	vcc-hdmi-supply = <&reg_dldo1>;
2605cbef9f9SIcenowy Zheng};
2615cbef9f9SIcenowy Zheng
262fcf7e5feSMarcus Cooper/* On Euler connector */
263fcf7e5feSMarcus Cooper&spdif {
264fcf7e5feSMarcus Cooper	status = "disabled";
265fcf7e5feSMarcus Cooper};
266fcf7e5feSMarcus Cooper
2672273aa16SAndreas Färber/* On Exp and Euler connectors */
268ac93c09cSIcenowy Zheng&uart0 {
269ac93c09cSIcenowy Zheng	pinctrl-names = "default";
270d91ebb95SChen-Yu Tsai	pinctrl-0 = <&uart0_pb_pins>;
271ac93c09cSIcenowy Zheng	status = "okay";
272ac93c09cSIcenowy Zheng};
273d49f9dbcSIcenowy Zheng
2742273aa16SAndreas Färber/* On Wifi/BT connector, with RTS/CTS */
2752273aa16SAndreas Färber&uart1 {
2762273aa16SAndreas Färber	pinctrl-names = "default";
2772273aa16SAndreas Färber	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
2782273aa16SAndreas Färber	status = "disabled";
2792273aa16SAndreas Färber};
2802273aa16SAndreas Färber
2812273aa16SAndreas Färber/* On Pi-2 connector */
2822273aa16SAndreas Färber&uart2 {
2832273aa16SAndreas Färber	pinctrl-names = "default";
2842273aa16SAndreas Färber	pinctrl-0 = <&uart2_pins>;
2852273aa16SAndreas Färber	status = "disabled";
2862273aa16SAndreas Färber};
2872273aa16SAndreas Färber
2882273aa16SAndreas Färber/* On Euler connector */
2892273aa16SAndreas Färber&uart3 {
2902273aa16SAndreas Färber	pinctrl-names = "default";
2912273aa16SAndreas Färber	pinctrl-0 = <&uart3_pins>;
2922273aa16SAndreas Färber	status = "disabled";
2932273aa16SAndreas Färber};
2942273aa16SAndreas Färber
2952273aa16SAndreas Färber/* On Euler connector, RTS/CTS optional */
2962273aa16SAndreas Färber&uart4 {
2972273aa16SAndreas Färber	pinctrl-names = "default";
2982273aa16SAndreas Färber	pinctrl-0 = <&uart4_pins>;
2992273aa16SAndreas Färber	status = "disabled";
3002273aa16SAndreas Färber};
3012273aa16SAndreas Färber
302f57e8384SIcenowy Zheng&usb_otg {
303f57e8384SIcenowy Zheng	dr_mode = "host";
304f57e8384SIcenowy Zheng	status = "okay";
305f57e8384SIcenowy Zheng};
306f57e8384SIcenowy Zheng
307d49f9dbcSIcenowy Zheng&usbphy {
308d49f9dbcSIcenowy Zheng	status = "okay";
309d49f9dbcSIcenowy Zheng};
310