1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2cabbaed7SClément Péron// Copyright (c) 2016 ARM Ltd. 34e388608SAndre Przywara 44e388608SAndre Przywara/dts-v1/; 54e388608SAndre Przywara 64e388608SAndre Przywara#include "sun50i-a64.dtsi" 74e388608SAndre Przywara 8ebe3ae29SAndre Przywara#include <dt-bindings/gpio/gpio.h> 9ebe3ae29SAndre Przywara 104e388608SAndre Przywara/ { 114e388608SAndre Przywara model = "Pine64"; 124e388608SAndre Przywara compatible = "pine64,pine64", "allwinner,sun50i-a64"; 134e388608SAndre Przywara 144e388608SAndre Przywara aliases { 1594f44288SCorentin Labbe ethernet0 = &emac; 164e388608SAndre Przywara serial0 = &uart0; 17226ab099SAndreas Färber serial1 = &uart1; 18226ab099SAndreas Färber serial2 = &uart2; 19226ab099SAndreas Färber serial3 = &uart3; 20226ab099SAndreas Färber serial4 = &uart4; 214e388608SAndre Przywara }; 224e388608SAndre Przywara 234e388608SAndre Przywara chosen { 244e388608SAndre Przywara stdout-path = "serial0:115200n8"; 254e388608SAndre Przywara }; 26f4e4453aSJagan Teki 27f4e4453aSJagan Teki hdmi-connector { 28f4e4453aSJagan Teki compatible = "hdmi-connector"; 29f4e4453aSJagan Teki type = "a"; 30f4e4453aSJagan Teki 31f4e4453aSJagan Teki port { 32f4e4453aSJagan Teki hdmi_con_in: endpoint { 33f4e4453aSJagan Teki remote-endpoint = <&hdmi_out_con>; 34f4e4453aSJagan Teki }; 35f4e4453aSJagan Teki }; 36f4e4453aSJagan Teki }; 37f4e4453aSJagan Teki}; 38f4e4453aSJagan Teki 39498c21f2SVasily Khoruzhick&codec { 40498c21f2SVasily Khoruzhick status = "okay"; 41498c21f2SVasily Khoruzhick}; 42498c21f2SVasily Khoruzhick 43498c21f2SVasily Khoruzhick&codec_analog { 4407de9094SChen-Yu Tsai cpvdd-supply = <®_eldo1>; 45498c21f2SVasily Khoruzhick status = "okay"; 46498c21f2SVasily Khoruzhick}; 47498c21f2SVasily Khoruzhick 48498c21f2SVasily Khoruzhick&dai { 49498c21f2SVasily Khoruzhick status = "okay"; 50498c21f2SVasily Khoruzhick}; 51498c21f2SVasily Khoruzhick 52f4e4453aSJagan Teki&de { 53f4e4453aSJagan Teki status = "okay"; 544e388608SAndre Przywara}; 554e388608SAndre Przywara 568543e620SIcenowy Zheng&ehci0 { 578543e620SIcenowy Zheng status = "okay"; 588543e620SIcenowy Zheng}; 598543e620SIcenowy Zheng 60d49f9dbcSIcenowy Zheng&ehci1 { 61d49f9dbcSIcenowy Zheng status = "okay"; 62d49f9dbcSIcenowy Zheng}; 63d49f9dbcSIcenowy Zheng 6494f44288SCorentin Labbe&emac { 6594f44288SCorentin Labbe pinctrl-names = "default"; 6694f44288SCorentin Labbe pinctrl-0 = <&rmii_pins>; 6794f44288SCorentin Labbe phy-mode = "rmii"; 6894f44288SCorentin Labbe phy-handle = <&ext_rmii_phy1>; 69bdfe4cebSIcenowy Zheng phy-supply = <®_dc1sw>; 7094f44288SCorentin Labbe status = "okay"; 7194f44288SCorentin Labbe 7294f44288SCorentin Labbe}; 7394f44288SCorentin Labbe 74f4e4453aSJagan Teki&hdmi { 75f4e4453aSJagan Teki hvcc-supply = <®_dldo1>; 76f4e4453aSJagan Teki status = "okay"; 77f4e4453aSJagan Teki}; 78f4e4453aSJagan Teki 79f4e4453aSJagan Teki&hdmi_out { 80f4e4453aSJagan Teki hdmi_out_con: endpoint { 81f4e4453aSJagan Teki remote-endpoint = <&hdmi_con_in>; 82f4e4453aSJagan Teki }; 83f4e4453aSJagan Teki}; 84f4e4453aSJagan Teki 854e388608SAndre Przywara&i2c1 { 864e388608SAndre Przywara status = "okay"; 874e388608SAndre Przywara}; 884e388608SAndre Przywara 894e388608SAndre Przywara&i2c1_pins { 904e388608SAndre Przywara bias-pull-up; 914e388608SAndre Przywara}; 92ac93c09cSIcenowy Zheng 9394f44288SCorentin Labbe&mdio { 9494f44288SCorentin Labbe ext_rmii_phy1: ethernet-phy@1 { 9594f44288SCorentin Labbe compatible = "ethernet-phy-ieee802.3-c22"; 9694f44288SCorentin Labbe reg = <1>; 9794f44288SCorentin Labbe }; 9894f44288SCorentin Labbe}; 9994f44288SCorentin Labbe 100ebe3ae29SAndre Przywara&mmc0 { 101ebe3ae29SAndre Przywara pinctrl-names = "default"; 102ebe3ae29SAndre Przywara pinctrl-0 = <&mmc0_pins>; 1033f241bfaSJagan Teki vmmc-supply = <®_dcdc1>; 104b75cb68dSTuomas Tynkkynen cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; 105ebe3ae29SAndre Przywara disable-wp; 106ebe3ae29SAndre Przywara bus-width = <4>; 107ebe3ae29SAndre Przywara status = "okay"; 108ebe3ae29SAndre Przywara}; 109ebe3ae29SAndre Przywara 1108543e620SIcenowy Zheng&ohci0 { 1118543e620SIcenowy Zheng status = "okay"; 1128543e620SIcenowy Zheng}; 1138543e620SIcenowy Zheng 114d49f9dbcSIcenowy Zheng&ohci1 { 115d49f9dbcSIcenowy Zheng status = "okay"; 116d49f9dbcSIcenowy Zheng}; 117d49f9dbcSIcenowy Zheng 1181b3010cdSIcenowy Zheng&r_rsb { 1191b3010cdSIcenowy Zheng status = "okay"; 1201b3010cdSIcenowy Zheng 1211b3010cdSIcenowy Zheng axp803: pmic@3a3 { 1221b3010cdSIcenowy Zheng compatible = "x-powers,axp803"; 1231b3010cdSIcenowy Zheng reg = <0x3a3>; 1241b3010cdSIcenowy Zheng interrupt-parent = <&r_intc>; 1251b3010cdSIcenowy Zheng interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 1261b3010cdSIcenowy Zheng }; 1271b3010cdSIcenowy Zheng}; 1281b3010cdSIcenowy Zheng 1292f005b44SIcenowy Zheng#include "axp803.dtsi" 1302f005b44SIcenowy Zheng 131a24270afSChen-Yu Tsai&ac_power_supply { 132a24270afSChen-Yu Tsai status = "okay"; 133a24270afSChen-Yu Tsai}; 134a24270afSChen-Yu Tsai 135a24270afSChen-Yu Tsai&battery_power_supply { 136a24270afSChen-Yu Tsai status = "okay"; 137a24270afSChen-Yu Tsai}; 138a24270afSChen-Yu Tsai 1392f005b44SIcenowy Zheng®_aldo2 { 1402f005b44SIcenowy Zheng regulator-always-on; 1412f005b44SIcenowy Zheng regulator-min-microvolt = <1800000>; 1422f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 1432f005b44SIcenowy Zheng regulator-name = "vcc-pl"; 1442f005b44SIcenowy Zheng}; 1452f005b44SIcenowy Zheng 1462f005b44SIcenowy Zheng®_aldo3 { 1472f005b44SIcenowy Zheng regulator-always-on; 1482f005b44SIcenowy Zheng regulator-min-microvolt = <3000000>; 1492f005b44SIcenowy Zheng regulator-max-microvolt = <3000000>; 1502f005b44SIcenowy Zheng regulator-name = "vcc-pll-avcc"; 1512f005b44SIcenowy Zheng}; 1522f005b44SIcenowy Zheng 1532f005b44SIcenowy Zheng®_dc1sw { 1542f005b44SIcenowy Zheng regulator-name = "vcc-phy"; 1552f005b44SIcenowy Zheng}; 1562f005b44SIcenowy Zheng 1572f005b44SIcenowy Zheng®_dcdc1 { 1582f005b44SIcenowy Zheng regulator-always-on; 1592f005b44SIcenowy Zheng regulator-min-microvolt = <3300000>; 1602f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 1612f005b44SIcenowy Zheng regulator-name = "vcc-3v3"; 1622f005b44SIcenowy Zheng}; 1632f005b44SIcenowy Zheng 1642f005b44SIcenowy Zheng®_dcdc2 { 1652f005b44SIcenowy Zheng regulator-always-on; 1662f005b44SIcenowy Zheng regulator-min-microvolt = <1040000>; 1672f005b44SIcenowy Zheng regulator-max-microvolt = <1300000>; 1682f005b44SIcenowy Zheng regulator-name = "vdd-cpux"; 1692f005b44SIcenowy Zheng}; 1702f005b44SIcenowy Zheng 1712f005b44SIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */ 1722f005b44SIcenowy Zheng 1732f005b44SIcenowy Zheng/* 1742f005b44SIcenowy Zheng * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can 1752f005b44SIcenowy Zheng * work at 1.35V with less power consumption. 1762f005b44SIcenowy Zheng * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead. 1772f005b44SIcenowy Zheng */ 1782f005b44SIcenowy Zheng®_dcdc5 { 1792f005b44SIcenowy Zheng regulator-always-on; 1802f005b44SIcenowy Zheng regulator-min-microvolt = <1360000>; 1812f005b44SIcenowy Zheng regulator-max-microvolt = <1360000>; 1822f005b44SIcenowy Zheng regulator-name = "vcc-dram"; 1832f005b44SIcenowy Zheng}; 1842f005b44SIcenowy Zheng 1852f005b44SIcenowy Zheng®_dcdc6 { 1862f005b44SIcenowy Zheng regulator-always-on; 1872f005b44SIcenowy Zheng regulator-min-microvolt = <1100000>; 1882f005b44SIcenowy Zheng regulator-max-microvolt = <1100000>; 1892f005b44SIcenowy Zheng regulator-name = "vdd-sys"; 1902f005b44SIcenowy Zheng}; 1912f005b44SIcenowy Zheng 1922f005b44SIcenowy Zheng®_dldo1 { 1932f005b44SIcenowy Zheng regulator-min-microvolt = <3300000>; 1942f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 1952f005b44SIcenowy Zheng regulator-name = "vcc-hdmi"; 1962f005b44SIcenowy Zheng}; 1972f005b44SIcenowy Zheng 1982f005b44SIcenowy Zheng®_dldo2 { 1992f005b44SIcenowy Zheng regulator-min-microvolt = <3300000>; 2002f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 2012f005b44SIcenowy Zheng regulator-name = "vcc-mipi"; 2022f005b44SIcenowy Zheng}; 2032f005b44SIcenowy Zheng 2042f005b44SIcenowy Zheng®_dldo4 { 2052f005b44SIcenowy Zheng regulator-min-microvolt = <3300000>; 2062f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 2072f005b44SIcenowy Zheng regulator-name = "vcc-wifi"; 2082f005b44SIcenowy Zheng}; 2092f005b44SIcenowy Zheng 2102f005b44SIcenowy Zheng®_eldo1 { 2112f005b44SIcenowy Zheng regulator-min-microvolt = <1800000>; 2122f005b44SIcenowy Zheng regulator-max-microvolt = <1800000>; 2132f005b44SIcenowy Zheng regulator-name = "cpvdd"; 2142f005b44SIcenowy Zheng}; 2152f005b44SIcenowy Zheng 2162f005b44SIcenowy Zheng®_fldo1 { 2172f005b44SIcenowy Zheng regulator-min-microvolt = <1200000>; 2182f005b44SIcenowy Zheng regulator-max-microvolt = <1200000>; 2192f005b44SIcenowy Zheng regulator-name = "vcc-1v2-hsic"; 2202f005b44SIcenowy Zheng}; 2212f005b44SIcenowy Zheng 2222f005b44SIcenowy Zheng/* 2232f005b44SIcenowy Zheng * The A64 chip cannot work without this regulator off, although 2242f005b44SIcenowy Zheng * it seems to be only driving the AR100 core. 2252f005b44SIcenowy Zheng * Maybe we don't still know well about CPUs domain. 2262f005b44SIcenowy Zheng */ 2272f005b44SIcenowy Zheng®_fldo2 { 2282f005b44SIcenowy Zheng regulator-always-on; 2292f005b44SIcenowy Zheng regulator-min-microvolt = <1100000>; 2302f005b44SIcenowy Zheng regulator-max-microvolt = <1100000>; 2312f005b44SIcenowy Zheng regulator-name = "vdd-cpus"; 2322f005b44SIcenowy Zheng}; 2332f005b44SIcenowy Zheng 2342f005b44SIcenowy Zheng®_rtc_ldo { 2352f005b44SIcenowy Zheng regulator-name = "vcc-rtc"; 2362f005b44SIcenowy Zheng}; 2372f005b44SIcenowy Zheng 2385cbef9f9SIcenowy Zheng&simplefb_hdmi { 2395cbef9f9SIcenowy Zheng vcc-hdmi-supply = <®_dldo1>; 2405cbef9f9SIcenowy Zheng}; 2415cbef9f9SIcenowy Zheng 242498c21f2SVasily Khoruzhick&sound { 243498c21f2SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 244498c21f2SVasily Khoruzhick simple-audio-card,widgets = "Microphone", "Microphone Jack", 245498c21f2SVasily Khoruzhick "Headphone", "Headphone Jack"; 246498c21f2SVasily Khoruzhick simple-audio-card,routing = 247498c21f2SVasily Khoruzhick "Left DAC", "AIF1 Slot 0 Left", 248498c21f2SVasily Khoruzhick "Right DAC", "AIF1 Slot 0 Right", 249498c21f2SVasily Khoruzhick "Headphone Jack", "HP", 250498c21f2SVasily Khoruzhick "AIF1 Slot 0 Left ADC", "Left ADC", 251498c21f2SVasily Khoruzhick "AIF1 Slot 0 Right ADC", "Right ADC", 252498c21f2SVasily Khoruzhick "MIC2", "Microphone Jack"; 253498c21f2SVasily Khoruzhick status = "okay"; 254498c21f2SVasily Khoruzhick}; 255498c21f2SVasily Khoruzhick 256fcf7e5feSMarcus Cooper/* On Euler connector */ 257fcf7e5feSMarcus Cooper&spdif { 258fcf7e5feSMarcus Cooper status = "disabled"; 259fcf7e5feSMarcus Cooper}; 260fcf7e5feSMarcus Cooper 2612273aa16SAndreas Färber/* On Exp and Euler connectors */ 262ac93c09cSIcenowy Zheng&uart0 { 263ac93c09cSIcenowy Zheng pinctrl-names = "default"; 264d91ebb95SChen-Yu Tsai pinctrl-0 = <&uart0_pb_pins>; 265ac93c09cSIcenowy Zheng status = "okay"; 266ac93c09cSIcenowy Zheng}; 267d49f9dbcSIcenowy Zheng 2682273aa16SAndreas Färber/* On Wifi/BT connector, with RTS/CTS */ 2692273aa16SAndreas Färber&uart1 { 2702273aa16SAndreas Färber pinctrl-names = "default"; 2712273aa16SAndreas Färber pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; 2722273aa16SAndreas Färber status = "disabled"; 2732273aa16SAndreas Färber}; 2742273aa16SAndreas Färber 2752273aa16SAndreas Färber/* On Pi-2 connector */ 2762273aa16SAndreas Färber&uart2 { 2772273aa16SAndreas Färber pinctrl-names = "default"; 2782273aa16SAndreas Färber pinctrl-0 = <&uart2_pins>; 2792273aa16SAndreas Färber status = "disabled"; 2802273aa16SAndreas Färber}; 2812273aa16SAndreas Färber 2822273aa16SAndreas Färber/* On Euler connector */ 2832273aa16SAndreas Färber&uart3 { 2842273aa16SAndreas Färber pinctrl-names = "default"; 2852273aa16SAndreas Färber pinctrl-0 = <&uart3_pins>; 2862273aa16SAndreas Färber status = "disabled"; 2872273aa16SAndreas Färber}; 2882273aa16SAndreas Färber 2892273aa16SAndreas Färber/* On Euler connector, RTS/CTS optional */ 2902273aa16SAndreas Färber&uart4 { 2912273aa16SAndreas Färber pinctrl-names = "default"; 2922273aa16SAndreas Färber pinctrl-0 = <&uart4_pins>; 2932273aa16SAndreas Färber status = "disabled"; 2942273aa16SAndreas Färber}; 2952273aa16SAndreas Färber 296f57e8384SIcenowy Zheng&usb_otg { 297f57e8384SIcenowy Zheng dr_mode = "host"; 298f57e8384SIcenowy Zheng status = "okay"; 299f57e8384SIcenowy Zheng}; 300f57e8384SIcenowy Zheng 301d49f9dbcSIcenowy Zheng&usbphy { 302d49f9dbcSIcenowy Zheng status = "okay"; 303d49f9dbcSIcenowy Zheng}; 304