14e388608SAndre Przywara/*
24e388608SAndre Przywara * Copyright (c) 2016 ARM Ltd.
34e388608SAndre Przywara *
44e388608SAndre Przywara * This file is dual-licensed: you can use it either under the terms
54e388608SAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual
64e388608SAndre Przywara * licensing only applies to this file, and not this project as a
74e388608SAndre Przywara * whole.
84e388608SAndre Przywara *
94e388608SAndre Przywara *  a) This library is free software; you can redistribute it and/or
104e388608SAndre Przywara *     modify it under the terms of the GNU General Public License as
114e388608SAndre Przywara *     published by the Free Software Foundation; either version 2 of the
124e388608SAndre Przywara *     License, or (at your option) any later version.
134e388608SAndre Przywara *
144e388608SAndre Przywara *     This library is distributed in the hope that it will be useful,
154e388608SAndre Przywara *     but WITHOUT ANY WARRANTY; without even the implied warranty of
164e388608SAndre Przywara *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
174e388608SAndre Przywara *     GNU General Public License for more details.
184e388608SAndre Przywara *
194e388608SAndre Przywara * Or, alternatively,
204e388608SAndre Przywara *
214e388608SAndre Przywara *  b) Permission is hereby granted, free of charge, to any person
224e388608SAndre Przywara *     obtaining a copy of this software and associated documentation
234e388608SAndre Przywara *     files (the "Software"), to deal in the Software without
244e388608SAndre Przywara *     restriction, including without limitation the rights to use,
254e388608SAndre Przywara *     copy, modify, merge, publish, distribute, sublicense, and/or
264e388608SAndre Przywara *     sell copies of the Software, and to permit persons to whom the
274e388608SAndre Przywara *     Software is furnished to do so, subject to the following
284e388608SAndre Przywara *     conditions:
294e388608SAndre Przywara *
304e388608SAndre Przywara *     The above copyright notice and this permission notice shall be
314e388608SAndre Przywara *     included in all copies or substantial portions of the Software.
324e388608SAndre Przywara *
334e388608SAndre Przywara *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
344e388608SAndre Przywara *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
354e388608SAndre Przywara *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
364e388608SAndre Przywara *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
374e388608SAndre Przywara *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
384e388608SAndre Przywara *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
394e388608SAndre Przywara *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
404e388608SAndre Przywara *     OTHER DEALINGS IN THE SOFTWARE.
414e388608SAndre Przywara */
424e388608SAndre Przywara
434e388608SAndre Przywara/dts-v1/;
444e388608SAndre Przywara
454e388608SAndre Przywara#include "sun50i-a64.dtsi"
464e388608SAndre Przywara
47ebe3ae29SAndre Przywara#include <dt-bindings/gpio/gpio.h>
48ebe3ae29SAndre Przywara
494e388608SAndre Przywara/ {
504e388608SAndre Przywara	model = "Pine64";
514e388608SAndre Przywara	compatible = "pine64,pine64", "allwinner,sun50i-a64";
524e388608SAndre Przywara
534e388608SAndre Przywara	aliases {
5494f44288SCorentin Labbe		ethernet0 = &emac;
554e388608SAndre Przywara		serial0 = &uart0;
56226ab099SAndreas Färber		serial1 = &uart1;
57226ab099SAndreas Färber		serial2 = &uart2;
58226ab099SAndreas Färber		serial3 = &uart3;
59226ab099SAndreas Färber		serial4 = &uart4;
604e388608SAndre Przywara	};
614e388608SAndre Przywara
624e388608SAndre Przywara	chosen {
634e388608SAndre Przywara		stdout-path = "serial0:115200n8";
644e388608SAndre Przywara	};
654e388608SAndre Przywara};
664e388608SAndre Przywara
678543e620SIcenowy Zheng&ehci0 {
688543e620SIcenowy Zheng	status = "okay";
698543e620SIcenowy Zheng};
708543e620SIcenowy Zheng
71d49f9dbcSIcenowy Zheng&ehci1 {
72d49f9dbcSIcenowy Zheng	status = "okay";
73d49f9dbcSIcenowy Zheng};
74d49f9dbcSIcenowy Zheng
7594f44288SCorentin Labbe&emac {
7694f44288SCorentin Labbe	pinctrl-names = "default";
7794f44288SCorentin Labbe	pinctrl-0 = <&rmii_pins>;
7894f44288SCorentin Labbe	phy-mode = "rmii";
7994f44288SCorentin Labbe	phy-handle = <&ext_rmii_phy1>;
80bdfe4cebSIcenowy Zheng	phy-supply = <&reg_dc1sw>;
8194f44288SCorentin Labbe	status = "okay";
8294f44288SCorentin Labbe
8394f44288SCorentin Labbe};
8494f44288SCorentin Labbe
854e388608SAndre Przywara&i2c1 {
864e388608SAndre Przywara	pinctrl-names = "default";
874e388608SAndre Przywara	pinctrl-0 = <&i2c1_pins>;
884e388608SAndre Przywara	status = "okay";
894e388608SAndre Przywara};
904e388608SAndre Przywara
914e388608SAndre Przywara&i2c1_pins {
924e388608SAndre Przywara	bias-pull-up;
934e388608SAndre Przywara};
94ac93c09cSIcenowy Zheng
9594f44288SCorentin Labbe&mdio {
9694f44288SCorentin Labbe	ext_rmii_phy1: ethernet-phy@1 {
9794f44288SCorentin Labbe		compatible = "ethernet-phy-ieee802.3-c22";
9894f44288SCorentin Labbe		reg = <1>;
9994f44288SCorentin Labbe	};
10094f44288SCorentin Labbe};
10194f44288SCorentin Labbe
102ebe3ae29SAndre Przywara&mmc0 {
103ebe3ae29SAndre Przywara	pinctrl-names = "default";
104ebe3ae29SAndre Przywara	pinctrl-0 = <&mmc0_pins>;
1053f241bfaSJagan Teki	vmmc-supply = <&reg_dcdc1>;
106ebe3ae29SAndre Przywara	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
107ebe3ae29SAndre Przywara	cd-inverted;
108ebe3ae29SAndre Przywara	disable-wp;
109ebe3ae29SAndre Przywara	bus-width = <4>;
110ebe3ae29SAndre Przywara	status = "okay";
111ebe3ae29SAndre Przywara};
112ebe3ae29SAndre Przywara
1138543e620SIcenowy Zheng&ohci0 {
1148543e620SIcenowy Zheng	status = "okay";
1158543e620SIcenowy Zheng};
1168543e620SIcenowy Zheng
117d49f9dbcSIcenowy Zheng&ohci1 {
118d49f9dbcSIcenowy Zheng	status = "okay";
119d49f9dbcSIcenowy Zheng};
120d49f9dbcSIcenowy Zheng
1211b3010cdSIcenowy Zheng&r_rsb {
1221b3010cdSIcenowy Zheng	status = "okay";
1231b3010cdSIcenowy Zheng
1241b3010cdSIcenowy Zheng	axp803: pmic@3a3 {
1251b3010cdSIcenowy Zheng		compatible = "x-powers,axp803";
1261b3010cdSIcenowy Zheng		reg = <0x3a3>;
1271b3010cdSIcenowy Zheng		interrupt-parent = <&r_intc>;
1281b3010cdSIcenowy Zheng		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
1291b3010cdSIcenowy Zheng	};
1301b3010cdSIcenowy Zheng};
1311b3010cdSIcenowy Zheng
1322f005b44SIcenowy Zheng#include "axp803.dtsi"
1332f005b44SIcenowy Zheng
1342f005b44SIcenowy Zheng&reg_aldo2 {
1352f005b44SIcenowy Zheng	regulator-always-on;
1362f005b44SIcenowy Zheng	regulator-min-microvolt = <1800000>;
1372f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1382f005b44SIcenowy Zheng	regulator-name = "vcc-pl";
1392f005b44SIcenowy Zheng};
1402f005b44SIcenowy Zheng
1412f005b44SIcenowy Zheng&reg_aldo3 {
1422f005b44SIcenowy Zheng	regulator-always-on;
1432f005b44SIcenowy Zheng	regulator-min-microvolt = <3000000>;
1442f005b44SIcenowy Zheng	regulator-max-microvolt = <3000000>;
1452f005b44SIcenowy Zheng	regulator-name = "vcc-pll-avcc";
1462f005b44SIcenowy Zheng};
1472f005b44SIcenowy Zheng
1482f005b44SIcenowy Zheng&reg_dc1sw {
1492f005b44SIcenowy Zheng	regulator-name = "vcc-phy";
1502f005b44SIcenowy Zheng};
1512f005b44SIcenowy Zheng
1522f005b44SIcenowy Zheng&reg_dcdc1 {
1532f005b44SIcenowy Zheng	regulator-always-on;
1542f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
1552f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1562f005b44SIcenowy Zheng	regulator-name = "vcc-3v3";
1572f005b44SIcenowy Zheng};
1582f005b44SIcenowy Zheng
1592f005b44SIcenowy Zheng&reg_dcdc2 {
1602f005b44SIcenowy Zheng	regulator-always-on;
1612f005b44SIcenowy Zheng	regulator-min-microvolt = <1040000>;
1622f005b44SIcenowy Zheng	regulator-max-microvolt = <1300000>;
1632f005b44SIcenowy Zheng	regulator-name = "vdd-cpux";
1642f005b44SIcenowy Zheng};
1652f005b44SIcenowy Zheng
1662f005b44SIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */
1672f005b44SIcenowy Zheng
1682f005b44SIcenowy Zheng/*
1692f005b44SIcenowy Zheng * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
1702f005b44SIcenowy Zheng * work at 1.35V with less power consumption.
1712f005b44SIcenowy Zheng * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead.
1722f005b44SIcenowy Zheng */
1732f005b44SIcenowy Zheng&reg_dcdc5 {
1742f005b44SIcenowy Zheng	regulator-always-on;
1752f005b44SIcenowy Zheng	regulator-min-microvolt = <1360000>;
1762f005b44SIcenowy Zheng	regulator-max-microvolt = <1360000>;
1772f005b44SIcenowy Zheng	regulator-name = "vcc-dram";
1782f005b44SIcenowy Zheng};
1792f005b44SIcenowy Zheng
1802f005b44SIcenowy Zheng&reg_dcdc6 {
1812f005b44SIcenowy Zheng	regulator-always-on;
1822f005b44SIcenowy Zheng	regulator-min-microvolt = <1100000>;
1832f005b44SIcenowy Zheng	regulator-max-microvolt = <1100000>;
1842f005b44SIcenowy Zheng	regulator-name = "vdd-sys";
1852f005b44SIcenowy Zheng};
1862f005b44SIcenowy Zheng
1872f005b44SIcenowy Zheng&reg_dldo1 {
1882f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
1892f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1902f005b44SIcenowy Zheng	regulator-name = "vcc-hdmi";
1912f005b44SIcenowy Zheng};
1922f005b44SIcenowy Zheng
1932f005b44SIcenowy Zheng&reg_dldo2 {
1942f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
1952f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1962f005b44SIcenowy Zheng	regulator-name = "vcc-mipi";
1972f005b44SIcenowy Zheng};
1982f005b44SIcenowy Zheng
1992f005b44SIcenowy Zheng&reg_dldo4 {
2002f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2012f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2022f005b44SIcenowy Zheng	regulator-name = "vcc-wifi";
2032f005b44SIcenowy Zheng};
2042f005b44SIcenowy Zheng
2052f005b44SIcenowy Zheng&reg_eldo1 {
2062f005b44SIcenowy Zheng	regulator-min-microvolt = <1800000>;
2072f005b44SIcenowy Zheng	regulator-max-microvolt = <1800000>;
2082f005b44SIcenowy Zheng	regulator-name = "cpvdd";
2092f005b44SIcenowy Zheng};
2102f005b44SIcenowy Zheng
2112f005b44SIcenowy Zheng&reg_fldo1 {
2122f005b44SIcenowy Zheng	regulator-min-microvolt = <1200000>;
2132f005b44SIcenowy Zheng	regulator-max-microvolt = <1200000>;
2142f005b44SIcenowy Zheng	regulator-name = "vcc-1v2-hsic";
2152f005b44SIcenowy Zheng};
2162f005b44SIcenowy Zheng
2172f005b44SIcenowy Zheng/*
2182f005b44SIcenowy Zheng * The A64 chip cannot work without this regulator off, although
2192f005b44SIcenowy Zheng * it seems to be only driving the AR100 core.
2202f005b44SIcenowy Zheng * Maybe we don't still know well about CPUs domain.
2212f005b44SIcenowy Zheng */
2222f005b44SIcenowy Zheng&reg_fldo2 {
2232f005b44SIcenowy Zheng	regulator-always-on;
2242f005b44SIcenowy Zheng	regulator-min-microvolt = <1100000>;
2252f005b44SIcenowy Zheng	regulator-max-microvolt = <1100000>;
2262f005b44SIcenowy Zheng	regulator-name = "vdd-cpus";
2272f005b44SIcenowy Zheng};
2282f005b44SIcenowy Zheng
2292f005b44SIcenowy Zheng&reg_rtc_ldo {
2302f005b44SIcenowy Zheng	regulator-name = "vcc-rtc";
2312f005b44SIcenowy Zheng};
2322f005b44SIcenowy Zheng
2332273aa16SAndreas Färber/* On Exp and Euler connectors */
234ac93c09cSIcenowy Zheng&uart0 {
235ac93c09cSIcenowy Zheng	pinctrl-names = "default";
236ac93c09cSIcenowy Zheng	pinctrl-0 = <&uart0_pins_a>;
237ac93c09cSIcenowy Zheng	status = "okay";
238ac93c09cSIcenowy Zheng};
239d49f9dbcSIcenowy Zheng
2402273aa16SAndreas Färber/* On Wifi/BT connector, with RTS/CTS */
2412273aa16SAndreas Färber&uart1 {
2422273aa16SAndreas Färber	pinctrl-names = "default";
2432273aa16SAndreas Färber	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
2442273aa16SAndreas Färber	status = "disabled";
2452273aa16SAndreas Färber};
2462273aa16SAndreas Färber
2472273aa16SAndreas Färber/* On Pi-2 connector */
2482273aa16SAndreas Färber&uart2 {
2492273aa16SAndreas Färber	pinctrl-names = "default";
2502273aa16SAndreas Färber	pinctrl-0 = <&uart2_pins>;
2512273aa16SAndreas Färber	status = "disabled";
2522273aa16SAndreas Färber};
2532273aa16SAndreas Färber
2542273aa16SAndreas Färber/* On Euler connector */
2552273aa16SAndreas Färber&uart3 {
2562273aa16SAndreas Färber	pinctrl-names = "default";
2572273aa16SAndreas Färber	pinctrl-0 = <&uart3_pins>;
2582273aa16SAndreas Färber	status = "disabled";
2592273aa16SAndreas Färber};
2602273aa16SAndreas Färber
2612273aa16SAndreas Färber/* On Euler connector, RTS/CTS optional */
2622273aa16SAndreas Färber&uart4 {
2632273aa16SAndreas Färber	pinctrl-names = "default";
2642273aa16SAndreas Färber	pinctrl-0 = <&uart4_pins>;
2652273aa16SAndreas Färber	status = "disabled";
2662273aa16SAndreas Färber};
2672273aa16SAndreas Färber
268f57e8384SIcenowy Zheng&usb_otg {
269f57e8384SIcenowy Zheng	dr_mode = "host";
270f57e8384SIcenowy Zheng	status = "okay";
271f57e8384SIcenowy Zheng};
272f57e8384SIcenowy Zheng
273d49f9dbcSIcenowy Zheng&usbphy {
274d49f9dbcSIcenowy Zheng	status = "okay";
275d49f9dbcSIcenowy Zheng};
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