1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 24e388608SAndre Przywara/* 34e388608SAndre Przywara * Copyright (c) 2016 ARM Ltd. 44e388608SAndre Przywara */ 54e388608SAndre Przywara 64e388608SAndre Przywara/dts-v1/; 74e388608SAndre Przywara 84e388608SAndre Przywara#include "sun50i-a64.dtsi" 94e388608SAndre Przywara 10ebe3ae29SAndre Przywara#include <dt-bindings/gpio/gpio.h> 11ebe3ae29SAndre Przywara 124e388608SAndre Przywara/ { 134e388608SAndre Przywara model = "Pine64"; 144e388608SAndre Przywara compatible = "pine64,pine64", "allwinner,sun50i-a64"; 154e388608SAndre Przywara 164e388608SAndre Przywara aliases { 1794f44288SCorentin Labbe ethernet0 = &emac; 184e388608SAndre Przywara serial0 = &uart0; 19226ab099SAndreas Färber serial1 = &uart1; 20226ab099SAndreas Färber serial2 = &uart2; 21226ab099SAndreas Färber serial3 = &uart3; 22226ab099SAndreas Färber serial4 = &uart4; 234e388608SAndre Przywara }; 244e388608SAndre Przywara 254e388608SAndre Przywara chosen { 264e388608SAndre Przywara stdout-path = "serial0:115200n8"; 274e388608SAndre Przywara }; 28f4e4453aSJagan Teki 29f4e4453aSJagan Teki hdmi-connector { 30f4e4453aSJagan Teki compatible = "hdmi-connector"; 31f4e4453aSJagan Teki type = "a"; 32f4e4453aSJagan Teki 33f4e4453aSJagan Teki port { 34f4e4453aSJagan Teki hdmi_con_in: endpoint { 35f4e4453aSJagan Teki remote-endpoint = <&hdmi_out_con>; 36f4e4453aSJagan Teki }; 37f4e4453aSJagan Teki }; 38f4e4453aSJagan Teki }; 39f4e4453aSJagan Teki}; 40f4e4453aSJagan Teki 41498c21f2SVasily Khoruzhick&codec { 42498c21f2SVasily Khoruzhick status = "okay"; 43498c21f2SVasily Khoruzhick}; 44498c21f2SVasily Khoruzhick 45498c21f2SVasily Khoruzhick&codec_analog { 4607de9094SChen-Yu Tsai cpvdd-supply = <®_eldo1>; 47498c21f2SVasily Khoruzhick status = "okay"; 48498c21f2SVasily Khoruzhick}; 49498c21f2SVasily Khoruzhick 50498c21f2SVasily Khoruzhick&dai { 51498c21f2SVasily Khoruzhick status = "okay"; 52498c21f2SVasily Khoruzhick}; 53498c21f2SVasily Khoruzhick 54f4e4453aSJagan Teki&de { 55f4e4453aSJagan Teki status = "okay"; 564e388608SAndre Przywara}; 574e388608SAndre Przywara 588543e620SIcenowy Zheng&ehci0 { 598543e620SIcenowy Zheng status = "okay"; 608543e620SIcenowy Zheng}; 618543e620SIcenowy Zheng 62d49f9dbcSIcenowy Zheng&ehci1 { 63d49f9dbcSIcenowy Zheng status = "okay"; 64d49f9dbcSIcenowy Zheng}; 65d49f9dbcSIcenowy Zheng 6694f44288SCorentin Labbe&emac { 6794f44288SCorentin Labbe pinctrl-names = "default"; 6894f44288SCorentin Labbe pinctrl-0 = <&rmii_pins>; 6994f44288SCorentin Labbe phy-mode = "rmii"; 7094f44288SCorentin Labbe phy-handle = <&ext_rmii_phy1>; 71bdfe4cebSIcenowy Zheng phy-supply = <®_dc1sw>; 7294f44288SCorentin Labbe status = "okay"; 7394f44288SCorentin Labbe 7494f44288SCorentin Labbe}; 7594f44288SCorentin Labbe 76f4e4453aSJagan Teki&hdmi { 77f4e4453aSJagan Teki hvcc-supply = <®_dldo1>; 78f4e4453aSJagan Teki status = "okay"; 79f4e4453aSJagan Teki}; 80f4e4453aSJagan Teki 81f4e4453aSJagan Teki&hdmi_out { 82f4e4453aSJagan Teki hdmi_out_con: endpoint { 83f4e4453aSJagan Teki remote-endpoint = <&hdmi_con_in>; 84f4e4453aSJagan Teki }; 85f4e4453aSJagan Teki}; 86f4e4453aSJagan Teki 874e388608SAndre Przywara&i2c1 { 884e388608SAndre Przywara status = "okay"; 894e388608SAndre Przywara}; 904e388608SAndre Przywara 914e388608SAndre Przywara&i2c1_pins { 924e388608SAndre Przywara bias-pull-up; 934e388608SAndre Przywara}; 94ac93c09cSIcenowy Zheng 9594f44288SCorentin Labbe&mdio { 9694f44288SCorentin Labbe ext_rmii_phy1: ethernet-phy@1 { 9794f44288SCorentin Labbe compatible = "ethernet-phy-ieee802.3-c22"; 9894f44288SCorentin Labbe reg = <1>; 9994f44288SCorentin Labbe }; 10094f44288SCorentin Labbe}; 10194f44288SCorentin Labbe 102ebe3ae29SAndre Przywara&mmc0 { 103ebe3ae29SAndre Przywara pinctrl-names = "default"; 104ebe3ae29SAndre Przywara pinctrl-0 = <&mmc0_pins>; 1053f241bfaSJagan Teki vmmc-supply = <®_dcdc1>; 106b75cb68dSTuomas Tynkkynen cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; 107ebe3ae29SAndre Przywara disable-wp; 108ebe3ae29SAndre Przywara bus-width = <4>; 109ebe3ae29SAndre Przywara status = "okay"; 110ebe3ae29SAndre Przywara}; 111ebe3ae29SAndre Przywara 1128543e620SIcenowy Zheng&ohci0 { 1138543e620SIcenowy Zheng status = "okay"; 1148543e620SIcenowy Zheng}; 1158543e620SIcenowy Zheng 116d49f9dbcSIcenowy Zheng&ohci1 { 117d49f9dbcSIcenowy Zheng status = "okay"; 118d49f9dbcSIcenowy Zheng}; 119d49f9dbcSIcenowy Zheng 1201b3010cdSIcenowy Zheng&r_rsb { 1211b3010cdSIcenowy Zheng status = "okay"; 1221b3010cdSIcenowy Zheng 1231b3010cdSIcenowy Zheng axp803: pmic@3a3 { 1241b3010cdSIcenowy Zheng compatible = "x-powers,axp803"; 1251b3010cdSIcenowy Zheng reg = <0x3a3>; 1261b3010cdSIcenowy Zheng interrupt-parent = <&r_intc>; 1271b3010cdSIcenowy Zheng interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 1281b3010cdSIcenowy Zheng }; 1291b3010cdSIcenowy Zheng}; 1301b3010cdSIcenowy Zheng 1312f005b44SIcenowy Zheng#include "axp803.dtsi" 1322f005b44SIcenowy Zheng 133a24270afSChen-Yu Tsai&ac_power_supply { 134a24270afSChen-Yu Tsai status = "okay"; 135a24270afSChen-Yu Tsai}; 136a24270afSChen-Yu Tsai 137a24270afSChen-Yu Tsai&battery_power_supply { 138a24270afSChen-Yu Tsai status = "okay"; 139a24270afSChen-Yu Tsai}; 140a24270afSChen-Yu Tsai 1412f005b44SIcenowy Zheng®_aldo2 { 1422f005b44SIcenowy Zheng regulator-always-on; 1432f005b44SIcenowy Zheng regulator-min-microvolt = <1800000>; 1442f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 1452f005b44SIcenowy Zheng regulator-name = "vcc-pl"; 1462f005b44SIcenowy Zheng}; 1472f005b44SIcenowy Zheng 1482f005b44SIcenowy Zheng®_aldo3 { 1492f005b44SIcenowy Zheng regulator-always-on; 1502f005b44SIcenowy Zheng regulator-min-microvolt = <3000000>; 1512f005b44SIcenowy Zheng regulator-max-microvolt = <3000000>; 1522f005b44SIcenowy Zheng regulator-name = "vcc-pll-avcc"; 1532f005b44SIcenowy Zheng}; 1542f005b44SIcenowy Zheng 1552f005b44SIcenowy Zheng®_dc1sw { 1562f005b44SIcenowy Zheng regulator-name = "vcc-phy"; 1572f005b44SIcenowy Zheng}; 1582f005b44SIcenowy Zheng 1592f005b44SIcenowy Zheng®_dcdc1 { 1602f005b44SIcenowy Zheng regulator-always-on; 1612f005b44SIcenowy Zheng regulator-min-microvolt = <3300000>; 1622f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 1632f005b44SIcenowy Zheng regulator-name = "vcc-3v3"; 1642f005b44SIcenowy Zheng}; 1652f005b44SIcenowy Zheng 1662f005b44SIcenowy Zheng®_dcdc2 { 1672f005b44SIcenowy Zheng regulator-always-on; 1682f005b44SIcenowy Zheng regulator-min-microvolt = <1040000>; 1692f005b44SIcenowy Zheng regulator-max-microvolt = <1300000>; 1702f005b44SIcenowy Zheng regulator-name = "vdd-cpux"; 1712f005b44SIcenowy Zheng}; 1722f005b44SIcenowy Zheng 1732f005b44SIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */ 1742f005b44SIcenowy Zheng 1752f005b44SIcenowy Zheng/* 1762f005b44SIcenowy Zheng * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can 1772f005b44SIcenowy Zheng * work at 1.35V with less power consumption. 1782f005b44SIcenowy Zheng * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead. 1792f005b44SIcenowy Zheng */ 1802f005b44SIcenowy Zheng®_dcdc5 { 1812f005b44SIcenowy Zheng regulator-always-on; 1822f005b44SIcenowy Zheng regulator-min-microvolt = <1360000>; 1832f005b44SIcenowy Zheng regulator-max-microvolt = <1360000>; 1842f005b44SIcenowy Zheng regulator-name = "vcc-dram"; 1852f005b44SIcenowy Zheng}; 1862f005b44SIcenowy Zheng 1872f005b44SIcenowy Zheng®_dcdc6 { 1882f005b44SIcenowy Zheng regulator-always-on; 1892f005b44SIcenowy Zheng regulator-min-microvolt = <1100000>; 1902f005b44SIcenowy Zheng regulator-max-microvolt = <1100000>; 1912f005b44SIcenowy Zheng regulator-name = "vdd-sys"; 1922f005b44SIcenowy Zheng}; 1932f005b44SIcenowy Zheng 1942f005b44SIcenowy Zheng®_dldo1 { 1952f005b44SIcenowy Zheng regulator-min-microvolt = <3300000>; 1962f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 1972f005b44SIcenowy Zheng regulator-name = "vcc-hdmi"; 1982f005b44SIcenowy Zheng}; 1992f005b44SIcenowy Zheng 2002f005b44SIcenowy Zheng®_dldo2 { 2012f005b44SIcenowy Zheng regulator-min-microvolt = <3300000>; 2022f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 2032f005b44SIcenowy Zheng regulator-name = "vcc-mipi"; 2042f005b44SIcenowy Zheng}; 2052f005b44SIcenowy Zheng 2062f005b44SIcenowy Zheng®_dldo4 { 2072f005b44SIcenowy Zheng regulator-min-microvolt = <3300000>; 2082f005b44SIcenowy Zheng regulator-max-microvolt = <3300000>; 2092f005b44SIcenowy Zheng regulator-name = "vcc-wifi"; 2102f005b44SIcenowy Zheng}; 2112f005b44SIcenowy Zheng 2122f005b44SIcenowy Zheng®_eldo1 { 2132f005b44SIcenowy Zheng regulator-min-microvolt = <1800000>; 2142f005b44SIcenowy Zheng regulator-max-microvolt = <1800000>; 2152f005b44SIcenowy Zheng regulator-name = "cpvdd"; 2162f005b44SIcenowy Zheng}; 2172f005b44SIcenowy Zheng 2182f005b44SIcenowy Zheng®_fldo1 { 2192f005b44SIcenowy Zheng regulator-min-microvolt = <1200000>; 2202f005b44SIcenowy Zheng regulator-max-microvolt = <1200000>; 2212f005b44SIcenowy Zheng regulator-name = "vcc-1v2-hsic"; 2222f005b44SIcenowy Zheng}; 2232f005b44SIcenowy Zheng 2242f005b44SIcenowy Zheng/* 2252f005b44SIcenowy Zheng * The A64 chip cannot work without this regulator off, although 2262f005b44SIcenowy Zheng * it seems to be only driving the AR100 core. 2272f005b44SIcenowy Zheng * Maybe we don't still know well about CPUs domain. 2282f005b44SIcenowy Zheng */ 2292f005b44SIcenowy Zheng®_fldo2 { 2302f005b44SIcenowy Zheng regulator-always-on; 2312f005b44SIcenowy Zheng regulator-min-microvolt = <1100000>; 2322f005b44SIcenowy Zheng regulator-max-microvolt = <1100000>; 2332f005b44SIcenowy Zheng regulator-name = "vdd-cpus"; 2342f005b44SIcenowy Zheng}; 2352f005b44SIcenowy Zheng 2362f005b44SIcenowy Zheng®_rtc_ldo { 2372f005b44SIcenowy Zheng regulator-name = "vcc-rtc"; 2382f005b44SIcenowy Zheng}; 2392f005b44SIcenowy Zheng 2405cbef9f9SIcenowy Zheng&simplefb_hdmi { 2415cbef9f9SIcenowy Zheng vcc-hdmi-supply = <®_dldo1>; 2425cbef9f9SIcenowy Zheng}; 2435cbef9f9SIcenowy Zheng 244498c21f2SVasily Khoruzhick&sound { 245498c21f2SVasily Khoruzhick simple-audio-card,aux-devs = <&codec_analog>; 246498c21f2SVasily Khoruzhick simple-audio-card,widgets = "Microphone", "Microphone Jack", 247498c21f2SVasily Khoruzhick "Headphone", "Headphone Jack"; 248498c21f2SVasily Khoruzhick simple-audio-card,routing = 249498c21f2SVasily Khoruzhick "Left DAC", "AIF1 Slot 0 Left", 250498c21f2SVasily Khoruzhick "Right DAC", "AIF1 Slot 0 Right", 251498c21f2SVasily Khoruzhick "Headphone Jack", "HP", 252498c21f2SVasily Khoruzhick "AIF1 Slot 0 Left ADC", "Left ADC", 253498c21f2SVasily Khoruzhick "AIF1 Slot 0 Right ADC", "Right ADC", 254498c21f2SVasily Khoruzhick "MIC2", "Microphone Jack"; 255498c21f2SVasily Khoruzhick status = "okay"; 256498c21f2SVasily Khoruzhick}; 257498c21f2SVasily Khoruzhick 258fcf7e5feSMarcus Cooper/* On Euler connector */ 259fcf7e5feSMarcus Cooper&spdif { 260fcf7e5feSMarcus Cooper status = "disabled"; 261fcf7e5feSMarcus Cooper}; 262fcf7e5feSMarcus Cooper 2632273aa16SAndreas Färber/* On Exp and Euler connectors */ 264ac93c09cSIcenowy Zheng&uart0 { 265ac93c09cSIcenowy Zheng pinctrl-names = "default"; 266d91ebb95SChen-Yu Tsai pinctrl-0 = <&uart0_pb_pins>; 267ac93c09cSIcenowy Zheng status = "okay"; 268ac93c09cSIcenowy Zheng}; 269d49f9dbcSIcenowy Zheng 2702273aa16SAndreas Färber/* On Wifi/BT connector, with RTS/CTS */ 2712273aa16SAndreas Färber&uart1 { 2722273aa16SAndreas Färber pinctrl-names = "default"; 2732273aa16SAndreas Färber pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; 2742273aa16SAndreas Färber status = "disabled"; 2752273aa16SAndreas Färber}; 2762273aa16SAndreas Färber 2772273aa16SAndreas Färber/* On Pi-2 connector */ 2782273aa16SAndreas Färber&uart2 { 2792273aa16SAndreas Färber pinctrl-names = "default"; 2802273aa16SAndreas Färber pinctrl-0 = <&uart2_pins>; 2812273aa16SAndreas Färber status = "disabled"; 2822273aa16SAndreas Färber}; 2832273aa16SAndreas Färber 2842273aa16SAndreas Färber/* On Euler connector */ 2852273aa16SAndreas Färber&uart3 { 2862273aa16SAndreas Färber pinctrl-names = "default"; 2872273aa16SAndreas Färber pinctrl-0 = <&uart3_pins>; 2882273aa16SAndreas Färber status = "disabled"; 2892273aa16SAndreas Färber}; 2902273aa16SAndreas Färber 2912273aa16SAndreas Färber/* On Euler connector, RTS/CTS optional */ 2922273aa16SAndreas Färber&uart4 { 2932273aa16SAndreas Färber pinctrl-names = "default"; 2942273aa16SAndreas Färber pinctrl-0 = <&uart4_pins>; 2952273aa16SAndreas Färber status = "disabled"; 2962273aa16SAndreas Färber}; 2972273aa16SAndreas Färber 298f57e8384SIcenowy Zheng&usb_otg { 299f57e8384SIcenowy Zheng dr_mode = "host"; 300f57e8384SIcenowy Zheng status = "okay"; 301f57e8384SIcenowy Zheng}; 302f57e8384SIcenowy Zheng 303d49f9dbcSIcenowy Zheng&usbphy { 304d49f9dbcSIcenowy Zheng status = "okay"; 305d49f9dbcSIcenowy Zheng}; 306