14e388608SAndre Przywara/*
24e388608SAndre Przywara * Copyright (c) 2016 ARM Ltd.
34e388608SAndre Przywara *
44e388608SAndre Przywara * This file is dual-licensed: you can use it either under the terms
54e388608SAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual
64e388608SAndre Przywara * licensing only applies to this file, and not this project as a
74e388608SAndre Przywara * whole.
84e388608SAndre Przywara *
94e388608SAndre Przywara *  a) This library is free software; you can redistribute it and/or
104e388608SAndre Przywara *     modify it under the terms of the GNU General Public License as
114e388608SAndre Przywara *     published by the Free Software Foundation; either version 2 of the
124e388608SAndre Przywara *     License, or (at your option) any later version.
134e388608SAndre Przywara *
144e388608SAndre Przywara *     This library is distributed in the hope that it will be useful,
154e388608SAndre Przywara *     but WITHOUT ANY WARRANTY; without even the implied warranty of
164e388608SAndre Przywara *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
174e388608SAndre Przywara *     GNU General Public License for more details.
184e388608SAndre Przywara *
194e388608SAndre Przywara * Or, alternatively,
204e388608SAndre Przywara *
214e388608SAndre Przywara *  b) Permission is hereby granted, free of charge, to any person
224e388608SAndre Przywara *     obtaining a copy of this software and associated documentation
234e388608SAndre Przywara *     files (the "Software"), to deal in the Software without
244e388608SAndre Przywara *     restriction, including without limitation the rights to use,
254e388608SAndre Przywara *     copy, modify, merge, publish, distribute, sublicense, and/or
264e388608SAndre Przywara *     sell copies of the Software, and to permit persons to whom the
274e388608SAndre Przywara *     Software is furnished to do so, subject to the following
284e388608SAndre Przywara *     conditions:
294e388608SAndre Przywara *
304e388608SAndre Przywara *     The above copyright notice and this permission notice shall be
314e388608SAndre Przywara *     included in all copies or substantial portions of the Software.
324e388608SAndre Przywara *
334e388608SAndre Przywara *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
344e388608SAndre Przywara *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
354e388608SAndre Przywara *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
364e388608SAndre Przywara *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
374e388608SAndre Przywara *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
384e388608SAndre Przywara *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
394e388608SAndre Przywara *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
404e388608SAndre Przywara *     OTHER DEALINGS IN THE SOFTWARE.
414e388608SAndre Przywara */
424e388608SAndre Przywara
434e388608SAndre Przywara/dts-v1/;
444e388608SAndre Przywara
454e388608SAndre Przywara#include "sun50i-a64.dtsi"
464e388608SAndre Przywara
47ebe3ae29SAndre Przywara#include <dt-bindings/gpio/gpio.h>
48ebe3ae29SAndre Przywara
494e388608SAndre Przywara/ {
504e388608SAndre Przywara	model = "Pine64";
514e388608SAndre Przywara	compatible = "pine64,pine64", "allwinner,sun50i-a64";
524e388608SAndre Przywara
534e388608SAndre Przywara	aliases {
5494f44288SCorentin Labbe		ethernet0 = &emac;
554e388608SAndre Przywara		serial0 = &uart0;
56226ab099SAndreas Färber		serial1 = &uart1;
57226ab099SAndreas Färber		serial2 = &uart2;
58226ab099SAndreas Färber		serial3 = &uart3;
59226ab099SAndreas Färber		serial4 = &uart4;
604e388608SAndre Przywara	};
614e388608SAndre Przywara
624e388608SAndre Przywara	chosen {
634e388608SAndre Przywara		stdout-path = "serial0:115200n8";
644e388608SAndre Przywara	};
65f4e4453aSJagan Teki
66f4e4453aSJagan Teki	hdmi-connector {
67f4e4453aSJagan Teki		compatible = "hdmi-connector";
68f4e4453aSJagan Teki		type = "a";
69f4e4453aSJagan Teki
70f4e4453aSJagan Teki		port {
71f4e4453aSJagan Teki			hdmi_con_in: endpoint {
72f4e4453aSJagan Teki				remote-endpoint = <&hdmi_out_con>;
73f4e4453aSJagan Teki			};
74f4e4453aSJagan Teki		};
75f4e4453aSJagan Teki	};
76f4e4453aSJagan Teki};
77f4e4453aSJagan Teki
78498c21f2SVasily Khoruzhick&codec {
79498c21f2SVasily Khoruzhick	status = "okay";
80498c21f2SVasily Khoruzhick};
81498c21f2SVasily Khoruzhick
82498c21f2SVasily Khoruzhick&codec_analog {
8307de9094SChen-Yu Tsai	cpvdd-supply = <&reg_eldo1>;
84498c21f2SVasily Khoruzhick	status = "okay";
85498c21f2SVasily Khoruzhick};
86498c21f2SVasily Khoruzhick
87498c21f2SVasily Khoruzhick&dai {
88498c21f2SVasily Khoruzhick	status = "okay";
89498c21f2SVasily Khoruzhick};
90498c21f2SVasily Khoruzhick
91f4e4453aSJagan Teki&de {
92f4e4453aSJagan Teki	status = "okay";
934e388608SAndre Przywara};
944e388608SAndre Przywara
958543e620SIcenowy Zheng&ehci0 {
968543e620SIcenowy Zheng	status = "okay";
978543e620SIcenowy Zheng};
988543e620SIcenowy Zheng
99d49f9dbcSIcenowy Zheng&ehci1 {
100d49f9dbcSIcenowy Zheng	status = "okay";
101d49f9dbcSIcenowy Zheng};
102d49f9dbcSIcenowy Zheng
10394f44288SCorentin Labbe&emac {
10494f44288SCorentin Labbe	pinctrl-names = "default";
10594f44288SCorentin Labbe	pinctrl-0 = <&rmii_pins>;
10694f44288SCorentin Labbe	phy-mode = "rmii";
10794f44288SCorentin Labbe	phy-handle = <&ext_rmii_phy1>;
108bdfe4cebSIcenowy Zheng	phy-supply = <&reg_dc1sw>;
10994f44288SCorentin Labbe	status = "okay";
11094f44288SCorentin Labbe
11194f44288SCorentin Labbe};
11294f44288SCorentin Labbe
113f4e4453aSJagan Teki&hdmi {
114f4e4453aSJagan Teki	hvcc-supply = <&reg_dldo1>;
115f4e4453aSJagan Teki	status = "okay";
116f4e4453aSJagan Teki};
117f4e4453aSJagan Teki
118f4e4453aSJagan Teki&hdmi_out {
119f4e4453aSJagan Teki	hdmi_out_con: endpoint {
120f4e4453aSJagan Teki		remote-endpoint = <&hdmi_con_in>;
121f4e4453aSJagan Teki	};
122f4e4453aSJagan Teki};
123f4e4453aSJagan Teki
1244e388608SAndre Przywara&i2c1 {
1254e388608SAndre Przywara	pinctrl-names = "default";
1264e388608SAndre Przywara	pinctrl-0 = <&i2c1_pins>;
1274e388608SAndre Przywara	status = "okay";
1284e388608SAndre Przywara};
1294e388608SAndre Przywara
1304e388608SAndre Przywara&i2c1_pins {
1314e388608SAndre Przywara	bias-pull-up;
1324e388608SAndre Przywara};
133ac93c09cSIcenowy Zheng
13494f44288SCorentin Labbe&mdio {
13594f44288SCorentin Labbe	ext_rmii_phy1: ethernet-phy@1 {
13694f44288SCorentin Labbe		compatible = "ethernet-phy-ieee802.3-c22";
13794f44288SCorentin Labbe		reg = <1>;
13894f44288SCorentin Labbe	};
13994f44288SCorentin Labbe};
14094f44288SCorentin Labbe
141ebe3ae29SAndre Przywara&mmc0 {
142ebe3ae29SAndre Przywara	pinctrl-names = "default";
143ebe3ae29SAndre Przywara	pinctrl-0 = <&mmc0_pins>;
1443f241bfaSJagan Teki	vmmc-supply = <&reg_dcdc1>;
145b75cb68dSTuomas Tynkkynen	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
146ebe3ae29SAndre Przywara	disable-wp;
147ebe3ae29SAndre Przywara	bus-width = <4>;
148ebe3ae29SAndre Przywara	status = "okay";
149ebe3ae29SAndre Przywara};
150ebe3ae29SAndre Przywara
1518543e620SIcenowy Zheng&ohci0 {
1528543e620SIcenowy Zheng	status = "okay";
1538543e620SIcenowy Zheng};
1548543e620SIcenowy Zheng
155d49f9dbcSIcenowy Zheng&ohci1 {
156d49f9dbcSIcenowy Zheng	status = "okay";
157d49f9dbcSIcenowy Zheng};
158d49f9dbcSIcenowy Zheng
1591b3010cdSIcenowy Zheng&r_rsb {
1601b3010cdSIcenowy Zheng	status = "okay";
1611b3010cdSIcenowy Zheng
1621b3010cdSIcenowy Zheng	axp803: pmic@3a3 {
1631b3010cdSIcenowy Zheng		compatible = "x-powers,axp803";
1641b3010cdSIcenowy Zheng		reg = <0x3a3>;
1651b3010cdSIcenowy Zheng		interrupt-parent = <&r_intc>;
1661b3010cdSIcenowy Zheng		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
1671b3010cdSIcenowy Zheng	};
1681b3010cdSIcenowy Zheng};
1691b3010cdSIcenowy Zheng
1702f005b44SIcenowy Zheng#include "axp803.dtsi"
1712f005b44SIcenowy Zheng
172a24270afSChen-Yu Tsai&ac_power_supply {
173a24270afSChen-Yu Tsai	status = "okay";
174a24270afSChen-Yu Tsai};
175a24270afSChen-Yu Tsai
176a24270afSChen-Yu Tsai&battery_power_supply {
177a24270afSChen-Yu Tsai	status = "okay";
178a24270afSChen-Yu Tsai};
179a24270afSChen-Yu Tsai
1802f005b44SIcenowy Zheng&reg_aldo2 {
1812f005b44SIcenowy Zheng	regulator-always-on;
1822f005b44SIcenowy Zheng	regulator-min-microvolt = <1800000>;
1832f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1842f005b44SIcenowy Zheng	regulator-name = "vcc-pl";
1852f005b44SIcenowy Zheng};
1862f005b44SIcenowy Zheng
1872f005b44SIcenowy Zheng&reg_aldo3 {
1882f005b44SIcenowy Zheng	regulator-always-on;
1892f005b44SIcenowy Zheng	regulator-min-microvolt = <3000000>;
1902f005b44SIcenowy Zheng	regulator-max-microvolt = <3000000>;
1912f005b44SIcenowy Zheng	regulator-name = "vcc-pll-avcc";
1922f005b44SIcenowy Zheng};
1932f005b44SIcenowy Zheng
1942f005b44SIcenowy Zheng&reg_dc1sw {
1952f005b44SIcenowy Zheng	regulator-name = "vcc-phy";
1962f005b44SIcenowy Zheng};
1972f005b44SIcenowy Zheng
1982f005b44SIcenowy Zheng&reg_dcdc1 {
1992f005b44SIcenowy Zheng	regulator-always-on;
2002f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2012f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2022f005b44SIcenowy Zheng	regulator-name = "vcc-3v3";
2032f005b44SIcenowy Zheng};
2042f005b44SIcenowy Zheng
2052f005b44SIcenowy Zheng&reg_dcdc2 {
2062f005b44SIcenowy Zheng	regulator-always-on;
2072f005b44SIcenowy Zheng	regulator-min-microvolt = <1040000>;
2082f005b44SIcenowy Zheng	regulator-max-microvolt = <1300000>;
2092f005b44SIcenowy Zheng	regulator-name = "vdd-cpux";
2102f005b44SIcenowy Zheng};
2112f005b44SIcenowy Zheng
2122f005b44SIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */
2132f005b44SIcenowy Zheng
2142f005b44SIcenowy Zheng/*
2152f005b44SIcenowy Zheng * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
2162f005b44SIcenowy Zheng * work at 1.35V with less power consumption.
2172f005b44SIcenowy Zheng * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead.
2182f005b44SIcenowy Zheng */
2192f005b44SIcenowy Zheng&reg_dcdc5 {
2202f005b44SIcenowy Zheng	regulator-always-on;
2212f005b44SIcenowy Zheng	regulator-min-microvolt = <1360000>;
2222f005b44SIcenowy Zheng	regulator-max-microvolt = <1360000>;
2232f005b44SIcenowy Zheng	regulator-name = "vcc-dram";
2242f005b44SIcenowy Zheng};
2252f005b44SIcenowy Zheng
2262f005b44SIcenowy Zheng&reg_dcdc6 {
2272f005b44SIcenowy Zheng	regulator-always-on;
2282f005b44SIcenowy Zheng	regulator-min-microvolt = <1100000>;
2292f005b44SIcenowy Zheng	regulator-max-microvolt = <1100000>;
2302f005b44SIcenowy Zheng	regulator-name = "vdd-sys";
2312f005b44SIcenowy Zheng};
2322f005b44SIcenowy Zheng
2332f005b44SIcenowy Zheng&reg_dldo1 {
2342f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2352f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2362f005b44SIcenowy Zheng	regulator-name = "vcc-hdmi";
2372f005b44SIcenowy Zheng};
2382f005b44SIcenowy Zheng
2392f005b44SIcenowy Zheng&reg_dldo2 {
2402f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2412f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2422f005b44SIcenowy Zheng	regulator-name = "vcc-mipi";
2432f005b44SIcenowy Zheng};
2442f005b44SIcenowy Zheng
2452f005b44SIcenowy Zheng&reg_dldo4 {
2462f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2472f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2482f005b44SIcenowy Zheng	regulator-name = "vcc-wifi";
2492f005b44SIcenowy Zheng};
2502f005b44SIcenowy Zheng
2512f005b44SIcenowy Zheng&reg_eldo1 {
2522f005b44SIcenowy Zheng	regulator-min-microvolt = <1800000>;
2532f005b44SIcenowy Zheng	regulator-max-microvolt = <1800000>;
2542f005b44SIcenowy Zheng	regulator-name = "cpvdd";
2552f005b44SIcenowy Zheng};
2562f005b44SIcenowy Zheng
2572f005b44SIcenowy Zheng&reg_fldo1 {
2582f005b44SIcenowy Zheng	regulator-min-microvolt = <1200000>;
2592f005b44SIcenowy Zheng	regulator-max-microvolt = <1200000>;
2602f005b44SIcenowy Zheng	regulator-name = "vcc-1v2-hsic";
2612f005b44SIcenowy Zheng};
2622f005b44SIcenowy Zheng
2632f005b44SIcenowy Zheng/*
2642f005b44SIcenowy Zheng * The A64 chip cannot work without this regulator off, although
2652f005b44SIcenowy Zheng * it seems to be only driving the AR100 core.
2662f005b44SIcenowy Zheng * Maybe we don't still know well about CPUs domain.
2672f005b44SIcenowy Zheng */
2682f005b44SIcenowy Zheng&reg_fldo2 {
2692f005b44SIcenowy Zheng	regulator-always-on;
2702f005b44SIcenowy Zheng	regulator-min-microvolt = <1100000>;
2712f005b44SIcenowy Zheng	regulator-max-microvolt = <1100000>;
2722f005b44SIcenowy Zheng	regulator-name = "vdd-cpus";
2732f005b44SIcenowy Zheng};
2742f005b44SIcenowy Zheng
2752f005b44SIcenowy Zheng&reg_rtc_ldo {
2762f005b44SIcenowy Zheng	regulator-name = "vcc-rtc";
2772f005b44SIcenowy Zheng};
2782f005b44SIcenowy Zheng
2795cbef9f9SIcenowy Zheng&simplefb_hdmi {
2805cbef9f9SIcenowy Zheng	vcc-hdmi-supply = <&reg_dldo1>;
2815cbef9f9SIcenowy Zheng};
2825cbef9f9SIcenowy Zheng
283498c21f2SVasily Khoruzhick&sound {
284498c21f2SVasily Khoruzhick	simple-audio-card,aux-devs = <&codec_analog>;
285498c21f2SVasily Khoruzhick	simple-audio-card,widgets = "Microphone", "Microphone Jack",
286498c21f2SVasily Khoruzhick				    "Headphone", "Headphone Jack";
287498c21f2SVasily Khoruzhick	simple-audio-card,routing =
288498c21f2SVasily Khoruzhick			"Left DAC", "AIF1 Slot 0 Left",
289498c21f2SVasily Khoruzhick			"Right DAC", "AIF1 Slot 0 Right",
290498c21f2SVasily Khoruzhick			"Headphone Jack", "HP",
291498c21f2SVasily Khoruzhick			"AIF1 Slot 0 Left ADC", "Left ADC",
292498c21f2SVasily Khoruzhick			"AIF1 Slot 0 Right ADC", "Right ADC",
293498c21f2SVasily Khoruzhick			"MIC2", "Microphone Jack";
294498c21f2SVasily Khoruzhick	status = "okay";
295498c21f2SVasily Khoruzhick};
296498c21f2SVasily Khoruzhick
297fcf7e5feSMarcus Cooper/* On Euler connector */
298fcf7e5feSMarcus Cooper&spdif {
299fcf7e5feSMarcus Cooper	status = "disabled";
300fcf7e5feSMarcus Cooper};
301fcf7e5feSMarcus Cooper
3022273aa16SAndreas Färber/* On Exp and Euler connectors */
303ac93c09cSIcenowy Zheng&uart0 {
304ac93c09cSIcenowy Zheng	pinctrl-names = "default";
305d91ebb95SChen-Yu Tsai	pinctrl-0 = <&uart0_pb_pins>;
306ac93c09cSIcenowy Zheng	status = "okay";
307ac93c09cSIcenowy Zheng};
308d49f9dbcSIcenowy Zheng
3092273aa16SAndreas Färber/* On Wifi/BT connector, with RTS/CTS */
3102273aa16SAndreas Färber&uart1 {
3112273aa16SAndreas Färber	pinctrl-names = "default";
3122273aa16SAndreas Färber	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
3132273aa16SAndreas Färber	status = "disabled";
3142273aa16SAndreas Färber};
3152273aa16SAndreas Färber
3162273aa16SAndreas Färber/* On Pi-2 connector */
3172273aa16SAndreas Färber&uart2 {
3182273aa16SAndreas Färber	pinctrl-names = "default";
3192273aa16SAndreas Färber	pinctrl-0 = <&uart2_pins>;
3202273aa16SAndreas Färber	status = "disabled";
3212273aa16SAndreas Färber};
3222273aa16SAndreas Färber
3232273aa16SAndreas Färber/* On Euler connector */
3242273aa16SAndreas Färber&uart3 {
3252273aa16SAndreas Färber	pinctrl-names = "default";
3262273aa16SAndreas Färber	pinctrl-0 = <&uart3_pins>;
3272273aa16SAndreas Färber	status = "disabled";
3282273aa16SAndreas Färber};
3292273aa16SAndreas Färber
3302273aa16SAndreas Färber/* On Euler connector, RTS/CTS optional */
3312273aa16SAndreas Färber&uart4 {
3322273aa16SAndreas Färber	pinctrl-names = "default";
3332273aa16SAndreas Färber	pinctrl-0 = <&uart4_pins>;
3342273aa16SAndreas Färber	status = "disabled";
3352273aa16SAndreas Färber};
3362273aa16SAndreas Färber
337f57e8384SIcenowy Zheng&usb_otg {
338f57e8384SIcenowy Zheng	dr_mode = "host";
339f57e8384SIcenowy Zheng	status = "okay";
340f57e8384SIcenowy Zheng};
341f57e8384SIcenowy Zheng
342d49f9dbcSIcenowy Zheng&usbphy {
343d49f9dbcSIcenowy Zheng	status = "okay";
344d49f9dbcSIcenowy Zheng};
345