1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2cabbaed7SClément Péron// Copyright (c) 2016 ARM Ltd.
34e388608SAndre Przywara
44e388608SAndre Przywara/dts-v1/;
54e388608SAndre Przywara
64e388608SAndre Przywara#include "sun50i-a64.dtsi"
7ac904843SVasily Khoruzhick#include "sun50i-a64-cpu-opp.dtsi"
84e388608SAndre Przywara
9ebe3ae29SAndre Przywara#include <dt-bindings/gpio/gpio.h>
10ebe3ae29SAndre Przywara
114e388608SAndre Przywara/ {
124e388608SAndre Przywara	model = "Pine64";
134e388608SAndre Przywara	compatible = "pine64,pine64", "allwinner,sun50i-a64";
144e388608SAndre Przywara
154e388608SAndre Przywara	aliases {
1694f44288SCorentin Labbe		ethernet0 = &emac;
174e388608SAndre Przywara		serial0 = &uart0;
18226ab099SAndreas Färber		serial1 = &uart1;
19226ab099SAndreas Färber		serial2 = &uart2;
20226ab099SAndreas Färber		serial3 = &uart3;
21226ab099SAndreas Färber		serial4 = &uart4;
224e388608SAndre Przywara	};
234e388608SAndre Przywara
244e388608SAndre Przywara	chosen {
254e388608SAndre Przywara		stdout-path = "serial0:115200n8";
264e388608SAndre Przywara	};
27f4e4453aSJagan Teki
28f4e4453aSJagan Teki	hdmi-connector {
29f4e4453aSJagan Teki		compatible = "hdmi-connector";
30f4e4453aSJagan Teki		type = "a";
31f4e4453aSJagan Teki
32f4e4453aSJagan Teki		port {
33f4e4453aSJagan Teki			hdmi_con_in: endpoint {
34f4e4453aSJagan Teki				remote-endpoint = <&hdmi_out_con>;
35f4e4453aSJagan Teki			};
36f4e4453aSJagan Teki		};
37f4e4453aSJagan Teki	};
38f4e4453aSJagan Teki};
39f4e4453aSJagan Teki
40498c21f2SVasily Khoruzhick&codec {
41498c21f2SVasily Khoruzhick	status = "okay";
42498c21f2SVasily Khoruzhick};
43498c21f2SVasily Khoruzhick
44498c21f2SVasily Khoruzhick&codec_analog {
4507de9094SChen-Yu Tsai	cpvdd-supply = <&reg_eldo1>;
46498c21f2SVasily Khoruzhick	status = "okay";
47498c21f2SVasily Khoruzhick};
48498c21f2SVasily Khoruzhick
49ac904843SVasily Khoruzhick&cpu0 {
50ac904843SVasily Khoruzhick	cpu-supply = <&reg_dcdc2>;
51ac904843SVasily Khoruzhick};
52ac904843SVasily Khoruzhick
53ac904843SVasily Khoruzhick&cpu1 {
54ac904843SVasily Khoruzhick	cpu-supply = <&reg_dcdc2>;
55ac904843SVasily Khoruzhick};
56ac904843SVasily Khoruzhick
57ac904843SVasily Khoruzhick&cpu2 {
58ac904843SVasily Khoruzhick	cpu-supply = <&reg_dcdc2>;
59ac904843SVasily Khoruzhick};
60ac904843SVasily Khoruzhick
61ac904843SVasily Khoruzhick&cpu3 {
62ac904843SVasily Khoruzhick	cpu-supply = <&reg_dcdc2>;
63ac904843SVasily Khoruzhick};
64ac904843SVasily Khoruzhick
65498c21f2SVasily Khoruzhick&dai {
66498c21f2SVasily Khoruzhick	status = "okay";
67498c21f2SVasily Khoruzhick};
68498c21f2SVasily Khoruzhick
69f4e4453aSJagan Teki&de {
70f4e4453aSJagan Teki	status = "okay";
714e388608SAndre Przywara};
724e388608SAndre Przywara
738543e620SIcenowy Zheng&ehci0 {
748543e620SIcenowy Zheng	status = "okay";
758543e620SIcenowy Zheng};
768543e620SIcenowy Zheng
77d49f9dbcSIcenowy Zheng&ehci1 {
78d49f9dbcSIcenowy Zheng	status = "okay";
79d49f9dbcSIcenowy Zheng};
80d49f9dbcSIcenowy Zheng
8194f44288SCorentin Labbe&emac {
8294f44288SCorentin Labbe	pinctrl-names = "default";
8394f44288SCorentin Labbe	pinctrl-0 = <&rmii_pins>;
8494f44288SCorentin Labbe	phy-mode = "rmii";
8594f44288SCorentin Labbe	phy-handle = <&ext_rmii_phy1>;
86bdfe4cebSIcenowy Zheng	phy-supply = <&reg_dc1sw>;
8794f44288SCorentin Labbe	status = "okay";
8894f44288SCorentin Labbe
8994f44288SCorentin Labbe};
9094f44288SCorentin Labbe
91f4e4453aSJagan Teki&hdmi {
92f4e4453aSJagan Teki	hvcc-supply = <&reg_dldo1>;
93f4e4453aSJagan Teki	status = "okay";
94f4e4453aSJagan Teki};
95f4e4453aSJagan Teki
96f4e4453aSJagan Teki&hdmi_out {
97f4e4453aSJagan Teki	hdmi_out_con: endpoint {
98f4e4453aSJagan Teki		remote-endpoint = <&hdmi_con_in>;
99f4e4453aSJagan Teki	};
100f4e4453aSJagan Teki};
101f4e4453aSJagan Teki
1024e388608SAndre Przywara&i2c1 {
1034e388608SAndre Przywara	status = "okay";
1044e388608SAndre Przywara};
1054e388608SAndre Przywara
1064e388608SAndre Przywara&i2c1_pins {
1074e388608SAndre Przywara	bias-pull-up;
1084e388608SAndre Przywara};
109ac93c09cSIcenowy Zheng
11094f44288SCorentin Labbe&mdio {
11194f44288SCorentin Labbe	ext_rmii_phy1: ethernet-phy@1 {
11294f44288SCorentin Labbe		compatible = "ethernet-phy-ieee802.3-c22";
11394f44288SCorentin Labbe		reg = <1>;
11494f44288SCorentin Labbe	};
11594f44288SCorentin Labbe};
11694f44288SCorentin Labbe
117ebe3ae29SAndre Przywara&mmc0 {
118ebe3ae29SAndre Przywara	pinctrl-names = "default";
119ebe3ae29SAndre Przywara	pinctrl-0 = <&mmc0_pins>;
1203f241bfaSJagan Teki	vmmc-supply = <&reg_dcdc1>;
121b75cb68dSTuomas Tynkkynen	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
122ebe3ae29SAndre Przywara	disable-wp;
123ebe3ae29SAndre Przywara	bus-width = <4>;
124ebe3ae29SAndre Przywara	status = "okay";
125ebe3ae29SAndre Przywara};
126ebe3ae29SAndre Przywara
1278543e620SIcenowy Zheng&ohci0 {
1288543e620SIcenowy Zheng	status = "okay";
1298543e620SIcenowy Zheng};
1308543e620SIcenowy Zheng
131d49f9dbcSIcenowy Zheng&ohci1 {
132d49f9dbcSIcenowy Zheng	status = "okay";
133d49f9dbcSIcenowy Zheng};
134d49f9dbcSIcenowy Zheng
1351b3010cdSIcenowy Zheng&r_rsb {
1361b3010cdSIcenowy Zheng	status = "okay";
1371b3010cdSIcenowy Zheng
1381b3010cdSIcenowy Zheng	axp803: pmic@3a3 {
1391b3010cdSIcenowy Zheng		compatible = "x-powers,axp803";
1401b3010cdSIcenowy Zheng		reg = <0x3a3>;
1411b3010cdSIcenowy Zheng		interrupt-parent = <&r_intc>;
142*73088dfeSSamuel Holland		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
1431b3010cdSIcenowy Zheng	};
1441b3010cdSIcenowy Zheng};
1451b3010cdSIcenowy Zheng
1462f005b44SIcenowy Zheng#include "axp803.dtsi"
1472f005b44SIcenowy Zheng
148a24270afSChen-Yu Tsai&ac_power_supply {
149a24270afSChen-Yu Tsai	status = "okay";
150a24270afSChen-Yu Tsai};
151a24270afSChen-Yu Tsai
152a24270afSChen-Yu Tsai&battery_power_supply {
153a24270afSChen-Yu Tsai	status = "okay";
154a24270afSChen-Yu Tsai};
155a24270afSChen-Yu Tsai
1562f005b44SIcenowy Zheng&reg_aldo2 {
1572f005b44SIcenowy Zheng	regulator-always-on;
1582f005b44SIcenowy Zheng	regulator-min-microvolt = <1800000>;
1592f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1602f005b44SIcenowy Zheng	regulator-name = "vcc-pl";
1612f005b44SIcenowy Zheng};
1622f005b44SIcenowy Zheng
1632f005b44SIcenowy Zheng&reg_aldo3 {
1642f005b44SIcenowy Zheng	regulator-always-on;
1652f005b44SIcenowy Zheng	regulator-min-microvolt = <3000000>;
1662f005b44SIcenowy Zheng	regulator-max-microvolt = <3000000>;
1672f005b44SIcenowy Zheng	regulator-name = "vcc-pll-avcc";
1682f005b44SIcenowy Zheng};
1692f005b44SIcenowy Zheng
1702f005b44SIcenowy Zheng&reg_dc1sw {
1712f005b44SIcenowy Zheng	regulator-name = "vcc-phy";
1722f005b44SIcenowy Zheng};
1732f005b44SIcenowy Zheng
1742f005b44SIcenowy Zheng&reg_dcdc1 {
1752f005b44SIcenowy Zheng	regulator-always-on;
1762f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
1772f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
1782f005b44SIcenowy Zheng	regulator-name = "vcc-3v3";
1792f005b44SIcenowy Zheng};
1802f005b44SIcenowy Zheng
1812f005b44SIcenowy Zheng&reg_dcdc2 {
1822f005b44SIcenowy Zheng	regulator-always-on;
1832f005b44SIcenowy Zheng	regulator-min-microvolt = <1040000>;
1842f005b44SIcenowy Zheng	regulator-max-microvolt = <1300000>;
1852f005b44SIcenowy Zheng	regulator-name = "vdd-cpux";
1862f005b44SIcenowy Zheng};
1872f005b44SIcenowy Zheng
1882f005b44SIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */
1892f005b44SIcenowy Zheng
1902f005b44SIcenowy Zheng/*
1912f005b44SIcenowy Zheng * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can
1922f005b44SIcenowy Zheng * work at 1.35V with less power consumption.
1932f005b44SIcenowy Zheng * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead.
1942f005b44SIcenowy Zheng */
1952f005b44SIcenowy Zheng&reg_dcdc5 {
1962f005b44SIcenowy Zheng	regulator-always-on;
1972f005b44SIcenowy Zheng	regulator-min-microvolt = <1360000>;
1982f005b44SIcenowy Zheng	regulator-max-microvolt = <1360000>;
1992f005b44SIcenowy Zheng	regulator-name = "vcc-dram";
2002f005b44SIcenowy Zheng};
2012f005b44SIcenowy Zheng
2022f005b44SIcenowy Zheng&reg_dcdc6 {
2032f005b44SIcenowy Zheng	regulator-always-on;
2042f005b44SIcenowy Zheng	regulator-min-microvolt = <1100000>;
2052f005b44SIcenowy Zheng	regulator-max-microvolt = <1100000>;
2062f005b44SIcenowy Zheng	regulator-name = "vdd-sys";
2072f005b44SIcenowy Zheng};
2082f005b44SIcenowy Zheng
2092f005b44SIcenowy Zheng&reg_dldo1 {
2102f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2112f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2122f005b44SIcenowy Zheng	regulator-name = "vcc-hdmi";
2132f005b44SIcenowy Zheng};
2142f005b44SIcenowy Zheng
2152f005b44SIcenowy Zheng&reg_dldo2 {
2162f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2172f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2182f005b44SIcenowy Zheng	regulator-name = "vcc-mipi";
2192f005b44SIcenowy Zheng};
2202f005b44SIcenowy Zheng
2212f005b44SIcenowy Zheng&reg_dldo4 {
2222f005b44SIcenowy Zheng	regulator-min-microvolt = <3300000>;
2232f005b44SIcenowy Zheng	regulator-max-microvolt = <3300000>;
2242f005b44SIcenowy Zheng	regulator-name = "vcc-wifi";
2252f005b44SIcenowy Zheng};
2262f005b44SIcenowy Zheng
2272f005b44SIcenowy Zheng&reg_eldo1 {
2282f005b44SIcenowy Zheng	regulator-min-microvolt = <1800000>;
2292f005b44SIcenowy Zheng	regulator-max-microvolt = <1800000>;
2302f005b44SIcenowy Zheng	regulator-name = "cpvdd";
2312f005b44SIcenowy Zheng};
2322f005b44SIcenowy Zheng
2332f005b44SIcenowy Zheng&reg_fldo1 {
2342f005b44SIcenowy Zheng	regulator-min-microvolt = <1200000>;
2352f005b44SIcenowy Zheng	regulator-max-microvolt = <1200000>;
2362f005b44SIcenowy Zheng	regulator-name = "vcc-1v2-hsic";
2372f005b44SIcenowy Zheng};
2382f005b44SIcenowy Zheng
2392f005b44SIcenowy Zheng/*
2402f005b44SIcenowy Zheng * The A64 chip cannot work without this regulator off, although
2412f005b44SIcenowy Zheng * it seems to be only driving the AR100 core.
2422f005b44SIcenowy Zheng * Maybe we don't still know well about CPUs domain.
2432f005b44SIcenowy Zheng */
2442f005b44SIcenowy Zheng&reg_fldo2 {
2452f005b44SIcenowy Zheng	regulator-always-on;
2462f005b44SIcenowy Zheng	regulator-min-microvolt = <1100000>;
2472f005b44SIcenowy Zheng	regulator-max-microvolt = <1100000>;
2482f005b44SIcenowy Zheng	regulator-name = "vdd-cpus";
2492f005b44SIcenowy Zheng};
2502f005b44SIcenowy Zheng
2512f005b44SIcenowy Zheng&reg_rtc_ldo {
2522f005b44SIcenowy Zheng	regulator-name = "vcc-rtc";
2532f005b44SIcenowy Zheng};
2542f005b44SIcenowy Zheng
2555cbef9f9SIcenowy Zheng&simplefb_hdmi {
2565cbef9f9SIcenowy Zheng	vcc-hdmi-supply = <&reg_dldo1>;
2575cbef9f9SIcenowy Zheng};
2585cbef9f9SIcenowy Zheng
259498c21f2SVasily Khoruzhick&sound {
260498c21f2SVasily Khoruzhick	simple-audio-card,aux-devs = <&codec_analog>;
261498c21f2SVasily Khoruzhick	simple-audio-card,widgets = "Microphone", "Microphone Jack",
262498c21f2SVasily Khoruzhick				    "Headphone", "Headphone Jack";
263498c21f2SVasily Khoruzhick	simple-audio-card,routing =
264631e6a35SSamuel Holland			"Left DAC", "DACL",
265631e6a35SSamuel Holland			"Right DAC", "DACR",
266498c21f2SVasily Khoruzhick			"Headphone Jack", "HP",
267631e6a35SSamuel Holland			"ADCL", "Left ADC",
268631e6a35SSamuel Holland			"ADCR", "Right ADC",
269498c21f2SVasily Khoruzhick			"MIC2", "Microphone Jack";
270498c21f2SVasily Khoruzhick	status = "okay";
271498c21f2SVasily Khoruzhick};
272498c21f2SVasily Khoruzhick
273fcf7e5feSMarcus Cooper/* On Euler connector */
274fcf7e5feSMarcus Cooper&spdif {
275fcf7e5feSMarcus Cooper	status = "disabled";
276fcf7e5feSMarcus Cooper};
277fcf7e5feSMarcus Cooper
2782273aa16SAndreas Färber/* On Exp and Euler connectors */
279ac93c09cSIcenowy Zheng&uart0 {
280ac93c09cSIcenowy Zheng	pinctrl-names = "default";
281d91ebb95SChen-Yu Tsai	pinctrl-0 = <&uart0_pb_pins>;
282ac93c09cSIcenowy Zheng	status = "okay";
283ac93c09cSIcenowy Zheng};
284d49f9dbcSIcenowy Zheng
2852273aa16SAndreas Färber/* On Wifi/BT connector, with RTS/CTS */
2862273aa16SAndreas Färber&uart1 {
2872273aa16SAndreas Färber	pinctrl-names = "default";
2882273aa16SAndreas Färber	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
2892273aa16SAndreas Färber	status = "disabled";
2902273aa16SAndreas Färber};
2912273aa16SAndreas Färber
2922273aa16SAndreas Färber/* On Pi-2 connector */
2932273aa16SAndreas Färber&uart2 {
2942273aa16SAndreas Färber	pinctrl-names = "default";
2952273aa16SAndreas Färber	pinctrl-0 = <&uart2_pins>;
2962273aa16SAndreas Färber	status = "disabled";
2972273aa16SAndreas Färber};
2982273aa16SAndreas Färber
2992273aa16SAndreas Färber/* On Euler connector */
3002273aa16SAndreas Färber&uart3 {
3012273aa16SAndreas Färber	pinctrl-names = "default";
3022273aa16SAndreas Färber	pinctrl-0 = <&uart3_pins>;
3032273aa16SAndreas Färber	status = "disabled";
3042273aa16SAndreas Färber};
3052273aa16SAndreas Färber
3062273aa16SAndreas Färber/* On Euler connector, RTS/CTS optional */
3072273aa16SAndreas Färber&uart4 {
3082273aa16SAndreas Färber	pinctrl-names = "default";
3092273aa16SAndreas Färber	pinctrl-0 = <&uart4_pins>;
3102273aa16SAndreas Färber	status = "disabled";
3112273aa16SAndreas Färber};
3122273aa16SAndreas Färber
313f57e8384SIcenowy Zheng&usb_otg {
314f57e8384SIcenowy Zheng	dr_mode = "host";
315f57e8384SIcenowy Zheng	status = "okay";
316f57e8384SIcenowy Zheng};
317f57e8384SIcenowy Zheng
318d49f9dbcSIcenowy Zheng&usbphy {
319d49f9dbcSIcenowy Zheng	status = "okay";
320d49f9dbcSIcenowy Zheng};
321