1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2/* 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-a100-ccu.h> 8#include <dt-bindings/clock/sun50i-a100-r-ccu.h> 9#include <dt-bindings/reset/sun50i-a100-ccu.h> 10#include <dt-bindings/reset/sun50i-a100-r-ccu.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a53"; 23 device_type = "cpu"; 24 reg = <0x0>; 25 enable-method = "psci"; 26 }; 27 28 cpu@1 { 29 compatible = "arm,cortex-a53"; 30 device_type = "cpu"; 31 reg = <0x1>; 32 enable-method = "psci"; 33 }; 34 35 cpu@2 { 36 compatible = "arm,cortex-a53"; 37 device_type = "cpu"; 38 reg = <0x2>; 39 enable-method = "psci"; 40 }; 41 42 cpu@3 { 43 compatible = "arm,cortex-a53"; 44 device_type = "cpu"; 45 reg = <0x3>; 46 enable-method = "psci"; 47 }; 48 }; 49 50 psci { 51 compatible = "arm,psci-1.0"; 52 method = "smc"; 53 }; 54 55 dcxo24M: dcxo24M-clk { 56 compatible = "fixed-clock"; 57 clock-frequency = <24000000>; 58 clock-output-names = "dcxo24M"; 59 #clock-cells = <0>; 60 }; 61 62 iosc: internal-osc-clk { 63 compatible = "fixed-clock"; 64 clock-frequency = <16000000>; 65 clock-accuracy = <300000000>; 66 clock-output-names = "iosc"; 67 #clock-cells = <0>; 68 }; 69 70 osc32k: osc32k-clk { 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 clock-output-names = "osc32k"; 74 #clock-cells = <0>; 75 }; 76 77 timer { 78 compatible = "arm,armv8-timer"; 79 interrupts = <GIC_PPI 13 80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 81 <GIC_PPI 14 82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 83 <GIC_PPI 11 84 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 85 <GIC_PPI 10 86 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 87 }; 88 89 soc { 90 compatible = "simple-bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges = <0 0 0 0x3fffffff>; 94 95 ccu: clock@3001000 { 96 compatible = "allwinner,sun50i-a100-ccu"; 97 reg = <0x03001000 0x1000>; 98 clocks = <&dcxo24M>, <&osc32k>, <&iosc>; 99 clock-names = "hosc", "losc", "iosc"; 100 #clock-cells = <1>; 101 #reset-cells = <1>; 102 }; 103 104 dma: dma-controller@3002000 { 105 compatible = "allwinner,sun50i-a100-dma"; 106 reg = <0x03002000 0x1000>; 107 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 109 clock-names = "bus", "mbus"; 110 resets = <&ccu RST_BUS_DMA>; 111 dma-channels = <8>; 112 dma-requests = <52>; 113 #dma-cells = <1>; 114 }; 115 116 gic: interrupt-controller@3021000 { 117 compatible = "arm,gic-400"; 118 reg = <0x03021000 0x1000>, <0x03022000 0x2000>, 119 <0x03024000 0x2000>, <0x03026000 0x2000>; 120 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 121 IRQ_TYPE_LEVEL_HIGH)>; 122 interrupt-controller; 123 #interrupt-cells = <3>; 124 }; 125 126 efuse@3006000 { 127 compatible = "allwinner,sun50i-a100-sid", 128 "allwinner,sun50i-a64-sid"; 129 reg = <0x03006000 0x1000>; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 133 ths_calibration: calib@14 { 134 reg = <0x14 8>; 135 }; 136 }; 137 138 pio: pinctrl@300b000 { 139 compatible = "allwinner,sun50i-a100-pinctrl"; 140 reg = <0x0300b000 0x400>; 141 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; 149 clock-names = "apb", "hosc", "losc"; 150 gpio-controller; 151 #gpio-cells = <3>; 152 interrupt-controller; 153 #interrupt-cells = <3>; 154 155 uart0_pb_pins: uart0-pb-pins { 156 pins = "PB9", "PB10"; 157 function = "uart0"; 158 }; 159 }; 160 161 uart0: serial@5000000 { 162 compatible = "snps,dw-apb-uart"; 163 reg = <0x05000000 0x400>; 164 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 165 reg-shift = <2>; 166 reg-io-width = <4>; 167 clocks = <&ccu CLK_BUS_UART0>; 168 resets = <&ccu RST_BUS_UART0>; 169 status = "disabled"; 170 }; 171 172 uart1: serial@5000400 { 173 compatible = "snps,dw-apb-uart"; 174 reg = <0x05000400 0x400>; 175 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 176 reg-shift = <2>; 177 reg-io-width = <4>; 178 clocks = <&ccu CLK_BUS_UART1>; 179 resets = <&ccu RST_BUS_UART1>; 180 status = "disabled"; 181 }; 182 183 uart2: serial@5000800 { 184 compatible = "snps,dw-apb-uart"; 185 reg = <0x05000800 0x400>; 186 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 187 reg-shift = <2>; 188 reg-io-width = <4>; 189 clocks = <&ccu CLK_BUS_UART2>; 190 resets = <&ccu RST_BUS_UART2>; 191 status = "disabled"; 192 }; 193 194 uart3: serial@5000c00 { 195 compatible = "snps,dw-apb-uart"; 196 reg = <0x05000c00 0x400>; 197 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 198 reg-shift = <2>; 199 reg-io-width = <4>; 200 clocks = <&ccu CLK_BUS_UART3>; 201 resets = <&ccu RST_BUS_UART3>; 202 status = "disabled"; 203 }; 204 205 uart4: serial@5001000 { 206 compatible = "snps,dw-apb-uart"; 207 reg = <0x05001000 0x400>; 208 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 209 reg-shift = <2>; 210 reg-io-width = <4>; 211 clocks = <&ccu CLK_BUS_UART4>; 212 resets = <&ccu RST_BUS_UART4>; 213 status = "disabled"; 214 }; 215 216 i2c0: i2c@5002000 { 217 compatible = "allwinner,sun50i-a100-i2c", 218 "allwinner,sun8i-v536-i2c", 219 "allwinner,sun6i-a31-i2c"; 220 reg = <0x05002000 0x400>; 221 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&ccu CLK_BUS_I2C0>; 223 resets = <&ccu RST_BUS_I2C0>; 224 status = "disabled"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 }; 228 229 i2c1: i2c@5002400 { 230 compatible = "allwinner,sun50i-a100-i2c", 231 "allwinner,sun8i-v536-i2c", 232 "allwinner,sun6i-a31-i2c"; 233 reg = <0x05002400 0x400>; 234 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&ccu CLK_BUS_I2C1>; 236 resets = <&ccu RST_BUS_I2C1>; 237 status = "disabled"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 }; 241 242 i2c2: i2c@5002800 { 243 compatible = "allwinner,sun50i-a100-i2c", 244 "allwinner,sun8i-v536-i2c", 245 "allwinner,sun6i-a31-i2c"; 246 reg = <0x05002800 0x400>; 247 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&ccu CLK_BUS_I2C2>; 249 resets = <&ccu RST_BUS_I2C2>; 250 status = "disabled"; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 }; 254 255 i2c3: i2c@5002c00 { 256 compatible = "allwinner,sun50i-a100-i2c", 257 "allwinner,sun8i-v536-i2c", 258 "allwinner,sun6i-a31-i2c"; 259 reg = <0x05002c00 0x400>; 260 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&ccu CLK_BUS_I2C3>; 262 resets = <&ccu RST_BUS_I2C3>; 263 status = "disabled"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 }; 267 268 ths: thermal-sensor@5070400 { 269 compatible = "allwinner,sun50i-a100-ths"; 270 reg = <0x05070400 0x100>; 271 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&ccu CLK_BUS_THS>; 273 clock-names = "bus"; 274 resets = <&ccu RST_BUS_THS>; 275 nvmem-cells = <&ths_calibration>; 276 nvmem-cell-names = "calibration"; 277 #thermal-sensor-cells = <1>; 278 }; 279 280 r_ccu: clock@7010000 { 281 compatible = "allwinner,sun50i-a100-r-ccu"; 282 reg = <0x07010000 0x300>; 283 clocks = <&dcxo24M>, <&osc32k>, <&iosc>, 284 <&ccu CLK_PLL_PERIPH0>; 285 clock-names = "hosc", "losc", "iosc", "pll-periph"; 286 #clock-cells = <1>; 287 #reset-cells = <1>; 288 }; 289 290 r_intc: interrupt-controller@7010320 { 291 compatible = "allwinner,sun50i-a100-nmi", 292 "allwinner,sun9i-a80-nmi"; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 reg = <0x07010320 0xc>; 296 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 297 }; 298 299 r_pio: pinctrl@7022000 { 300 compatible = "allwinner,sun50i-a100-r-pinctrl"; 301 reg = <0x07022000 0x400>; 302 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; 304 clock-names = "apb", "hosc", "losc"; 305 gpio-controller; 306 #gpio-cells = <3>; 307 interrupt-controller; 308 #interrupt-cells = <3>; 309 310 r_i2c0_pins: r-i2c0-pins { 311 pins = "PL0", "PL1"; 312 function = "s_i2c0"; 313 }; 314 315 r_i2c1_pins: r-i2c1-pins { 316 pins = "PL8", "PL9"; 317 function = "s_i2c1"; 318 }; 319 }; 320 321 r_uart: serial@7080000 { 322 compatible = "snps,dw-apb-uart"; 323 reg = <0x07080000 0x400>; 324 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 325 reg-shift = <2>; 326 reg-io-width = <4>; 327 clocks = <&r_ccu CLK_R_APB2_UART>; 328 resets = <&r_ccu RST_R_APB2_UART>; 329 status = "disabled"; 330 }; 331 332 r_i2c0: i2c@7081400 { 333 compatible = "allwinner,sun50i-a100-i2c", 334 "allwinner,sun8i-v536-i2c", 335 "allwinner,sun6i-a31-i2c"; 336 reg = <0x07081400 0x400>; 337 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&r_ccu CLK_R_APB2_I2C0>; 339 resets = <&r_ccu RST_R_APB2_I2C0>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&r_i2c0_pins>; 342 status = "disabled"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 }; 346 347 r_i2c1: i2c@7081800 { 348 compatible = "allwinner,sun50i-a100-i2c", 349 "allwinner,sun8i-v536-i2c", 350 "allwinner,sun6i-a31-i2c"; 351 reg = <0x07081800 0x400>; 352 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&r_ccu CLK_R_APB2_I2C1>; 354 resets = <&r_ccu RST_R_APB2_I2C1>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&r_i2c1_pins>; 357 status = "disabled"; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 }; 361 }; 362 363 thermal-zones { 364 cpu-thermal { 365 polling-delay-passive = <0>; 366 polling-delay = <0>; 367 thermal-sensors = <&ths 0>; 368 }; 369 370 ddr-thermal { 371 polling-delay-passive = <0>; 372 polling-delay = <0>; 373 thermal-sensors = <&ths 2>; 374 }; 375 376 gpu-thermal { 377 polling-delay-passive = <0>; 378 polling-delay = <0>; 379 thermal-sensors = <&ths 1>; 380 }; 381 }; 382}; 383