1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Copyright (C) 2011 - 2014 Xilinx
4*724ba675SRob Herring * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
5*724ba675SRob Herring */
6*724ba675SRob Herring/dts-v1/;
7*724ba675SRob Herring/include/ "zynq-7000.dtsi"
8*724ba675SRob Herring
9*724ba675SRob Herring/ {
10*724ba675SRob Herring	model = "Avnet MicroZed board";
11*724ba675SRob Herring	compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
12*724ba675SRob Herring
13*724ba675SRob Herring	aliases {
14*724ba675SRob Herring		ethernet0 = &gem0;
15*724ba675SRob Herring		serial0 = &uart1;
16*724ba675SRob Herring	};
17*724ba675SRob Herring
18*724ba675SRob Herring	memory@0 {
19*724ba675SRob Herring		device_type = "memory";
20*724ba675SRob Herring		reg = <0x0 0x40000000>;
21*724ba675SRob Herring	};
22*724ba675SRob Herring
23*724ba675SRob Herring	chosen {
24*724ba675SRob Herring		bootargs = "earlycon";
25*724ba675SRob Herring		stdout-path = "serial0:115200n8";
26*724ba675SRob Herring	};
27*724ba675SRob Herring
28*724ba675SRob Herring	usb_phy0: phy0 {
29*724ba675SRob Herring		compatible = "usb-nop-xceiv";
30*724ba675SRob Herring		#phy-cells = <0>;
31*724ba675SRob Herring	};
32*724ba675SRob Herring};
33*724ba675SRob Herring
34*724ba675SRob Herring&clkc {
35*724ba675SRob Herring	ps-clk-frequency = <33333333>;
36*724ba675SRob Herring};
37*724ba675SRob Herring
38*724ba675SRob Herring&gem0 {
39*724ba675SRob Herring	status = "okay";
40*724ba675SRob Herring	phy-mode = "rgmii-id";
41*724ba675SRob Herring	phy-handle = <&ethernet_phy>;
42*724ba675SRob Herring
43*724ba675SRob Herring	ethernet_phy: ethernet-phy@0 {
44*724ba675SRob Herring		reg = <0>;
45*724ba675SRob Herring	};
46*724ba675SRob Herring};
47*724ba675SRob Herring
48*724ba675SRob Herring&sdhci0 {
49*724ba675SRob Herring	status = "okay";
50*724ba675SRob Herring};
51*724ba675SRob Herring
52*724ba675SRob Herring&uart1 {
53*724ba675SRob Herring	status = "okay";
54*724ba675SRob Herring};
55*724ba675SRob Herring
56*724ba675SRob Herring&usb0 {
57*724ba675SRob Herring	status = "okay";
58*724ba675SRob Herring	dr_mode = "host";
59*724ba675SRob Herring	usb-phy = <&usb_phy0>;
60*724ba675SRob Herring	pinctrl-names = "default";
61*724ba675SRob Herring	pinctrl-0 = <&pinctrl_usb0_default>;
62*724ba675SRob Herring};
63*724ba675SRob Herring
64*724ba675SRob Herring&pinctrl0 {
65*724ba675SRob Herring	pinctrl_usb0_default: usb0-default {
66*724ba675SRob Herring		mux {
67*724ba675SRob Herring			groups = "usb0_0_grp";
68*724ba675SRob Herring			function = "usb0";
69*724ba675SRob Herring		};
70*724ba675SRob Herring
71*724ba675SRob Herring		conf {
72*724ba675SRob Herring			groups = "usb0_0_grp";
73*724ba675SRob Herring			slew-rate = <0>;
74*724ba675SRob Herring			io-standard = <1>;
75*724ba675SRob Herring		};
76*724ba675SRob Herring
77*724ba675SRob Herring		conf-rx {
78*724ba675SRob Herring			pins = "MIO29", "MIO31", "MIO36";
79*724ba675SRob Herring			bias-high-impedance;
80*724ba675SRob Herring		};
81*724ba675SRob Herring
82*724ba675SRob Herring		conf-tx {
83*724ba675SRob Herring			pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
84*724ba675SRob Herring			       "MIO35", "MIO37", "MIO38", "MIO39";
85*724ba675SRob Herring			bias-disable;
86*724ba675SRob Herring		};
87*724ba675SRob Herring	};
88*724ba675SRob Herring};
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