1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Copyright (C) 2021 Michael Walle <michael@walle.cc>
4*724ba675SRob Herring */
5*724ba675SRob Herring/dts-v1/;
6*724ba675SRob Herring/include/ "zynq-7000.dtsi"
7*724ba675SRob Herring
8*724ba675SRob Herring/ {
9*724ba675SRob Herring	model = "Ebang EBAZ4205";
10*724ba675SRob Herring	compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
11*724ba675SRob Herring
12*724ba675SRob Herring	aliases {
13*724ba675SRob Herring		ethernet0 = &gem0;
14*724ba675SRob Herring		serial0 = &uart1;
15*724ba675SRob Herring	};
16*724ba675SRob Herring
17*724ba675SRob Herring	memory@0 {
18*724ba675SRob Herring		device_type = "memory";
19*724ba675SRob Herring		reg = <0x0 0x10000000>;
20*724ba675SRob Herring	};
21*724ba675SRob Herring
22*724ba675SRob Herring	chosen {
23*724ba675SRob Herring		stdout-path = "serial0:115200n8";
24*724ba675SRob Herring	};
25*724ba675SRob Herring};
26*724ba675SRob Herring
27*724ba675SRob Herring&clkc {
28*724ba675SRob Herring	ps-clk-frequency = <33333333>;
29*724ba675SRob Herring	fclk-enable = <8>;
30*724ba675SRob Herring};
31*724ba675SRob Herring
32*724ba675SRob Herring&gem0 {
33*724ba675SRob Herring	status = "okay";
34*724ba675SRob Herring	phy-mode = "mii";
35*724ba675SRob Herring	phy-handle = <&phy>;
36*724ba675SRob Herring
37*724ba675SRob Herring	/* PHY clock */
38*724ba675SRob Herring	assigned-clocks = <&clkc 18>;
39*724ba675SRob Herring	assigned-clock-rates = <25000000>;
40*724ba675SRob Herring
41*724ba675SRob Herring	phy: ethernet-phy@0 {
42*724ba675SRob Herring		reg = <0>;
43*724ba675SRob Herring	};
44*724ba675SRob Herring};
45*724ba675SRob Herring
46*724ba675SRob Herring&gpio0 {
47*724ba675SRob Herring	pinctrl-names = "default";
48*724ba675SRob Herring	pinctrl-0 = <&pinctrl_gpio0_default>;
49*724ba675SRob Herring};
50*724ba675SRob Herring
51*724ba675SRob Herring&nfc0 {
52*724ba675SRob Herring	status = "okay";
53*724ba675SRob Herring
54*724ba675SRob Herring	nand@0 {
55*724ba675SRob Herring		reg = <0>;
56*724ba675SRob Herring	};
57*724ba675SRob Herring};
58*724ba675SRob Herring
59*724ba675SRob Herring&pinctrl0 {
60*724ba675SRob Herring	pinctrl_gpio0_default: gpio0-default {
61*724ba675SRob Herring		mux {
62*724ba675SRob Herring			groups = "gpio0_20_grp", "gpio0_32_grp";
63*724ba675SRob Herring			function = "gpio0";
64*724ba675SRob Herring		};
65*724ba675SRob Herring
66*724ba675SRob Herring		conf {
67*724ba675SRob Herring			groups = "gpio0_20_grp", "gpio0_32_grp";
68*724ba675SRob Herring			io-standard = <3>;
69*724ba675SRob Herring			slew-rate = <0>;
70*724ba675SRob Herring		};
71*724ba675SRob Herring
72*724ba675SRob Herring		conf-pull-up {
73*724ba675SRob Herring			pins = "MIO20", "MIO32";
74*724ba675SRob Herring			bias-disable;
75*724ba675SRob Herring		};
76*724ba675SRob Herring	};
77*724ba675SRob Herring
78*724ba675SRob Herring	pinctrl_sdhci0_default: sdhci0-default {
79*724ba675SRob Herring		mux {
80*724ba675SRob Herring			groups = "sdio0_2_grp";
81*724ba675SRob Herring			function = "sdio0";
82*724ba675SRob Herring		};
83*724ba675SRob Herring
84*724ba675SRob Herring		conf {
85*724ba675SRob Herring			groups = "sdio0_2_grp";
86*724ba675SRob Herring			io-standard = <3>;
87*724ba675SRob Herring			slew-rate = <0>;
88*724ba675SRob Herring			bias-disable;
89*724ba675SRob Herring		};
90*724ba675SRob Herring
91*724ba675SRob Herring		mux-cd {
92*724ba675SRob Herring			groups = "gpio0_34_grp";
93*724ba675SRob Herring			function = "sdio0_cd";
94*724ba675SRob Herring		};
95*724ba675SRob Herring
96*724ba675SRob Herring		conf-cd {
97*724ba675SRob Herring			groups = "gpio0_34_grp";
98*724ba675SRob Herring			io-standard = <3>;
99*724ba675SRob Herring			slew-rate = <0>;
100*724ba675SRob Herring			bias-high-impedance;
101*724ba675SRob Herring			bias-pull-up;
102*724ba675SRob Herring		};
103*724ba675SRob Herring	};
104*724ba675SRob Herring
105*724ba675SRob Herring	pinctrl_uart1_default: uart1-default {
106*724ba675SRob Herring		mux {
107*724ba675SRob Herring			groups = "uart1_4_grp";
108*724ba675SRob Herring			function = "uart1";
109*724ba675SRob Herring		};
110*724ba675SRob Herring
111*724ba675SRob Herring		conf {
112*724ba675SRob Herring			groups = "uart1_4_grp";
113*724ba675SRob Herring			io-standard = <3>;
114*724ba675SRob Herring			slew-rate = <0>;
115*724ba675SRob Herring		};
116*724ba675SRob Herring
117*724ba675SRob Herring		conf-rx {
118*724ba675SRob Herring			pins = "MIO25";
119*724ba675SRob Herring			bias-high-impedance;
120*724ba675SRob Herring		};
121*724ba675SRob Herring
122*724ba675SRob Herring		conf-tx {
123*724ba675SRob Herring			pins = "MIO24";
124*724ba675SRob Herring			bias-disable;
125*724ba675SRob Herring		};
126*724ba675SRob Herring	};
127*724ba675SRob Herring};
128*724ba675SRob Herring
129*724ba675SRob Herring&smcc {
130*724ba675SRob Herring	status = "okay";
131*724ba675SRob Herring};
132*724ba675SRob Herring
133*724ba675SRob Herring&sdhci0 {
134*724ba675SRob Herring	status = "okay";
135*724ba675SRob Herring	disable-wp;
136*724ba675SRob Herring	pinctrl-names = "default";
137*724ba675SRob Herring	pinctrl-0 = <&pinctrl_sdhci0_default>;
138*724ba675SRob Herring};
139*724ba675SRob Herring
140*724ba675SRob Herring&uart1 {
141*724ba675SRob Herring	status = "okay";
142*724ba675SRob Herring	pinctrl-names = "default";
143*724ba675SRob Herring	pinctrl-0 = <&pinctrl_uart1_default>;
144*724ba675SRob Herring};
145