1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Xen Virtual Machine for unprivileged guests 4*724ba675SRob Herring * 5*724ba675SRob Herring * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) 6*724ba675SRob Herring * Cortex-A15 MPCore (V2P-CA15) 7*724ba675SRob Herring * 8*724ba675SRob Herring */ 9*724ba675SRob Herring 10*724ba675SRob Herring/dts-v1/; 11*724ba675SRob Herring 12*724ba675SRob Herring/ { 13*724ba675SRob Herring model = "XENVM-4.2"; 14*724ba675SRob Herring compatible = "xen,xenvm-4.2", "xen,xenvm"; 15*724ba675SRob Herring interrupt-parent = <&gic>; 16*724ba675SRob Herring #address-cells = <2>; 17*724ba675SRob Herring #size-cells = <2>; 18*724ba675SRob Herring 19*724ba675SRob Herring chosen { 20*724ba675SRob Herring /* this field is going to be adjusted by the hypervisor */ 21*724ba675SRob Herring bootargs = "console=hvc0 root=/dev/xvda"; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring cpus { 25*724ba675SRob Herring #address-cells = <1>; 26*724ba675SRob Herring #size-cells = <0>; 27*724ba675SRob Herring 28*724ba675SRob Herring cpu@0 { 29*724ba675SRob Herring device_type = "cpu"; 30*724ba675SRob Herring compatible = "arm,cortex-a15"; 31*724ba675SRob Herring reg = <0>; 32*724ba675SRob Herring }; 33*724ba675SRob Herring 34*724ba675SRob Herring cpu@1 { 35*724ba675SRob Herring device_type = "cpu"; 36*724ba675SRob Herring compatible = "arm,cortex-a15"; 37*724ba675SRob Herring reg = <1>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring }; 40*724ba675SRob Herring 41*724ba675SRob Herring psci { 42*724ba675SRob Herring compatible = "arm,psci"; 43*724ba675SRob Herring method = "hvc"; 44*724ba675SRob Herring cpu_off = <1>; 45*724ba675SRob Herring cpu_on = <2>; 46*724ba675SRob Herring }; 47*724ba675SRob Herring 48*724ba675SRob Herring memory@80000000 { 49*724ba675SRob Herring device_type = "memory"; 50*724ba675SRob Herring /* this field is going to be adjusted by the hypervisor */ 51*724ba675SRob Herring reg = <0 0x80000000 0 0x08000000>; 52*724ba675SRob Herring }; 53*724ba675SRob Herring 54*724ba675SRob Herring gic: interrupt-controller@2c001000 { 55*724ba675SRob Herring compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 56*724ba675SRob Herring #interrupt-cells = <3>; 57*724ba675SRob Herring #address-cells = <0>; 58*724ba675SRob Herring interrupt-controller; 59*724ba675SRob Herring reg = <0 0x2c001000 0 0x1000>, 60*724ba675SRob Herring <0 0x2c002000 0 0x100>; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring timer { 64*724ba675SRob Herring compatible = "arm,armv7-timer"; 65*724ba675SRob Herring interrupts = <1 13 0xf08>, 66*724ba675SRob Herring <1 14 0xf08>, 67*724ba675SRob Herring <1 11 0xf08>, 68*724ba675SRob Herring <1 10 0xf08>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring hypervisor { 72*724ba675SRob Herring compatible = "xen,xen-4.2", "xen,xen"; 73*724ba675SRob Herring /* this field is going to be adjusted by the hypervisor */ 74*724ba675SRob Herring reg = <0 0xb0000000 0 0x20000>; 75*724ba675SRob Herring /* this field is going to be adjusted by the hypervisor */ 76*724ba675SRob Herring interrupts = <1 15 0xf08>; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring motherboard { 80*724ba675SRob Herring arm,v2m-memory-map = "rs1"; 81*724ba675SRob Herring }; 82*724ba675SRob Herring}; 83