1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2724ba675SRob Herring/* 3724ba675SRob Herring * Device Tree Source for OMAP4460 SoC 4724ba675SRob Herring * 5724ba675SRob Herring * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 6724ba675SRob Herring */ 7724ba675SRob Herring#include "omap4.dtsi" 8724ba675SRob Herring 9724ba675SRob Herring/ { 10724ba675SRob Herring cpus { 11724ba675SRob Herring /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */ 12724ba675SRob Herring cpu0: cpu@0 { 13724ba675SRob Herring operating-points = < 14724ba675SRob Herring /* kHz uV */ 15724ba675SRob Herring 350000 1025000 16724ba675SRob Herring 700000 1200000 17724ba675SRob Herring 920000 1313000 18724ba675SRob Herring >; 19724ba675SRob Herring clock-latency = <300000>; /* From legacy driver */ 20724ba675SRob Herring 21724ba675SRob Herring /* cooling options */ 22724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 23724ba675SRob Herring }; 24724ba675SRob Herring }; 25724ba675SRob Herring 26724ba675SRob Herring thermal-zones { 27724ba675SRob Herring #include "omap4-cpu-thermal.dtsi" 28724ba675SRob Herring }; 29724ba675SRob Herring 30724ba675SRob Herring ocp { 31724ba675SRob Herring bandgap: bandgap@4a002260 { 32724ba675SRob Herring reg = <0x4a002260 0x4 33724ba675SRob Herring 0x4a00232C 0x4 34724ba675SRob Herring 0x4a002378 0x18>; 35724ba675SRob Herring compatible = "ti,omap4460-bandgap"; 36724ba675SRob Herring interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ 37724ba675SRob Herring gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */ 38724ba675SRob Herring 39724ba675SRob Herring #thermal-sensor-cells = <0>; 40724ba675SRob Herring }; 41724ba675SRob Herring 42724ba675SRob Herring abb_mpu: regulator-abb-mpu { 43724ba675SRob Herring status = "okay"; 44724ba675SRob Herring 45724ba675SRob Herring reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, 46724ba675SRob Herring <0x4A002268 0x4>; 47724ba675SRob Herring reg-names = "base-address", "int-address", 48724ba675SRob Herring "efuse-address"; 49724ba675SRob Herring 50724ba675SRob Herring ti,abb_info = < 51724ba675SRob Herring /*uV ABB efuse rbb_m fbb_m vset_m*/ 52724ba675SRob Herring 1025000 0 0 0 0 0 53724ba675SRob Herring 1200000 0 0 0 0 0 54724ba675SRob Herring 1313000 0 0 0x100000 0x40000 0 55724ba675SRob Herring 1375000 1 0 0 0 0 56724ba675SRob Herring 1389000 1 0 0 0 0 57724ba675SRob Herring >; 58724ba675SRob Herring }; 59724ba675SRob Herring 60724ba675SRob Herring abb_iva: regulator-abb-iva { 61724ba675SRob Herring status = "okay"; 62724ba675SRob Herring 63724ba675SRob Herring reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>, 64724ba675SRob Herring <0x4A002268 0x4>; 65724ba675SRob Herring reg-names = "base-address", "int-address", 66724ba675SRob Herring "efuse-address"; 67724ba675SRob Herring 68724ba675SRob Herring ti,abb_info = < 69724ba675SRob Herring /*uV ABB efuse rbb_m fbb_m vset_m*/ 70724ba675SRob Herring 950000 0 0 0 0 0 71724ba675SRob Herring 1140000 0 0 0 0 0 72724ba675SRob Herring 1291000 0 0 0x200000 0 0 73724ba675SRob Herring 1375000 1 0 0 0 0 74724ba675SRob Herring 1376000 1 0 0 0 0 75724ba675SRob Herring >; 76724ba675SRob Herring }; 77724ba675SRob Herring }; 78724ba675SRob Herring 79724ba675SRob Herring}; 80724ba675SRob Herring 81724ba675SRob Herring&cpu_thermal { 82*6469b2feSTony Lindgren thermal-sensors = <&bandgap>; 83724ba675SRob Herring coefficients = <348 (-9301)>; 84724ba675SRob Herring}; 85724ba675SRob Herring 86724ba675SRob Herring/* Only some L4 CFG interconnect ranges are different on 4460 */ 87724ba675SRob Herring&l4_cfg_segment_300000 { 88724ba675SRob Herring ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ 89724ba675SRob Herring <0x00040000 0x00340000 0x001000>, /* ap 68 */ 90724ba675SRob Herring <0x00020000 0x00320000 0x004000>, /* ap 71 */ 91724ba675SRob Herring <0x00024000 0x00324000 0x002000>, /* ap 72 */ 92724ba675SRob Herring <0x00026000 0x00326000 0x001000>, /* ap 73 */ 93724ba675SRob Herring <0x00027000 0x00327000 0x001000>, /* ap 74 */ 94724ba675SRob Herring <0x00028000 0x00328000 0x001000>, /* ap 75 */ 95724ba675SRob Herring <0x00029000 0x00329000 0x001000>, /* ap 76 */ 96724ba675SRob Herring <0x00030000 0x00330000 0x010000>, /* ap 77 */ 97724ba675SRob Herring <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ 98724ba675SRob Herring <0x0002c000 0x0032c000 0x004000>, /* ap 91 */ 99724ba675SRob Herring <0x00010000 0x00310000 0x008000>, /* ap 92 */ 100724ba675SRob Herring <0x00018000 0x00318000 0x004000>, /* ap 93 */ 101724ba675SRob Herring <0x0001c000 0x0031c000 0x002000>, /* ap 94 */ 102724ba675SRob Herring <0x0001e000 0x0031e000 0x002000>; /* ap 95 */ 103724ba675SRob Herring}; 104724ba675SRob Herring 105724ba675SRob Herring&l4_cfg_target_0 { 106724ba675SRob Herring ranges = <0x00000000 0x00000000 0x00010000>, 107724ba675SRob Herring <0x00010000 0x00010000 0x00008000>, 108724ba675SRob Herring <0x00018000 0x00018000 0x00004000>, 109724ba675SRob Herring <0x0001c000 0x0001c000 0x00002000>, 110724ba675SRob Herring <0x0001e000 0x0001e000 0x00002000>, 111724ba675SRob Herring <0x00020000 0x00020000 0x00004000>, 112724ba675SRob Herring <0x00024000 0x00024000 0x00002000>, 113724ba675SRob Herring <0x00026000 0x00026000 0x00001000>, 114724ba675SRob Herring <0x00027000 0x00027000 0x00001000>, 115724ba675SRob Herring <0x00028000 0x00028000 0x00001000>, 116724ba675SRob Herring <0x00029000 0x00029000 0x00001000>, 117724ba675SRob Herring <0x0002a000 0x0002a000 0x00002000>, 118724ba675SRob Herring <0x0002c000 0x0002c000 0x00004000>, 119724ba675SRob Herring <0x00030000 0x00030000 0x00010000>; 120724ba675SRob Herring}; 121724ba675SRob Herring 122724ba675SRob Herring&pmu { 123724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 124724ba675SRob Herring interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 125724ba675SRob Herring <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 126724ba675SRob Herring}; 127724ba675SRob Herring 128724ba675SRob Herring/include/ "omap446x-clocks.dtsi" 129