1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for DRA7xx clock data 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013 Texas Instruments, Inc. 6*724ba675SRob Herring */ 7*724ba675SRob Herring&cm_core_aon_clocks { 8*724ba675SRob Herring atl_clkin0_ck: clock-atl-clkin0 { 9*724ba675SRob Herring #clock-cells = <0>; 10*724ba675SRob Herring compatible = "ti,dra7-atl-clock"; 11*724ba675SRob Herring clock-output-names = "atl_clkin0_ck"; 12*724ba675SRob Herring clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 13*724ba675SRob Herring }; 14*724ba675SRob Herring 15*724ba675SRob Herring atl_clkin1_ck: clock-atl-clkin1 { 16*724ba675SRob Herring #clock-cells = <0>; 17*724ba675SRob Herring compatible = "ti,dra7-atl-clock"; 18*724ba675SRob Herring clock-output-names = "atl_clkin1_ck"; 19*724ba675SRob Herring clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 20*724ba675SRob Herring }; 21*724ba675SRob Herring 22*724ba675SRob Herring atl_clkin2_ck: clock-atl-clkin2 { 23*724ba675SRob Herring #clock-cells = <0>; 24*724ba675SRob Herring compatible = "ti,dra7-atl-clock"; 25*724ba675SRob Herring clock-output-names = "atl_clkin2_ck"; 26*724ba675SRob Herring clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring atl_clkin3_ck: clock-atl-clkin3 { 30*724ba675SRob Herring #clock-cells = <0>; 31*724ba675SRob Herring compatible = "ti,dra7-atl-clock"; 32*724ba675SRob Herring clock-output-names = "atl_clkin3_ck"; 33*724ba675SRob Herring clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 34*724ba675SRob Herring }; 35*724ba675SRob Herring 36*724ba675SRob Herring hdmi_clkin_ck: clock-hdmi-clkin { 37*724ba675SRob Herring #clock-cells = <0>; 38*724ba675SRob Herring compatible = "fixed-clock"; 39*724ba675SRob Herring clock-output-names = "hdmi_clkin_ck"; 40*724ba675SRob Herring clock-frequency = <0>; 41*724ba675SRob Herring }; 42*724ba675SRob Herring 43*724ba675SRob Herring mlb_clkin_ck: clock-mlb-clkin { 44*724ba675SRob Herring #clock-cells = <0>; 45*724ba675SRob Herring compatible = "fixed-clock"; 46*724ba675SRob Herring clock-output-names = "mlb_clkin_ck"; 47*724ba675SRob Herring clock-frequency = <0>; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring mlbp_clkin_ck: clock-mlbp-clkin { 51*724ba675SRob Herring #clock-cells = <0>; 52*724ba675SRob Herring compatible = "fixed-clock"; 53*724ba675SRob Herring clock-output-names = "mlbp_clkin_ck"; 54*724ba675SRob Herring clock-frequency = <0>; 55*724ba675SRob Herring }; 56*724ba675SRob Herring 57*724ba675SRob Herring pciesref_acs_clk_ck: clock-pciesref-acs { 58*724ba675SRob Herring #clock-cells = <0>; 59*724ba675SRob Herring compatible = "fixed-clock"; 60*724ba675SRob Herring clock-output-names = "pciesref_acs_clk_ck"; 61*724ba675SRob Herring clock-frequency = <100000000>; 62*724ba675SRob Herring }; 63*724ba675SRob Herring 64*724ba675SRob Herring ref_clkin0_ck: clock-ref-clkin0 { 65*724ba675SRob Herring #clock-cells = <0>; 66*724ba675SRob Herring compatible = "fixed-clock"; 67*724ba675SRob Herring clock-output-names = "ref_clkin0_ck"; 68*724ba675SRob Herring clock-frequency = <0>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring ref_clkin1_ck: clock-ref-clkin1 { 72*724ba675SRob Herring #clock-cells = <0>; 73*724ba675SRob Herring compatible = "fixed-clock"; 74*724ba675SRob Herring clock-output-names = "ref_clkin1_ck"; 75*724ba675SRob Herring clock-frequency = <0>; 76*724ba675SRob Herring }; 77*724ba675SRob Herring 78*724ba675SRob Herring ref_clkin2_ck: clock-ref-clkin2 { 79*724ba675SRob Herring #clock-cells = <0>; 80*724ba675SRob Herring compatible = "fixed-clock"; 81*724ba675SRob Herring clock-output-names = "ref_clkin2_ck"; 82*724ba675SRob Herring clock-frequency = <0>; 83*724ba675SRob Herring }; 84*724ba675SRob Herring 85*724ba675SRob Herring ref_clkin3_ck: clock-ref-clkin3 { 86*724ba675SRob Herring #clock-cells = <0>; 87*724ba675SRob Herring compatible = "fixed-clock"; 88*724ba675SRob Herring clock-output-names = "ref_clkin3_ck"; 89*724ba675SRob Herring clock-frequency = <0>; 90*724ba675SRob Herring }; 91*724ba675SRob Herring 92*724ba675SRob Herring rmii_clk_ck: clock-rmii { 93*724ba675SRob Herring #clock-cells = <0>; 94*724ba675SRob Herring compatible = "fixed-clock"; 95*724ba675SRob Herring clock-output-names = "rmii_clk_ck"; 96*724ba675SRob Herring clock-frequency = <0>; 97*724ba675SRob Herring }; 98*724ba675SRob Herring 99*724ba675SRob Herring sdvenc_clkin_ck: clock-sdvenc-clkin { 100*724ba675SRob Herring #clock-cells = <0>; 101*724ba675SRob Herring compatible = "fixed-clock"; 102*724ba675SRob Herring clock-output-names = "sdvenc_clkin_ck"; 103*724ba675SRob Herring clock-frequency = <0>; 104*724ba675SRob Herring }; 105*724ba675SRob Herring 106*724ba675SRob Herring secure_32k_clk_src_ck: clock-secure-32k-clk-src { 107*724ba675SRob Herring #clock-cells = <0>; 108*724ba675SRob Herring compatible = "fixed-clock"; 109*724ba675SRob Herring clock-output-names = "secure_32k_clk_src_ck"; 110*724ba675SRob Herring clock-frequency = <32768>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring 113*724ba675SRob Herring sys_clk32_crystal_ck: clock-sys-clk32-crystal { 114*724ba675SRob Herring #clock-cells = <0>; 115*724ba675SRob Herring compatible = "fixed-clock"; 116*724ba675SRob Herring clock-output-names = "sys_clk32_crystal_ck"; 117*724ba675SRob Herring clock-frequency = <32768>; 118*724ba675SRob Herring }; 119*724ba675SRob Herring 120*724ba675SRob Herring sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { 121*724ba675SRob Herring #clock-cells = <0>; 122*724ba675SRob Herring compatible = "fixed-factor-clock"; 123*724ba675SRob Herring clock-output-names = "sys_clk32_pseudo_ck"; 124*724ba675SRob Herring clocks = <&sys_clkin1>; 125*724ba675SRob Herring clock-mult = <1>; 126*724ba675SRob Herring clock-div = <610>; 127*724ba675SRob Herring }; 128*724ba675SRob Herring 129*724ba675SRob Herring virt_12000000_ck: clock-virt-12000000 { 130*724ba675SRob Herring #clock-cells = <0>; 131*724ba675SRob Herring compatible = "fixed-clock"; 132*724ba675SRob Herring clock-output-names = "virt_12000000_ck"; 133*724ba675SRob Herring clock-frequency = <12000000>; 134*724ba675SRob Herring }; 135*724ba675SRob Herring 136*724ba675SRob Herring virt_13000000_ck: clock-virt-13000000 { 137*724ba675SRob Herring #clock-cells = <0>; 138*724ba675SRob Herring compatible = "fixed-clock"; 139*724ba675SRob Herring clock-output-names = "virt_13000000_ck"; 140*724ba675SRob Herring clock-frequency = <13000000>; 141*724ba675SRob Herring }; 142*724ba675SRob Herring 143*724ba675SRob Herring virt_16800000_ck: clock-virt-16800000 { 144*724ba675SRob Herring #clock-cells = <0>; 145*724ba675SRob Herring compatible = "fixed-clock"; 146*724ba675SRob Herring clock-output-names = "virt_16800000_ck"; 147*724ba675SRob Herring clock-frequency = <16800000>; 148*724ba675SRob Herring }; 149*724ba675SRob Herring 150*724ba675SRob Herring virt_19200000_ck: clock-virt-19200000 { 151*724ba675SRob Herring #clock-cells = <0>; 152*724ba675SRob Herring compatible = "fixed-clock"; 153*724ba675SRob Herring clock-output-names = "virt_19200000_ck"; 154*724ba675SRob Herring clock-frequency = <19200000>; 155*724ba675SRob Herring }; 156*724ba675SRob Herring 157*724ba675SRob Herring virt_20000000_ck: clock-virt-20000000 { 158*724ba675SRob Herring #clock-cells = <0>; 159*724ba675SRob Herring compatible = "fixed-clock"; 160*724ba675SRob Herring clock-output-names = "virt_20000000_ck"; 161*724ba675SRob Herring clock-frequency = <20000000>; 162*724ba675SRob Herring }; 163*724ba675SRob Herring 164*724ba675SRob Herring virt_26000000_ck: clock-virt-26000000 { 165*724ba675SRob Herring #clock-cells = <0>; 166*724ba675SRob Herring compatible = "fixed-clock"; 167*724ba675SRob Herring clock-output-names = "virt_26000000_ck"; 168*724ba675SRob Herring clock-frequency = <26000000>; 169*724ba675SRob Herring }; 170*724ba675SRob Herring 171*724ba675SRob Herring virt_27000000_ck: clock-virt-27000000 { 172*724ba675SRob Herring #clock-cells = <0>; 173*724ba675SRob Herring compatible = "fixed-clock"; 174*724ba675SRob Herring clock-output-names = "virt_27000000_ck"; 175*724ba675SRob Herring clock-frequency = <27000000>; 176*724ba675SRob Herring }; 177*724ba675SRob Herring 178*724ba675SRob Herring virt_38400000_ck: clock-virt-38400000 { 179*724ba675SRob Herring #clock-cells = <0>; 180*724ba675SRob Herring compatible = "fixed-clock"; 181*724ba675SRob Herring clock-output-names = "virt_38400000_ck"; 182*724ba675SRob Herring clock-frequency = <38400000>; 183*724ba675SRob Herring }; 184*724ba675SRob Herring 185*724ba675SRob Herring sys_clkin2: clock-sys-clkin2 { 186*724ba675SRob Herring #clock-cells = <0>; 187*724ba675SRob Herring compatible = "fixed-clock"; 188*724ba675SRob Herring clock-output-names = "sys_clkin2"; 189*724ba675SRob Herring clock-frequency = <22579200>; 190*724ba675SRob Herring }; 191*724ba675SRob Herring 192*724ba675SRob Herring usb_otg_clkin_ck: clock-usb-otg-clkin { 193*724ba675SRob Herring #clock-cells = <0>; 194*724ba675SRob Herring compatible = "fixed-clock"; 195*724ba675SRob Herring clock-output-names = "usb_otg_clkin_ck"; 196*724ba675SRob Herring clock-frequency = <0>; 197*724ba675SRob Herring }; 198*724ba675SRob Herring 199*724ba675SRob Herring video1_clkin_ck: clock-video1-clkin { 200*724ba675SRob Herring #clock-cells = <0>; 201*724ba675SRob Herring compatible = "fixed-clock"; 202*724ba675SRob Herring clock-output-names = "video1_clkin_ck"; 203*724ba675SRob Herring clock-frequency = <0>; 204*724ba675SRob Herring }; 205*724ba675SRob Herring 206*724ba675SRob Herring video1_m2_clkin_ck: clock-video1-m2-clkin { 207*724ba675SRob Herring #clock-cells = <0>; 208*724ba675SRob Herring compatible = "fixed-clock"; 209*724ba675SRob Herring clock-output-names = "video1_m2_clkin_ck"; 210*724ba675SRob Herring clock-frequency = <0>; 211*724ba675SRob Herring }; 212*724ba675SRob Herring 213*724ba675SRob Herring video2_clkin_ck: clock-video2-clkin { 214*724ba675SRob Herring #clock-cells = <0>; 215*724ba675SRob Herring compatible = "fixed-clock"; 216*724ba675SRob Herring clock-output-names = "video2_clkin_ck"; 217*724ba675SRob Herring clock-frequency = <0>; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring video2_m2_clkin_ck: clock-video2-m2-clkin { 221*724ba675SRob Herring #clock-cells = <0>; 222*724ba675SRob Herring compatible = "fixed-clock"; 223*724ba675SRob Herring clock-output-names = "video2_m2_clkin_ck"; 224*724ba675SRob Herring clock-frequency = <0>; 225*724ba675SRob Herring }; 226*724ba675SRob Herring 227*724ba675SRob Herring dpll_abe_ck: clock@1e0 { 228*724ba675SRob Herring #clock-cells = <0>; 229*724ba675SRob Herring compatible = "ti,omap4-dpll-m4xen-clock"; 230*724ba675SRob Herring clock-output-names = "dpll_abe_ck"; 231*724ba675SRob Herring clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; 232*724ba675SRob Herring reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 233*724ba675SRob Herring }; 234*724ba675SRob Herring 235*724ba675SRob Herring dpll_abe_x2_ck: clock-dpll-abe-x2 { 236*724ba675SRob Herring #clock-cells = <0>; 237*724ba675SRob Herring compatible = "ti,omap4-dpll-x2-clock"; 238*724ba675SRob Herring clock-output-names = "dpll_abe_x2_ck"; 239*724ba675SRob Herring clocks = <&dpll_abe_ck>; 240*724ba675SRob Herring }; 241*724ba675SRob Herring 242*724ba675SRob Herring dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { 243*724ba675SRob Herring #clock-cells = <0>; 244*724ba675SRob Herring compatible = "ti,divider-clock"; 245*724ba675SRob Herring clock-output-names = "dpll_abe_m2x2_ck"; 246*724ba675SRob Herring clocks = <&dpll_abe_x2_ck>; 247*724ba675SRob Herring ti,max-div = <31>; 248*724ba675SRob Herring ti,autoidle-shift = <8>; 249*724ba675SRob Herring reg = <0x01f0>; 250*724ba675SRob Herring ti,index-starts-at-one; 251*724ba675SRob Herring ti,invert-autoidle-bit; 252*724ba675SRob Herring }; 253*724ba675SRob Herring 254*724ba675SRob Herring abe_clk: clock-abe@108 { 255*724ba675SRob Herring #clock-cells = <0>; 256*724ba675SRob Herring compatible = "ti,divider-clock"; 257*724ba675SRob Herring clock-output-names = "abe_clk"; 258*724ba675SRob Herring clocks = <&dpll_abe_m2x2_ck>; 259*724ba675SRob Herring ti,max-div = <4>; 260*724ba675SRob Herring reg = <0x0108>; 261*724ba675SRob Herring ti,index-power-of-two; 262*724ba675SRob Herring }; 263*724ba675SRob Herring 264*724ba675SRob Herring dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { 265*724ba675SRob Herring #clock-cells = <0>; 266*724ba675SRob Herring compatible = "ti,divider-clock"; 267*724ba675SRob Herring clock-output-names = "dpll_abe_m2_ck"; 268*724ba675SRob Herring clocks = <&dpll_abe_ck>; 269*724ba675SRob Herring ti,max-div = <31>; 270*724ba675SRob Herring ti,autoidle-shift = <8>; 271*724ba675SRob Herring reg = <0x01f0>; 272*724ba675SRob Herring ti,index-starts-at-one; 273*724ba675SRob Herring ti,invert-autoidle-bit; 274*724ba675SRob Herring }; 275*724ba675SRob Herring 276*724ba675SRob Herring dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { 277*724ba675SRob Herring #clock-cells = <0>; 278*724ba675SRob Herring compatible = "ti,divider-clock"; 279*724ba675SRob Herring clock-output-names = "dpll_abe_m3x2_ck"; 280*724ba675SRob Herring clocks = <&dpll_abe_x2_ck>; 281*724ba675SRob Herring ti,max-div = <31>; 282*724ba675SRob Herring ti,autoidle-shift = <8>; 283*724ba675SRob Herring reg = <0x01f4>; 284*724ba675SRob Herring ti,index-starts-at-one; 285*724ba675SRob Herring ti,invert-autoidle-bit; 286*724ba675SRob Herring }; 287*724ba675SRob Herring 288*724ba675SRob Herring dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { 289*724ba675SRob Herring #clock-cells = <0>; 290*724ba675SRob Herring compatible = "ti,mux-clock"; 291*724ba675SRob Herring clock-output-names = "dpll_core_byp_mux"; 292*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 293*724ba675SRob Herring ti,bit-shift = <23>; 294*724ba675SRob Herring reg = <0x012c>; 295*724ba675SRob Herring }; 296*724ba675SRob Herring 297*724ba675SRob Herring dpll_core_ck: clock@120 { 298*724ba675SRob Herring #clock-cells = <0>; 299*724ba675SRob Herring compatible = "ti,omap4-dpll-core-clock"; 300*724ba675SRob Herring clock-output-names = "dpll_core_ck"; 301*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; 302*724ba675SRob Herring reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 303*724ba675SRob Herring }; 304*724ba675SRob Herring 305*724ba675SRob Herring dpll_core_x2_ck: clock-dpll-core-x2 { 306*724ba675SRob Herring #clock-cells = <0>; 307*724ba675SRob Herring compatible = "ti,omap4-dpll-x2-clock"; 308*724ba675SRob Herring clock-output-names = "dpll_core_x2_ck"; 309*724ba675SRob Herring clocks = <&dpll_core_ck>; 310*724ba675SRob Herring }; 311*724ba675SRob Herring 312*724ba675SRob Herring dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { 313*724ba675SRob Herring #clock-cells = <0>; 314*724ba675SRob Herring compatible = "ti,divider-clock"; 315*724ba675SRob Herring clock-output-names = "dpll_core_h12x2_ck"; 316*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 317*724ba675SRob Herring ti,max-div = <63>; 318*724ba675SRob Herring ti,autoidle-shift = <8>; 319*724ba675SRob Herring reg = <0x013c>; 320*724ba675SRob Herring ti,index-starts-at-one; 321*724ba675SRob Herring ti,invert-autoidle-bit; 322*724ba675SRob Herring }; 323*724ba675SRob Herring 324*724ba675SRob Herring mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { 325*724ba675SRob Herring #clock-cells = <0>; 326*724ba675SRob Herring compatible = "fixed-factor-clock"; 327*724ba675SRob Herring clock-output-names = "mpu_dpll_hs_clk_div"; 328*724ba675SRob Herring clocks = <&dpll_core_h12x2_ck>; 329*724ba675SRob Herring clock-mult = <1>; 330*724ba675SRob Herring clock-div = <1>; 331*724ba675SRob Herring }; 332*724ba675SRob Herring 333*724ba675SRob Herring dpll_mpu_ck: clock@160 { 334*724ba675SRob Herring #clock-cells = <0>; 335*724ba675SRob Herring compatible = "ti,omap5-mpu-dpll-clock"; 336*724ba675SRob Herring clock-output-names = "dpll_mpu_ck"; 337*724ba675SRob Herring clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; 338*724ba675SRob Herring reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 339*724ba675SRob Herring }; 340*724ba675SRob Herring 341*724ba675SRob Herring dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { 342*724ba675SRob Herring #clock-cells = <0>; 343*724ba675SRob Herring compatible = "ti,divider-clock"; 344*724ba675SRob Herring clock-output-names = "dpll_mpu_m2_ck"; 345*724ba675SRob Herring clocks = <&dpll_mpu_ck>; 346*724ba675SRob Herring ti,max-div = <31>; 347*724ba675SRob Herring ti,autoidle-shift = <8>; 348*724ba675SRob Herring reg = <0x0170>; 349*724ba675SRob Herring ti,index-starts-at-one; 350*724ba675SRob Herring ti,invert-autoidle-bit; 351*724ba675SRob Herring }; 352*724ba675SRob Herring 353*724ba675SRob Herring mpu_dclk_div: clock-mpu-dclk-div { 354*724ba675SRob Herring #clock-cells = <0>; 355*724ba675SRob Herring compatible = "fixed-factor-clock"; 356*724ba675SRob Herring clock-output-names = "mpu_dclk_div"; 357*724ba675SRob Herring clocks = <&dpll_mpu_m2_ck>; 358*724ba675SRob Herring clock-mult = <1>; 359*724ba675SRob Herring clock-div = <1>; 360*724ba675SRob Herring }; 361*724ba675SRob Herring 362*724ba675SRob Herring dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { 363*724ba675SRob Herring #clock-cells = <0>; 364*724ba675SRob Herring compatible = "fixed-factor-clock"; 365*724ba675SRob Herring clock-output-names = "dsp_dpll_hs_clk_div"; 366*724ba675SRob Herring clocks = <&dpll_core_h12x2_ck>; 367*724ba675SRob Herring clock-mult = <1>; 368*724ba675SRob Herring clock-div = <1>; 369*724ba675SRob Herring }; 370*724ba675SRob Herring 371*724ba675SRob Herring dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { 372*724ba675SRob Herring #clock-cells = <0>; 373*724ba675SRob Herring compatible = "ti,mux-clock"; 374*724ba675SRob Herring clock-output-names = "dpll_dsp_byp_mux"; 375*724ba675SRob Herring clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; 376*724ba675SRob Herring ti,bit-shift = <23>; 377*724ba675SRob Herring reg = <0x0240>; 378*724ba675SRob Herring }; 379*724ba675SRob Herring 380*724ba675SRob Herring dpll_dsp_ck: clock@234 { 381*724ba675SRob Herring #clock-cells = <0>; 382*724ba675SRob Herring compatible = "ti,omap4-dpll-clock"; 383*724ba675SRob Herring clock-output-names = "dpll_dsp_ck"; 384*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; 385*724ba675SRob Herring reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; 386*724ba675SRob Herring assigned-clocks = <&dpll_dsp_ck>; 387*724ba675SRob Herring assigned-clock-rates = <600000000>; 388*724ba675SRob Herring }; 389*724ba675SRob Herring 390*724ba675SRob Herring dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { 391*724ba675SRob Herring #clock-cells = <0>; 392*724ba675SRob Herring compatible = "ti,divider-clock"; 393*724ba675SRob Herring clock-output-names = "dpll_dsp_m2_ck"; 394*724ba675SRob Herring clocks = <&dpll_dsp_ck>; 395*724ba675SRob Herring ti,max-div = <31>; 396*724ba675SRob Herring ti,autoidle-shift = <8>; 397*724ba675SRob Herring reg = <0x0244>; 398*724ba675SRob Herring ti,index-starts-at-one; 399*724ba675SRob Herring ti,invert-autoidle-bit; 400*724ba675SRob Herring assigned-clocks = <&dpll_dsp_m2_ck>; 401*724ba675SRob Herring assigned-clock-rates = <600000000>; 402*724ba675SRob Herring }; 403*724ba675SRob Herring 404*724ba675SRob Herring iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { 405*724ba675SRob Herring #clock-cells = <0>; 406*724ba675SRob Herring compatible = "fixed-factor-clock"; 407*724ba675SRob Herring clock-output-names = "iva_dpll_hs_clk_div"; 408*724ba675SRob Herring clocks = <&dpll_core_h12x2_ck>; 409*724ba675SRob Herring clock-mult = <1>; 410*724ba675SRob Herring clock-div = <1>; 411*724ba675SRob Herring }; 412*724ba675SRob Herring 413*724ba675SRob Herring dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { 414*724ba675SRob Herring #clock-cells = <0>; 415*724ba675SRob Herring compatible = "ti,mux-clock"; 416*724ba675SRob Herring clock-output-names = "dpll_iva_byp_mux"; 417*724ba675SRob Herring clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; 418*724ba675SRob Herring ti,bit-shift = <23>; 419*724ba675SRob Herring reg = <0x01ac>; 420*724ba675SRob Herring }; 421*724ba675SRob Herring 422*724ba675SRob Herring dpll_iva_ck: clock@1a0 { 423*724ba675SRob Herring #clock-cells = <0>; 424*724ba675SRob Herring compatible = "ti,omap4-dpll-clock"; 425*724ba675SRob Herring clock-output-names = "dpll_iva_ck"; 426*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; 427*724ba675SRob Herring reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 428*724ba675SRob Herring assigned-clocks = <&dpll_iva_ck>; 429*724ba675SRob Herring assigned-clock-rates = <1165000000>; 430*724ba675SRob Herring }; 431*724ba675SRob Herring 432*724ba675SRob Herring dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { 433*724ba675SRob Herring #clock-cells = <0>; 434*724ba675SRob Herring compatible = "ti,divider-clock"; 435*724ba675SRob Herring clock-output-names = "dpll_iva_m2_ck"; 436*724ba675SRob Herring clocks = <&dpll_iva_ck>; 437*724ba675SRob Herring ti,max-div = <31>; 438*724ba675SRob Herring ti,autoidle-shift = <8>; 439*724ba675SRob Herring reg = <0x01b0>; 440*724ba675SRob Herring ti,index-starts-at-one; 441*724ba675SRob Herring ti,invert-autoidle-bit; 442*724ba675SRob Herring assigned-clocks = <&dpll_iva_m2_ck>; 443*724ba675SRob Herring assigned-clock-rates = <388333334>; 444*724ba675SRob Herring }; 445*724ba675SRob Herring 446*724ba675SRob Herring iva_dclk: clock-iva-dclk { 447*724ba675SRob Herring #clock-cells = <0>; 448*724ba675SRob Herring compatible = "fixed-factor-clock"; 449*724ba675SRob Herring clock-output-names = "iva_dclk"; 450*724ba675SRob Herring clocks = <&dpll_iva_m2_ck>; 451*724ba675SRob Herring clock-mult = <1>; 452*724ba675SRob Herring clock-div = <1>; 453*724ba675SRob Herring }; 454*724ba675SRob Herring 455*724ba675SRob Herring dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { 456*724ba675SRob Herring #clock-cells = <0>; 457*724ba675SRob Herring compatible = "ti,mux-clock"; 458*724ba675SRob Herring clock-output-names = "dpll_gpu_byp_mux"; 459*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 460*724ba675SRob Herring ti,bit-shift = <23>; 461*724ba675SRob Herring reg = <0x02e4>; 462*724ba675SRob Herring }; 463*724ba675SRob Herring 464*724ba675SRob Herring dpll_gpu_ck: clock@2d8 { 465*724ba675SRob Herring #clock-cells = <0>; 466*724ba675SRob Herring compatible = "ti,omap4-dpll-clock"; 467*724ba675SRob Herring clock-output-names = "dpll_gpu_ck"; 468*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; 469*724ba675SRob Herring reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; 470*724ba675SRob Herring assigned-clocks = <&dpll_gpu_ck>; 471*724ba675SRob Herring assigned-clock-rates = <1277000000>; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { 475*724ba675SRob Herring #clock-cells = <0>; 476*724ba675SRob Herring compatible = "ti,divider-clock"; 477*724ba675SRob Herring clock-output-names = "dpll_gpu_m2_ck"; 478*724ba675SRob Herring clocks = <&dpll_gpu_ck>; 479*724ba675SRob Herring ti,max-div = <31>; 480*724ba675SRob Herring ti,autoidle-shift = <8>; 481*724ba675SRob Herring reg = <0x02e8>; 482*724ba675SRob Herring ti,index-starts-at-one; 483*724ba675SRob Herring ti,invert-autoidle-bit; 484*724ba675SRob Herring assigned-clocks = <&dpll_gpu_m2_ck>; 485*724ba675SRob Herring assigned-clock-rates = <425666667>; 486*724ba675SRob Herring }; 487*724ba675SRob Herring 488*724ba675SRob Herring dpll_core_m2_ck: clock-dpll-core-m2-8@130 { 489*724ba675SRob Herring #clock-cells = <0>; 490*724ba675SRob Herring compatible = "ti,divider-clock"; 491*724ba675SRob Herring clock-output-names = "dpll_core_m2_ck"; 492*724ba675SRob Herring clocks = <&dpll_core_ck>; 493*724ba675SRob Herring ti,max-div = <31>; 494*724ba675SRob Herring ti,autoidle-shift = <8>; 495*724ba675SRob Herring reg = <0x0130>; 496*724ba675SRob Herring ti,index-starts-at-one; 497*724ba675SRob Herring ti,invert-autoidle-bit; 498*724ba675SRob Herring }; 499*724ba675SRob Herring 500*724ba675SRob Herring core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { 501*724ba675SRob Herring #clock-cells = <0>; 502*724ba675SRob Herring compatible = "fixed-factor-clock"; 503*724ba675SRob Herring clock-output-names = "core_dpll_out_dclk_div"; 504*724ba675SRob Herring clocks = <&dpll_core_m2_ck>; 505*724ba675SRob Herring clock-mult = <1>; 506*724ba675SRob Herring clock-div = <1>; 507*724ba675SRob Herring }; 508*724ba675SRob Herring 509*724ba675SRob Herring dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { 510*724ba675SRob Herring #clock-cells = <0>; 511*724ba675SRob Herring compatible = "ti,mux-clock"; 512*724ba675SRob Herring clock-output-names = "dpll_ddr_byp_mux"; 513*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 514*724ba675SRob Herring ti,bit-shift = <23>; 515*724ba675SRob Herring reg = <0x021c>; 516*724ba675SRob Herring }; 517*724ba675SRob Herring 518*724ba675SRob Herring dpll_ddr_ck: clock@210 { 519*724ba675SRob Herring #clock-cells = <0>; 520*724ba675SRob Herring compatible = "ti,omap4-dpll-clock"; 521*724ba675SRob Herring clock-output-names = "dpll_ddr_ck"; 522*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; 523*724ba675SRob Herring reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; 524*724ba675SRob Herring }; 525*724ba675SRob Herring 526*724ba675SRob Herring dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { 527*724ba675SRob Herring #clock-cells = <0>; 528*724ba675SRob Herring compatible = "ti,divider-clock"; 529*724ba675SRob Herring clock-output-names = "dpll_ddr_m2_ck"; 530*724ba675SRob Herring clocks = <&dpll_ddr_ck>; 531*724ba675SRob Herring ti,max-div = <31>; 532*724ba675SRob Herring ti,autoidle-shift = <8>; 533*724ba675SRob Herring reg = <0x0220>; 534*724ba675SRob Herring ti,index-starts-at-one; 535*724ba675SRob Herring ti,invert-autoidle-bit; 536*724ba675SRob Herring }; 537*724ba675SRob Herring 538*724ba675SRob Herring dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { 539*724ba675SRob Herring #clock-cells = <0>; 540*724ba675SRob Herring compatible = "ti,mux-clock"; 541*724ba675SRob Herring clock-output-names = "dpll_gmac_byp_mux"; 542*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; 543*724ba675SRob Herring ti,bit-shift = <23>; 544*724ba675SRob Herring reg = <0x02b4>; 545*724ba675SRob Herring }; 546*724ba675SRob Herring 547*724ba675SRob Herring dpll_gmac_ck: clock@2a8 { 548*724ba675SRob Herring #clock-cells = <0>; 549*724ba675SRob Herring compatible = "ti,omap4-dpll-clock"; 550*724ba675SRob Herring clock-output-names = "dpll_gmac_ck"; 551*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; 552*724ba675SRob Herring reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; 553*724ba675SRob Herring }; 554*724ba675SRob Herring 555*724ba675SRob Herring dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { 556*724ba675SRob Herring #clock-cells = <0>; 557*724ba675SRob Herring compatible = "ti,divider-clock"; 558*724ba675SRob Herring clock-output-names = "dpll_gmac_m2_ck"; 559*724ba675SRob Herring clocks = <&dpll_gmac_ck>; 560*724ba675SRob Herring ti,max-div = <31>; 561*724ba675SRob Herring ti,autoidle-shift = <8>; 562*724ba675SRob Herring reg = <0x02b8>; 563*724ba675SRob Herring ti,index-starts-at-one; 564*724ba675SRob Herring ti,invert-autoidle-bit; 565*724ba675SRob Herring }; 566*724ba675SRob Herring 567*724ba675SRob Herring video2_dclk_div: clock-video2-dclk-div { 568*724ba675SRob Herring #clock-cells = <0>; 569*724ba675SRob Herring compatible = "fixed-factor-clock"; 570*724ba675SRob Herring clock-output-names = "video2_dclk_div"; 571*724ba675SRob Herring clocks = <&video2_m2_clkin_ck>; 572*724ba675SRob Herring clock-mult = <1>; 573*724ba675SRob Herring clock-div = <1>; 574*724ba675SRob Herring }; 575*724ba675SRob Herring 576*724ba675SRob Herring video1_dclk_div: clock-video1-dclk-div { 577*724ba675SRob Herring #clock-cells = <0>; 578*724ba675SRob Herring compatible = "fixed-factor-clock"; 579*724ba675SRob Herring clock-output-names = "video1_dclk_div"; 580*724ba675SRob Herring clocks = <&video1_m2_clkin_ck>; 581*724ba675SRob Herring clock-mult = <1>; 582*724ba675SRob Herring clock-div = <1>; 583*724ba675SRob Herring }; 584*724ba675SRob Herring 585*724ba675SRob Herring hdmi_dclk_div: clock-hdmi-dclk-div { 586*724ba675SRob Herring #clock-cells = <0>; 587*724ba675SRob Herring compatible = "fixed-factor-clock"; 588*724ba675SRob Herring clock-output-names = "hdmi_dclk_div"; 589*724ba675SRob Herring clocks = <&hdmi_clkin_ck>; 590*724ba675SRob Herring clock-mult = <1>; 591*724ba675SRob Herring clock-div = <1>; 592*724ba675SRob Herring }; 593*724ba675SRob Herring 594*724ba675SRob Herring per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { 595*724ba675SRob Herring #clock-cells = <0>; 596*724ba675SRob Herring compatible = "fixed-factor-clock"; 597*724ba675SRob Herring clock-output-names = "per_dpll_hs_clk_div"; 598*724ba675SRob Herring clocks = <&dpll_abe_m3x2_ck>; 599*724ba675SRob Herring clock-mult = <1>; 600*724ba675SRob Herring clock-div = <2>; 601*724ba675SRob Herring }; 602*724ba675SRob Herring 603*724ba675SRob Herring usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { 604*724ba675SRob Herring #clock-cells = <0>; 605*724ba675SRob Herring compatible = "fixed-factor-clock"; 606*724ba675SRob Herring clock-output-names = "usb_dpll_hs_clk_div"; 607*724ba675SRob Herring clocks = <&dpll_abe_m3x2_ck>; 608*724ba675SRob Herring clock-mult = <1>; 609*724ba675SRob Herring clock-div = <3>; 610*724ba675SRob Herring }; 611*724ba675SRob Herring 612*724ba675SRob Herring eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { 613*724ba675SRob Herring #clock-cells = <0>; 614*724ba675SRob Herring compatible = "fixed-factor-clock"; 615*724ba675SRob Herring clock-output-names = "eve_dpll_hs_clk_div"; 616*724ba675SRob Herring clocks = <&dpll_core_h12x2_ck>; 617*724ba675SRob Herring clock-mult = <1>; 618*724ba675SRob Herring clock-div = <1>; 619*724ba675SRob Herring }; 620*724ba675SRob Herring 621*724ba675SRob Herring dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { 622*724ba675SRob Herring #clock-cells = <0>; 623*724ba675SRob Herring compatible = "ti,mux-clock"; 624*724ba675SRob Herring clock-output-names = "dpll_eve_byp_mux"; 625*724ba675SRob Herring clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; 626*724ba675SRob Herring ti,bit-shift = <23>; 627*724ba675SRob Herring reg = <0x0290>; 628*724ba675SRob Herring }; 629*724ba675SRob Herring 630*724ba675SRob Herring dpll_eve_ck: clock@284 { 631*724ba675SRob Herring #clock-cells = <0>; 632*724ba675SRob Herring compatible = "ti,omap4-dpll-clock"; 633*724ba675SRob Herring clock-output-names = "dpll_eve_ck"; 634*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; 635*724ba675SRob Herring reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; 636*724ba675SRob Herring }; 637*724ba675SRob Herring 638*724ba675SRob Herring dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { 639*724ba675SRob Herring #clock-cells = <0>; 640*724ba675SRob Herring compatible = "ti,divider-clock"; 641*724ba675SRob Herring clock-output-names = "dpll_eve_m2_ck"; 642*724ba675SRob Herring clocks = <&dpll_eve_ck>; 643*724ba675SRob Herring ti,max-div = <31>; 644*724ba675SRob Herring ti,autoidle-shift = <8>; 645*724ba675SRob Herring reg = <0x0294>; 646*724ba675SRob Herring ti,index-starts-at-one; 647*724ba675SRob Herring ti,invert-autoidle-bit; 648*724ba675SRob Herring }; 649*724ba675SRob Herring 650*724ba675SRob Herring eve_dclk_div: clock-eve-dclk-div { 651*724ba675SRob Herring #clock-cells = <0>; 652*724ba675SRob Herring compatible = "fixed-factor-clock"; 653*724ba675SRob Herring clock-output-names = "eve_dclk_div"; 654*724ba675SRob Herring clocks = <&dpll_eve_m2_ck>; 655*724ba675SRob Herring clock-mult = <1>; 656*724ba675SRob Herring clock-div = <1>; 657*724ba675SRob Herring }; 658*724ba675SRob Herring 659*724ba675SRob Herring dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { 660*724ba675SRob Herring #clock-cells = <0>; 661*724ba675SRob Herring compatible = "ti,divider-clock"; 662*724ba675SRob Herring clock-output-names = "dpll_core_h13x2_ck"; 663*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 664*724ba675SRob Herring ti,max-div = <63>; 665*724ba675SRob Herring ti,autoidle-shift = <8>; 666*724ba675SRob Herring reg = <0x0140>; 667*724ba675SRob Herring ti,index-starts-at-one; 668*724ba675SRob Herring ti,invert-autoidle-bit; 669*724ba675SRob Herring }; 670*724ba675SRob Herring 671*724ba675SRob Herring dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { 672*724ba675SRob Herring #clock-cells = <0>; 673*724ba675SRob Herring compatible = "ti,divider-clock"; 674*724ba675SRob Herring clock-output-names = "dpll_core_h14x2_ck"; 675*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 676*724ba675SRob Herring ti,max-div = <63>; 677*724ba675SRob Herring ti,autoidle-shift = <8>; 678*724ba675SRob Herring reg = <0x0144>; 679*724ba675SRob Herring ti,index-starts-at-one; 680*724ba675SRob Herring ti,invert-autoidle-bit; 681*724ba675SRob Herring }; 682*724ba675SRob Herring 683*724ba675SRob Herring dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { 684*724ba675SRob Herring #clock-cells = <0>; 685*724ba675SRob Herring compatible = "ti,divider-clock"; 686*724ba675SRob Herring clock-output-names = "dpll_core_h22x2_ck"; 687*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 688*724ba675SRob Herring ti,max-div = <63>; 689*724ba675SRob Herring ti,autoidle-shift = <8>; 690*724ba675SRob Herring reg = <0x0154>; 691*724ba675SRob Herring ti,index-starts-at-one; 692*724ba675SRob Herring ti,invert-autoidle-bit; 693*724ba675SRob Herring }; 694*724ba675SRob Herring 695*724ba675SRob Herring dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { 696*724ba675SRob Herring #clock-cells = <0>; 697*724ba675SRob Herring compatible = "ti,divider-clock"; 698*724ba675SRob Herring clock-output-names = "dpll_core_h23x2_ck"; 699*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 700*724ba675SRob Herring ti,max-div = <63>; 701*724ba675SRob Herring ti,autoidle-shift = <8>; 702*724ba675SRob Herring reg = <0x0158>; 703*724ba675SRob Herring ti,index-starts-at-one; 704*724ba675SRob Herring ti,invert-autoidle-bit; 705*724ba675SRob Herring }; 706*724ba675SRob Herring 707*724ba675SRob Herring dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { 708*724ba675SRob Herring #clock-cells = <0>; 709*724ba675SRob Herring compatible = "ti,divider-clock"; 710*724ba675SRob Herring clock-output-names = "dpll_core_h24x2_ck"; 711*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 712*724ba675SRob Herring ti,max-div = <63>; 713*724ba675SRob Herring ti,autoidle-shift = <8>; 714*724ba675SRob Herring reg = <0x015c>; 715*724ba675SRob Herring ti,index-starts-at-one; 716*724ba675SRob Herring ti,invert-autoidle-bit; 717*724ba675SRob Herring }; 718*724ba675SRob Herring 719*724ba675SRob Herring dpll_ddr_x2_ck: clock-dpll-ddr-x2 { 720*724ba675SRob Herring #clock-cells = <0>; 721*724ba675SRob Herring compatible = "ti,omap4-dpll-x2-clock"; 722*724ba675SRob Herring clock-output-names = "dpll_ddr_x2_ck"; 723*724ba675SRob Herring clocks = <&dpll_ddr_ck>; 724*724ba675SRob Herring }; 725*724ba675SRob Herring 726*724ba675SRob Herring dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { 727*724ba675SRob Herring #clock-cells = <0>; 728*724ba675SRob Herring compatible = "ti,divider-clock"; 729*724ba675SRob Herring clock-output-names = "dpll_ddr_h11x2_ck"; 730*724ba675SRob Herring clocks = <&dpll_ddr_x2_ck>; 731*724ba675SRob Herring ti,max-div = <63>; 732*724ba675SRob Herring ti,autoidle-shift = <8>; 733*724ba675SRob Herring reg = <0x0228>; 734*724ba675SRob Herring ti,index-starts-at-one; 735*724ba675SRob Herring ti,invert-autoidle-bit; 736*724ba675SRob Herring }; 737*724ba675SRob Herring 738*724ba675SRob Herring dpll_dsp_x2_ck: clock-dpll-dsp-x2 { 739*724ba675SRob Herring #clock-cells = <0>; 740*724ba675SRob Herring compatible = "ti,omap4-dpll-x2-clock"; 741*724ba675SRob Herring clock-output-names = "dpll_dsp_x2_ck"; 742*724ba675SRob Herring clocks = <&dpll_dsp_ck>; 743*724ba675SRob Herring }; 744*724ba675SRob Herring 745*724ba675SRob Herring dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { 746*724ba675SRob Herring #clock-cells = <0>; 747*724ba675SRob Herring compatible = "ti,divider-clock"; 748*724ba675SRob Herring clock-output-names = "dpll_dsp_m3x2_ck"; 749*724ba675SRob Herring clocks = <&dpll_dsp_x2_ck>; 750*724ba675SRob Herring ti,max-div = <31>; 751*724ba675SRob Herring ti,autoidle-shift = <8>; 752*724ba675SRob Herring reg = <0x0248>; 753*724ba675SRob Herring ti,index-starts-at-one; 754*724ba675SRob Herring ti,invert-autoidle-bit; 755*724ba675SRob Herring assigned-clocks = <&dpll_dsp_m3x2_ck>; 756*724ba675SRob Herring assigned-clock-rates = <400000000>; 757*724ba675SRob Herring }; 758*724ba675SRob Herring 759*724ba675SRob Herring dpll_gmac_x2_ck: clock-dpll-gmac-x2 { 760*724ba675SRob Herring #clock-cells = <0>; 761*724ba675SRob Herring compatible = "ti,omap4-dpll-x2-clock"; 762*724ba675SRob Herring clock-output-names = "dpll_gmac_x2_ck"; 763*724ba675SRob Herring clocks = <&dpll_gmac_ck>; 764*724ba675SRob Herring }; 765*724ba675SRob Herring 766*724ba675SRob Herring dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { 767*724ba675SRob Herring #clock-cells = <0>; 768*724ba675SRob Herring compatible = "ti,divider-clock"; 769*724ba675SRob Herring clock-output-names = "dpll_gmac_h11x2_ck"; 770*724ba675SRob Herring clocks = <&dpll_gmac_x2_ck>; 771*724ba675SRob Herring ti,max-div = <63>; 772*724ba675SRob Herring ti,autoidle-shift = <8>; 773*724ba675SRob Herring reg = <0x02c0>; 774*724ba675SRob Herring ti,index-starts-at-one; 775*724ba675SRob Herring ti,invert-autoidle-bit; 776*724ba675SRob Herring }; 777*724ba675SRob Herring 778*724ba675SRob Herring dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { 779*724ba675SRob Herring #clock-cells = <0>; 780*724ba675SRob Herring compatible = "ti,divider-clock"; 781*724ba675SRob Herring clock-output-names = "dpll_gmac_h12x2_ck"; 782*724ba675SRob Herring clocks = <&dpll_gmac_x2_ck>; 783*724ba675SRob Herring ti,max-div = <63>; 784*724ba675SRob Herring ti,autoidle-shift = <8>; 785*724ba675SRob Herring reg = <0x02c4>; 786*724ba675SRob Herring ti,index-starts-at-one; 787*724ba675SRob Herring ti,invert-autoidle-bit; 788*724ba675SRob Herring }; 789*724ba675SRob Herring 790*724ba675SRob Herring dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { 791*724ba675SRob Herring #clock-cells = <0>; 792*724ba675SRob Herring compatible = "ti,divider-clock"; 793*724ba675SRob Herring clock-output-names = "dpll_gmac_h13x2_ck"; 794*724ba675SRob Herring clocks = <&dpll_gmac_x2_ck>; 795*724ba675SRob Herring ti,max-div = <63>; 796*724ba675SRob Herring ti,autoidle-shift = <8>; 797*724ba675SRob Herring reg = <0x02c8>; 798*724ba675SRob Herring ti,index-starts-at-one; 799*724ba675SRob Herring ti,invert-autoidle-bit; 800*724ba675SRob Herring }; 801*724ba675SRob Herring 802*724ba675SRob Herring dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { 803*724ba675SRob Herring #clock-cells = <0>; 804*724ba675SRob Herring compatible = "ti,divider-clock"; 805*724ba675SRob Herring clock-output-names = "dpll_gmac_m3x2_ck"; 806*724ba675SRob Herring clocks = <&dpll_gmac_x2_ck>; 807*724ba675SRob Herring ti,max-div = <31>; 808*724ba675SRob Herring ti,autoidle-shift = <8>; 809*724ba675SRob Herring reg = <0x02bc>; 810*724ba675SRob Herring ti,index-starts-at-one; 811*724ba675SRob Herring ti,invert-autoidle-bit; 812*724ba675SRob Herring }; 813*724ba675SRob Herring 814*724ba675SRob Herring gmii_m_clk_div: clock-gmii-m-clk-div { 815*724ba675SRob Herring #clock-cells = <0>; 816*724ba675SRob Herring compatible = "fixed-factor-clock"; 817*724ba675SRob Herring clock-output-names = "gmii_m_clk_div"; 818*724ba675SRob Herring clocks = <&dpll_gmac_h11x2_ck>; 819*724ba675SRob Herring clock-mult = <1>; 820*724ba675SRob Herring clock-div = <2>; 821*724ba675SRob Herring }; 822*724ba675SRob Herring 823*724ba675SRob Herring hdmi_clk2_div: clock-hdmi-clk2-div { 824*724ba675SRob Herring #clock-cells = <0>; 825*724ba675SRob Herring compatible = "fixed-factor-clock"; 826*724ba675SRob Herring clock-output-names = "hdmi_clk2_div"; 827*724ba675SRob Herring clocks = <&hdmi_clkin_ck>; 828*724ba675SRob Herring clock-mult = <1>; 829*724ba675SRob Herring clock-div = <1>; 830*724ba675SRob Herring }; 831*724ba675SRob Herring 832*724ba675SRob Herring hdmi_div_clk: clock-hdmi-div { 833*724ba675SRob Herring #clock-cells = <0>; 834*724ba675SRob Herring compatible = "fixed-factor-clock"; 835*724ba675SRob Herring clock-output-names = "hdmi_div_clk"; 836*724ba675SRob Herring clocks = <&hdmi_clkin_ck>; 837*724ba675SRob Herring clock-mult = <1>; 838*724ba675SRob Herring clock-div = <1>; 839*724ba675SRob Herring }; 840*724ba675SRob Herring 841*724ba675SRob Herring l3_iclk_div: clock-l3-iclk-div-4@100 { 842*724ba675SRob Herring #clock-cells = <0>; 843*724ba675SRob Herring compatible = "ti,divider-clock"; 844*724ba675SRob Herring clock-output-names = "l3_iclk_div"; 845*724ba675SRob Herring ti,max-div = <2>; 846*724ba675SRob Herring ti,bit-shift = <4>; 847*724ba675SRob Herring reg = <0x0100>; 848*724ba675SRob Herring clocks = <&dpll_core_h12x2_ck>; 849*724ba675SRob Herring ti,index-power-of-two; 850*724ba675SRob Herring }; 851*724ba675SRob Herring 852*724ba675SRob Herring l4_root_clk_div: clock-l4-root-clk-div { 853*724ba675SRob Herring #clock-cells = <0>; 854*724ba675SRob Herring compatible = "fixed-factor-clock"; 855*724ba675SRob Herring clock-output-names = "l4_root_clk_div"; 856*724ba675SRob Herring clocks = <&l3_iclk_div>; 857*724ba675SRob Herring clock-mult = <1>; 858*724ba675SRob Herring clock-div = <2>; 859*724ba675SRob Herring }; 860*724ba675SRob Herring 861*724ba675SRob Herring video1_clk2_div: clock-video1-clk2-div { 862*724ba675SRob Herring #clock-cells = <0>; 863*724ba675SRob Herring compatible = "fixed-factor-clock"; 864*724ba675SRob Herring clock-output-names = "video1_clk2_div"; 865*724ba675SRob Herring clocks = <&video1_clkin_ck>; 866*724ba675SRob Herring clock-mult = <1>; 867*724ba675SRob Herring clock-div = <1>; 868*724ba675SRob Herring }; 869*724ba675SRob Herring 870*724ba675SRob Herring video1_div_clk: clock-video1-div { 871*724ba675SRob Herring #clock-cells = <0>; 872*724ba675SRob Herring compatible = "fixed-factor-clock"; 873*724ba675SRob Herring clock-output-names = "video1_div_clk"; 874*724ba675SRob Herring clocks = <&video1_clkin_ck>; 875*724ba675SRob Herring clock-mult = <1>; 876*724ba675SRob Herring clock-div = <1>; 877*724ba675SRob Herring }; 878*724ba675SRob Herring 879*724ba675SRob Herring video2_clk2_div: clock-video2-clk2-div { 880*724ba675SRob Herring #clock-cells = <0>; 881*724ba675SRob Herring compatible = "fixed-factor-clock"; 882*724ba675SRob Herring clock-output-names = "video2_clk2_div"; 883*724ba675SRob Herring clocks = <&video2_clkin_ck>; 884*724ba675SRob Herring clock-mult = <1>; 885*724ba675SRob Herring clock-div = <1>; 886*724ba675SRob Herring }; 887*724ba675SRob Herring 888*724ba675SRob Herring video2_div_clk: clock-video2-div { 889*724ba675SRob Herring #clock-cells = <0>; 890*724ba675SRob Herring compatible = "fixed-factor-clock"; 891*724ba675SRob Herring clock-output-names = "video2_div_clk"; 892*724ba675SRob Herring clocks = <&video2_clkin_ck>; 893*724ba675SRob Herring clock-mult = <1>; 894*724ba675SRob Herring clock-div = <1>; 895*724ba675SRob Herring }; 896*724ba675SRob Herring 897*724ba675SRob Herring dummy_ck: clock-dummy { 898*724ba675SRob Herring #clock-cells = <0>; 899*724ba675SRob Herring compatible = "fixed-clock"; 900*724ba675SRob Herring clock-output-names = "dummy_ck"; 901*724ba675SRob Herring clock-frequency = <0>; 902*724ba675SRob Herring }; 903*724ba675SRob Herring}; 904*724ba675SRob Herring&prm_clocks { 905*724ba675SRob Herring sys_clkin1: clock-sys-clkin1@110 { 906*724ba675SRob Herring #clock-cells = <0>; 907*724ba675SRob Herring compatible = "ti,mux-clock"; 908*724ba675SRob Herring clock-output-names = "sys_clkin1"; 909*724ba675SRob Herring clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 910*724ba675SRob Herring reg = <0x0110>; 911*724ba675SRob Herring ti,index-starts-at-one; 912*724ba675SRob Herring }; 913*724ba675SRob Herring 914*724ba675SRob Herring abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { 915*724ba675SRob Herring #clock-cells = <0>; 916*724ba675SRob Herring compatible = "ti,mux-clock"; 917*724ba675SRob Herring clock-output-names = "abe_dpll_sys_clk_mux"; 918*724ba675SRob Herring clocks = <&sys_clkin1>, <&sys_clkin2>; 919*724ba675SRob Herring reg = <0x0118>; 920*724ba675SRob Herring }; 921*724ba675SRob Herring 922*724ba675SRob Herring abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { 923*724ba675SRob Herring #clock-cells = <0>; 924*724ba675SRob Herring compatible = "ti,mux-clock"; 925*724ba675SRob Herring clock-output-names = "abe_dpll_bypass_clk_mux"; 926*724ba675SRob Herring clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; 927*724ba675SRob Herring reg = <0x0114>; 928*724ba675SRob Herring }; 929*724ba675SRob Herring 930*724ba675SRob Herring abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { 931*724ba675SRob Herring #clock-cells = <0>; 932*724ba675SRob Herring compatible = "ti,mux-clock"; 933*724ba675SRob Herring clock-output-names = "abe_dpll_clk_mux"; 934*724ba675SRob Herring clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; 935*724ba675SRob Herring reg = <0x010c>; 936*724ba675SRob Herring }; 937*724ba675SRob Herring 938*724ba675SRob Herring abe_24m_fclk: clock-abe-24m@11c { 939*724ba675SRob Herring #clock-cells = <0>; 940*724ba675SRob Herring compatible = "ti,divider-clock"; 941*724ba675SRob Herring clock-output-names = "abe_24m_fclk"; 942*724ba675SRob Herring clocks = <&dpll_abe_m2x2_ck>; 943*724ba675SRob Herring reg = <0x011c>; 944*724ba675SRob Herring ti,dividers = <8>, <16>; 945*724ba675SRob Herring }; 946*724ba675SRob Herring 947*724ba675SRob Herring aess_fclk: clock-aess@178 { 948*724ba675SRob Herring #clock-cells = <0>; 949*724ba675SRob Herring compatible = "ti,divider-clock"; 950*724ba675SRob Herring clock-output-names = "aess_fclk"; 951*724ba675SRob Herring clocks = <&abe_clk>; 952*724ba675SRob Herring reg = <0x0178>; 953*724ba675SRob Herring ti,max-div = <2>; 954*724ba675SRob Herring }; 955*724ba675SRob Herring 956*724ba675SRob Herring abe_giclk_div: clock-abe-giclk-div@174 { 957*724ba675SRob Herring #clock-cells = <0>; 958*724ba675SRob Herring compatible = "ti,divider-clock"; 959*724ba675SRob Herring clock-output-names = "abe_giclk_div"; 960*724ba675SRob Herring clocks = <&aess_fclk>; 961*724ba675SRob Herring reg = <0x0174>; 962*724ba675SRob Herring ti,max-div = <2>; 963*724ba675SRob Herring }; 964*724ba675SRob Herring 965*724ba675SRob Herring abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { 966*724ba675SRob Herring #clock-cells = <0>; 967*724ba675SRob Herring compatible = "ti,divider-clock"; 968*724ba675SRob Herring clock-output-names = "abe_lp_clk_div"; 969*724ba675SRob Herring clocks = <&dpll_abe_m2x2_ck>; 970*724ba675SRob Herring reg = <0x01d8>; 971*724ba675SRob Herring ti,dividers = <16>, <32>; 972*724ba675SRob Herring }; 973*724ba675SRob Herring 974*724ba675SRob Herring abe_sys_clk_div: clock-abe-sys-clk-div@120 { 975*724ba675SRob Herring #clock-cells = <0>; 976*724ba675SRob Herring compatible = "ti,divider-clock"; 977*724ba675SRob Herring clock-output-names = "abe_sys_clk_div"; 978*724ba675SRob Herring clocks = <&sys_clkin1>; 979*724ba675SRob Herring reg = <0x0120>; 980*724ba675SRob Herring ti,max-div = <2>; 981*724ba675SRob Herring }; 982*724ba675SRob Herring 983*724ba675SRob Herring adc_gfclk_mux: clock-adc-gfclk-mux@1dc { 984*724ba675SRob Herring #clock-cells = <0>; 985*724ba675SRob Herring compatible = "ti,mux-clock"; 986*724ba675SRob Herring clock-output-names = "adc_gfclk_mux"; 987*724ba675SRob Herring clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; 988*724ba675SRob Herring reg = <0x01dc>; 989*724ba675SRob Herring }; 990*724ba675SRob Herring 991*724ba675SRob Herring sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { 992*724ba675SRob Herring #clock-cells = <0>; 993*724ba675SRob Herring compatible = "ti,divider-clock"; 994*724ba675SRob Herring clock-output-names = "sys_clk1_dclk_div"; 995*724ba675SRob Herring clocks = <&sys_clkin1>; 996*724ba675SRob Herring ti,max-div = <64>; 997*724ba675SRob Herring reg = <0x01c8>; 998*724ba675SRob Herring ti,index-power-of-two; 999*724ba675SRob Herring }; 1000*724ba675SRob Herring 1001*724ba675SRob Herring sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { 1002*724ba675SRob Herring #clock-cells = <0>; 1003*724ba675SRob Herring compatible = "ti,divider-clock"; 1004*724ba675SRob Herring clock-output-names = "sys_clk2_dclk_div"; 1005*724ba675SRob Herring clocks = <&sys_clkin2>; 1006*724ba675SRob Herring ti,max-div = <64>; 1007*724ba675SRob Herring reg = <0x01cc>; 1008*724ba675SRob Herring ti,index-power-of-two; 1009*724ba675SRob Herring }; 1010*724ba675SRob Herring 1011*724ba675SRob Herring per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { 1012*724ba675SRob Herring #clock-cells = <0>; 1013*724ba675SRob Herring compatible = "ti,divider-clock"; 1014*724ba675SRob Herring clock-output-names = "per_abe_x1_dclk_div"; 1015*724ba675SRob Herring clocks = <&dpll_abe_m2_ck>; 1016*724ba675SRob Herring ti,max-div = <64>; 1017*724ba675SRob Herring reg = <0x01bc>; 1018*724ba675SRob Herring ti,index-power-of-two; 1019*724ba675SRob Herring }; 1020*724ba675SRob Herring 1021*724ba675SRob Herring dsp_gclk_div: clock-dsp-gclk-div@18c { 1022*724ba675SRob Herring #clock-cells = <0>; 1023*724ba675SRob Herring compatible = "ti,divider-clock"; 1024*724ba675SRob Herring clock-output-names = "dsp_gclk_div"; 1025*724ba675SRob Herring clocks = <&dpll_dsp_m2_ck>; 1026*724ba675SRob Herring ti,max-div = <64>; 1027*724ba675SRob Herring reg = <0x018c>; 1028*724ba675SRob Herring ti,index-power-of-two; 1029*724ba675SRob Herring }; 1030*724ba675SRob Herring 1031*724ba675SRob Herring gpu_dclk: clock-gpu-dclk@1a0 { 1032*724ba675SRob Herring #clock-cells = <0>; 1033*724ba675SRob Herring compatible = "ti,divider-clock"; 1034*724ba675SRob Herring clock-output-names = "gpu_dclk"; 1035*724ba675SRob Herring clocks = <&dpll_gpu_m2_ck>; 1036*724ba675SRob Herring ti,max-div = <64>; 1037*724ba675SRob Herring reg = <0x01a0>; 1038*724ba675SRob Herring ti,index-power-of-two; 1039*724ba675SRob Herring }; 1040*724ba675SRob Herring 1041*724ba675SRob Herring emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { 1042*724ba675SRob Herring #clock-cells = <0>; 1043*724ba675SRob Herring compatible = "ti,divider-clock"; 1044*724ba675SRob Herring clock-output-names = "emif_phy_dclk_div"; 1045*724ba675SRob Herring clocks = <&dpll_ddr_m2_ck>; 1046*724ba675SRob Herring ti,max-div = <64>; 1047*724ba675SRob Herring reg = <0x0190>; 1048*724ba675SRob Herring ti,index-power-of-two; 1049*724ba675SRob Herring }; 1050*724ba675SRob Herring 1051*724ba675SRob Herring gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { 1052*724ba675SRob Herring #clock-cells = <0>; 1053*724ba675SRob Herring compatible = "ti,divider-clock"; 1054*724ba675SRob Herring clock-output-names = "gmac_250m_dclk_div"; 1055*724ba675SRob Herring clocks = <&dpll_gmac_m2_ck>; 1056*724ba675SRob Herring ti,max-div = <64>; 1057*724ba675SRob Herring reg = <0x019c>; 1058*724ba675SRob Herring ti,index-power-of-two; 1059*724ba675SRob Herring }; 1060*724ba675SRob Herring 1061*724ba675SRob Herring gmac_main_clk: clock-gmac-main { 1062*724ba675SRob Herring #clock-cells = <0>; 1063*724ba675SRob Herring compatible = "fixed-factor-clock"; 1064*724ba675SRob Herring clock-output-names = "gmac_main_clk"; 1065*724ba675SRob Herring clocks = <&gmac_250m_dclk_div>; 1066*724ba675SRob Herring clock-mult = <1>; 1067*724ba675SRob Herring clock-div = <2>; 1068*724ba675SRob Herring }; 1069*724ba675SRob Herring 1070*724ba675SRob Herring l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { 1071*724ba675SRob Herring #clock-cells = <0>; 1072*724ba675SRob Herring compatible = "ti,divider-clock"; 1073*724ba675SRob Herring clock-output-names = "l3init_480m_dclk_div"; 1074*724ba675SRob Herring clocks = <&dpll_usb_m2_ck>; 1075*724ba675SRob Herring ti,max-div = <64>; 1076*724ba675SRob Herring reg = <0x01ac>; 1077*724ba675SRob Herring ti,index-power-of-two; 1078*724ba675SRob Herring }; 1079*724ba675SRob Herring 1080*724ba675SRob Herring usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { 1081*724ba675SRob Herring #clock-cells = <0>; 1082*724ba675SRob Herring compatible = "ti,divider-clock"; 1083*724ba675SRob Herring clock-output-names = "usb_otg_dclk_div"; 1084*724ba675SRob Herring clocks = <&usb_otg_clkin_ck>; 1085*724ba675SRob Herring ti,max-div = <64>; 1086*724ba675SRob Herring reg = <0x0184>; 1087*724ba675SRob Herring ti,index-power-of-two; 1088*724ba675SRob Herring }; 1089*724ba675SRob Herring 1090*724ba675SRob Herring sata_dclk_div: clock-sata-dclk-div@1c0 { 1091*724ba675SRob Herring #clock-cells = <0>; 1092*724ba675SRob Herring compatible = "ti,divider-clock"; 1093*724ba675SRob Herring clock-output-names = "sata_dclk_div"; 1094*724ba675SRob Herring clocks = <&sys_clkin1>; 1095*724ba675SRob Herring ti,max-div = <64>; 1096*724ba675SRob Herring reg = <0x01c0>; 1097*724ba675SRob Herring ti,index-power-of-two; 1098*724ba675SRob Herring }; 1099*724ba675SRob Herring 1100*724ba675SRob Herring pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { 1101*724ba675SRob Herring #clock-cells = <0>; 1102*724ba675SRob Herring compatible = "ti,divider-clock"; 1103*724ba675SRob Herring clock-output-names = "pcie2_dclk_div"; 1104*724ba675SRob Herring clocks = <&dpll_pcie_ref_m2_ck>; 1105*724ba675SRob Herring ti,max-div = <64>; 1106*724ba675SRob Herring reg = <0x01b8>; 1107*724ba675SRob Herring ti,index-power-of-two; 1108*724ba675SRob Herring }; 1109*724ba675SRob Herring 1110*724ba675SRob Herring pcie_dclk_div: clock-pcie-dclk-div@1b4 { 1111*724ba675SRob Herring #clock-cells = <0>; 1112*724ba675SRob Herring compatible = "ti,divider-clock"; 1113*724ba675SRob Herring clock-output-names = "pcie_dclk_div"; 1114*724ba675SRob Herring clocks = <&apll_pcie_m2_ck>; 1115*724ba675SRob Herring ti,max-div = <64>; 1116*724ba675SRob Herring reg = <0x01b4>; 1117*724ba675SRob Herring ti,index-power-of-two; 1118*724ba675SRob Herring }; 1119*724ba675SRob Herring 1120*724ba675SRob Herring emu_dclk_div: clock-emu-dclk-div@194 { 1121*724ba675SRob Herring #clock-cells = <0>; 1122*724ba675SRob Herring compatible = "ti,divider-clock"; 1123*724ba675SRob Herring clock-output-names = "emu_dclk_div"; 1124*724ba675SRob Herring clocks = <&sys_clkin1>; 1125*724ba675SRob Herring ti,max-div = <64>; 1126*724ba675SRob Herring reg = <0x0194>; 1127*724ba675SRob Herring ti,index-power-of-two; 1128*724ba675SRob Herring }; 1129*724ba675SRob Herring 1130*724ba675SRob Herring secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { 1131*724ba675SRob Herring #clock-cells = <0>; 1132*724ba675SRob Herring compatible = "ti,divider-clock"; 1133*724ba675SRob Herring clock-output-names = "secure_32k_dclk_div"; 1134*724ba675SRob Herring clocks = <&secure_32k_clk_src_ck>; 1135*724ba675SRob Herring ti,max-div = <64>; 1136*724ba675SRob Herring reg = <0x01c4>; 1137*724ba675SRob Herring ti,index-power-of-two; 1138*724ba675SRob Herring }; 1139*724ba675SRob Herring 1140*724ba675SRob Herring clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { 1141*724ba675SRob Herring #clock-cells = <0>; 1142*724ba675SRob Herring compatible = "ti,mux-clock"; 1143*724ba675SRob Herring clock-output-names = "clkoutmux0_clk_mux"; 1144*724ba675SRob Herring clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1145*724ba675SRob Herring reg = <0x0158>; 1146*724ba675SRob Herring }; 1147*724ba675SRob Herring 1148*724ba675SRob Herring clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { 1149*724ba675SRob Herring #clock-cells = <0>; 1150*724ba675SRob Herring compatible = "ti,mux-clock"; 1151*724ba675SRob Herring clock-output-names = "clkoutmux1_clk_mux"; 1152*724ba675SRob Herring clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1153*724ba675SRob Herring reg = <0x015c>; 1154*724ba675SRob Herring }; 1155*724ba675SRob Herring 1156*724ba675SRob Herring clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { 1157*724ba675SRob Herring #clock-cells = <0>; 1158*724ba675SRob Herring compatible = "ti,mux-clock"; 1159*724ba675SRob Herring clock-output-names = "clkoutmux2_clk_mux"; 1160*724ba675SRob Herring clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; 1161*724ba675SRob Herring reg = <0x0160>; 1162*724ba675SRob Herring }; 1163*724ba675SRob Herring 1164*724ba675SRob Herring custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { 1165*724ba675SRob Herring #clock-cells = <0>; 1166*724ba675SRob Herring compatible = "fixed-factor-clock"; 1167*724ba675SRob Herring clock-output-names = "custefuse_sys_gfclk_div"; 1168*724ba675SRob Herring clocks = <&sys_clkin1>; 1169*724ba675SRob Herring clock-mult = <1>; 1170*724ba675SRob Herring clock-div = <2>; 1171*724ba675SRob Herring }; 1172*724ba675SRob Herring 1173*724ba675SRob Herring eve_clk: clock-eve@180 { 1174*724ba675SRob Herring #clock-cells = <0>; 1175*724ba675SRob Herring compatible = "ti,mux-clock"; 1176*724ba675SRob Herring clock-output-names = "eve_clk"; 1177*724ba675SRob Herring clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; 1178*724ba675SRob Herring reg = <0x0180>; 1179*724ba675SRob Herring }; 1180*724ba675SRob Herring 1181*724ba675SRob Herring hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { 1182*724ba675SRob Herring #clock-cells = <0>; 1183*724ba675SRob Herring compatible = "ti,mux-clock"; 1184*724ba675SRob Herring clock-output-names = "hdmi_dpll_clk_mux"; 1185*724ba675SRob Herring clocks = <&sys_clkin1>, <&sys_clkin2>; 1186*724ba675SRob Herring reg = <0x0164>; 1187*724ba675SRob Herring }; 1188*724ba675SRob Herring 1189*724ba675SRob Herring mlb_clk: clock-mlb@134 { 1190*724ba675SRob Herring #clock-cells = <0>; 1191*724ba675SRob Herring compatible = "ti,divider-clock"; 1192*724ba675SRob Herring clock-output-names = "mlb_clk"; 1193*724ba675SRob Herring clocks = <&mlb_clkin_ck>; 1194*724ba675SRob Herring ti,max-div = <64>; 1195*724ba675SRob Herring reg = <0x0134>; 1196*724ba675SRob Herring ti,index-power-of-two; 1197*724ba675SRob Herring }; 1198*724ba675SRob Herring 1199*724ba675SRob Herring mlbp_clk: clock-mlbp@130 { 1200*724ba675SRob Herring #clock-cells = <0>; 1201*724ba675SRob Herring compatible = "ti,divider-clock"; 1202*724ba675SRob Herring clock-output-names = "mlbp_clk"; 1203*724ba675SRob Herring clocks = <&mlbp_clkin_ck>; 1204*724ba675SRob Herring ti,max-div = <64>; 1205*724ba675SRob Herring reg = <0x0130>; 1206*724ba675SRob Herring ti,index-power-of-two; 1207*724ba675SRob Herring }; 1208*724ba675SRob Herring 1209*724ba675SRob Herring per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { 1210*724ba675SRob Herring #clock-cells = <0>; 1211*724ba675SRob Herring compatible = "ti,divider-clock"; 1212*724ba675SRob Herring clock-output-names = "per_abe_x1_gfclk2_div"; 1213*724ba675SRob Herring clocks = <&dpll_abe_m2_ck>; 1214*724ba675SRob Herring ti,max-div = <64>; 1215*724ba675SRob Herring reg = <0x0138>; 1216*724ba675SRob Herring ti,index-power-of-two; 1217*724ba675SRob Herring }; 1218*724ba675SRob Herring 1219*724ba675SRob Herring timer_sys_clk_div: clock-timer-sys-clk-div@144 { 1220*724ba675SRob Herring #clock-cells = <0>; 1221*724ba675SRob Herring compatible = "ti,divider-clock"; 1222*724ba675SRob Herring clock-output-names = "timer_sys_clk_div"; 1223*724ba675SRob Herring clocks = <&sys_clkin1>; 1224*724ba675SRob Herring reg = <0x0144>; 1225*724ba675SRob Herring ti,max-div = <2>; 1226*724ba675SRob Herring }; 1227*724ba675SRob Herring 1228*724ba675SRob Herring video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { 1229*724ba675SRob Herring #clock-cells = <0>; 1230*724ba675SRob Herring compatible = "ti,mux-clock"; 1231*724ba675SRob Herring clock-output-names = "video1_dpll_clk_mux"; 1232*724ba675SRob Herring clocks = <&sys_clkin1>, <&sys_clkin2>; 1233*724ba675SRob Herring reg = <0x0168>; 1234*724ba675SRob Herring }; 1235*724ba675SRob Herring 1236*724ba675SRob Herring video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { 1237*724ba675SRob Herring #clock-cells = <0>; 1238*724ba675SRob Herring compatible = "ti,mux-clock"; 1239*724ba675SRob Herring clock-output-names = "video2_dpll_clk_mux"; 1240*724ba675SRob Herring clocks = <&sys_clkin1>, <&sys_clkin2>; 1241*724ba675SRob Herring reg = <0x016c>; 1242*724ba675SRob Herring }; 1243*724ba675SRob Herring 1244*724ba675SRob Herring wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { 1245*724ba675SRob Herring #clock-cells = <0>; 1246*724ba675SRob Herring compatible = "ti,mux-clock"; 1247*724ba675SRob Herring clock-output-names = "wkupaon_iclk_mux"; 1248*724ba675SRob Herring clocks = <&sys_clkin1>, <&abe_lp_clk_div>; 1249*724ba675SRob Herring reg = <0x0108>; 1250*724ba675SRob Herring }; 1251*724ba675SRob Herring}; 1252*724ba675SRob Herring 1253*724ba675SRob Herring&cm_core_clocks { 1254*724ba675SRob Herring dpll_pcie_ref_ck: clock@200 { 1255*724ba675SRob Herring #clock-cells = <0>; 1256*724ba675SRob Herring compatible = "ti,omap4-dpll-clock"; 1257*724ba675SRob Herring clock-output-names = "dpll_pcie_ref_ck"; 1258*724ba675SRob Herring clocks = <&sys_clkin1>, <&sys_clkin1>; 1259*724ba675SRob Herring reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; 1260*724ba675SRob Herring }; 1261*724ba675SRob Herring 1262*724ba675SRob Herring dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { 1263*724ba675SRob Herring #clock-cells = <0>; 1264*724ba675SRob Herring compatible = "ti,divider-clock"; 1265*724ba675SRob Herring clock-output-names = "dpll_pcie_ref_m2ldo_ck"; 1266*724ba675SRob Herring clocks = <&dpll_pcie_ref_ck>; 1267*724ba675SRob Herring ti,max-div = <31>; 1268*724ba675SRob Herring ti,autoidle-shift = <8>; 1269*724ba675SRob Herring reg = <0x0210>; 1270*724ba675SRob Herring ti,index-starts-at-one; 1271*724ba675SRob Herring ti,invert-autoidle-bit; 1272*724ba675SRob Herring }; 1273*724ba675SRob Herring 1274*724ba675SRob Herring apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { 1275*724ba675SRob Herring compatible = "ti,mux-clock"; 1276*724ba675SRob Herring clock-output-names = "apll_pcie_in_clk_mux"; 1277*724ba675SRob Herring clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; 1278*724ba675SRob Herring #clock-cells = <0>; 1279*724ba675SRob Herring reg = <0x021c 0x4>; 1280*724ba675SRob Herring ti,bit-shift = <7>; 1281*724ba675SRob Herring }; 1282*724ba675SRob Herring 1283*724ba675SRob Herring apll_pcie_ck: clock@21c { 1284*724ba675SRob Herring #clock-cells = <0>; 1285*724ba675SRob Herring compatible = "ti,dra7-apll-clock"; 1286*724ba675SRob Herring clock-output-names = "apll_pcie_ck"; 1287*724ba675SRob Herring clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; 1288*724ba675SRob Herring reg = <0x021c>, <0x0220>; 1289*724ba675SRob Herring }; 1290*724ba675SRob Herring 1291*724ba675SRob Herring optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { 1292*724ba675SRob Herring compatible = "ti,divider-clock"; 1293*724ba675SRob Herring clock-output-names = "optfclk_pciephy_div"; 1294*724ba675SRob Herring clocks = <&apll_pcie_ck>; 1295*724ba675SRob Herring #clock-cells = <0>; 1296*724ba675SRob Herring reg = <0x021c>; 1297*724ba675SRob Herring ti,dividers = <2>, <1>; 1298*724ba675SRob Herring ti,bit-shift = <8>; 1299*724ba675SRob Herring ti,max-div = <2>; 1300*724ba675SRob Herring }; 1301*724ba675SRob Herring 1302*724ba675SRob Herring apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { 1303*724ba675SRob Herring #clock-cells = <0>; 1304*724ba675SRob Herring compatible = "fixed-factor-clock"; 1305*724ba675SRob Herring clock-output-names = "apll_pcie_clkvcoldo"; 1306*724ba675SRob Herring clocks = <&apll_pcie_ck>; 1307*724ba675SRob Herring clock-mult = <1>; 1308*724ba675SRob Herring clock-div = <1>; 1309*724ba675SRob Herring }; 1310*724ba675SRob Herring 1311*724ba675SRob Herring apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { 1312*724ba675SRob Herring #clock-cells = <0>; 1313*724ba675SRob Herring compatible = "fixed-factor-clock"; 1314*724ba675SRob Herring clock-output-names = "apll_pcie_clkvcoldo_div"; 1315*724ba675SRob Herring clocks = <&apll_pcie_ck>; 1316*724ba675SRob Herring clock-mult = <1>; 1317*724ba675SRob Herring clock-div = <1>; 1318*724ba675SRob Herring }; 1319*724ba675SRob Herring 1320*724ba675SRob Herring apll_pcie_m2_ck: clock-apll-pcie-m2 { 1321*724ba675SRob Herring #clock-cells = <0>; 1322*724ba675SRob Herring compatible = "fixed-factor-clock"; 1323*724ba675SRob Herring clock-output-names = "apll_pcie_m2_ck"; 1324*724ba675SRob Herring clocks = <&apll_pcie_ck>; 1325*724ba675SRob Herring clock-mult = <1>; 1326*724ba675SRob Herring clock-div = <1>; 1327*724ba675SRob Herring }; 1328*724ba675SRob Herring 1329*724ba675SRob Herring dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { 1330*724ba675SRob Herring #clock-cells = <0>; 1331*724ba675SRob Herring compatible = "ti,mux-clock"; 1332*724ba675SRob Herring clock-output-names = "dpll_per_byp_mux"; 1333*724ba675SRob Herring clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; 1334*724ba675SRob Herring ti,bit-shift = <23>; 1335*724ba675SRob Herring reg = <0x014c>; 1336*724ba675SRob Herring }; 1337*724ba675SRob Herring 1338*724ba675SRob Herring dpll_per_ck: clock@140 { 1339*724ba675SRob Herring #clock-cells = <0>; 1340*724ba675SRob Herring compatible = "ti,omap4-dpll-clock"; 1341*724ba675SRob Herring clock-output-names = "dpll_per_ck"; 1342*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; 1343*724ba675SRob Herring reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 1344*724ba675SRob Herring }; 1345*724ba675SRob Herring 1346*724ba675SRob Herring dpll_per_m2_ck: clock-dpll-per-m2-8@150 { 1347*724ba675SRob Herring #clock-cells = <0>; 1348*724ba675SRob Herring compatible = "ti,divider-clock"; 1349*724ba675SRob Herring clock-output-names = "dpll_per_m2_ck"; 1350*724ba675SRob Herring clocks = <&dpll_per_ck>; 1351*724ba675SRob Herring ti,max-div = <31>; 1352*724ba675SRob Herring ti,autoidle-shift = <8>; 1353*724ba675SRob Herring reg = <0x0150>; 1354*724ba675SRob Herring ti,index-starts-at-one; 1355*724ba675SRob Herring ti,invert-autoidle-bit; 1356*724ba675SRob Herring }; 1357*724ba675SRob Herring 1358*724ba675SRob Herring func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { 1359*724ba675SRob Herring #clock-cells = <0>; 1360*724ba675SRob Herring compatible = "fixed-factor-clock"; 1361*724ba675SRob Herring clock-output-names = "func_96m_aon_dclk_div"; 1362*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 1363*724ba675SRob Herring clock-mult = <1>; 1364*724ba675SRob Herring clock-div = <1>; 1365*724ba675SRob Herring }; 1366*724ba675SRob Herring 1367*724ba675SRob Herring dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { 1368*724ba675SRob Herring #clock-cells = <0>; 1369*724ba675SRob Herring compatible = "ti,mux-clock"; 1370*724ba675SRob Herring clock-output-names = "dpll_usb_byp_mux"; 1371*724ba675SRob Herring clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; 1372*724ba675SRob Herring ti,bit-shift = <23>; 1373*724ba675SRob Herring reg = <0x018c>; 1374*724ba675SRob Herring }; 1375*724ba675SRob Herring 1376*724ba675SRob Herring dpll_usb_ck: clock@180 { 1377*724ba675SRob Herring #clock-cells = <0>; 1378*724ba675SRob Herring compatible = "ti,omap4-dpll-j-type-clock"; 1379*724ba675SRob Herring clock-output-names = "dpll_usb_ck"; 1380*724ba675SRob Herring clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; 1381*724ba675SRob Herring reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 1382*724ba675SRob Herring }; 1383*724ba675SRob Herring 1384*724ba675SRob Herring dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { 1385*724ba675SRob Herring #clock-cells = <0>; 1386*724ba675SRob Herring compatible = "ti,divider-clock"; 1387*724ba675SRob Herring clock-output-names = "dpll_usb_m2_ck"; 1388*724ba675SRob Herring clocks = <&dpll_usb_ck>; 1389*724ba675SRob Herring ti,max-div = <127>; 1390*724ba675SRob Herring ti,autoidle-shift = <8>; 1391*724ba675SRob Herring reg = <0x0190>; 1392*724ba675SRob Herring ti,index-starts-at-one; 1393*724ba675SRob Herring ti,invert-autoidle-bit; 1394*724ba675SRob Herring }; 1395*724ba675SRob Herring 1396*724ba675SRob Herring dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { 1397*724ba675SRob Herring #clock-cells = <0>; 1398*724ba675SRob Herring compatible = "ti,divider-clock"; 1399*724ba675SRob Herring clock-output-names = "dpll_pcie_ref_m2_ck"; 1400*724ba675SRob Herring clocks = <&dpll_pcie_ref_ck>; 1401*724ba675SRob Herring ti,max-div = <127>; 1402*724ba675SRob Herring ti,autoidle-shift = <8>; 1403*724ba675SRob Herring reg = <0x0210>; 1404*724ba675SRob Herring ti,index-starts-at-one; 1405*724ba675SRob Herring ti,invert-autoidle-bit; 1406*724ba675SRob Herring }; 1407*724ba675SRob Herring 1408*724ba675SRob Herring dpll_per_x2_ck: clock-dpll-per-x2 { 1409*724ba675SRob Herring #clock-cells = <0>; 1410*724ba675SRob Herring compatible = "ti,omap4-dpll-x2-clock"; 1411*724ba675SRob Herring clock-output-names = "dpll_per_x2_ck"; 1412*724ba675SRob Herring clocks = <&dpll_per_ck>; 1413*724ba675SRob Herring }; 1414*724ba675SRob Herring 1415*724ba675SRob Herring dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { 1416*724ba675SRob Herring #clock-cells = <0>; 1417*724ba675SRob Herring compatible = "ti,divider-clock"; 1418*724ba675SRob Herring clock-output-names = "dpll_per_h11x2_ck"; 1419*724ba675SRob Herring clocks = <&dpll_per_x2_ck>; 1420*724ba675SRob Herring ti,max-div = <63>; 1421*724ba675SRob Herring ti,autoidle-shift = <8>; 1422*724ba675SRob Herring reg = <0x0158>; 1423*724ba675SRob Herring ti,index-starts-at-one; 1424*724ba675SRob Herring ti,invert-autoidle-bit; 1425*724ba675SRob Herring }; 1426*724ba675SRob Herring 1427*724ba675SRob Herring dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { 1428*724ba675SRob Herring #clock-cells = <0>; 1429*724ba675SRob Herring compatible = "ti,divider-clock"; 1430*724ba675SRob Herring clock-output-names = "dpll_per_h12x2_ck"; 1431*724ba675SRob Herring clocks = <&dpll_per_x2_ck>; 1432*724ba675SRob Herring ti,max-div = <63>; 1433*724ba675SRob Herring ti,autoidle-shift = <8>; 1434*724ba675SRob Herring reg = <0x015c>; 1435*724ba675SRob Herring ti,index-starts-at-one; 1436*724ba675SRob Herring ti,invert-autoidle-bit; 1437*724ba675SRob Herring }; 1438*724ba675SRob Herring 1439*724ba675SRob Herring dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { 1440*724ba675SRob Herring #clock-cells = <0>; 1441*724ba675SRob Herring compatible = "ti,divider-clock"; 1442*724ba675SRob Herring clock-output-names = "dpll_per_h13x2_ck"; 1443*724ba675SRob Herring clocks = <&dpll_per_x2_ck>; 1444*724ba675SRob Herring ti,max-div = <63>; 1445*724ba675SRob Herring ti,autoidle-shift = <8>; 1446*724ba675SRob Herring reg = <0x0160>; 1447*724ba675SRob Herring ti,index-starts-at-one; 1448*724ba675SRob Herring ti,invert-autoidle-bit; 1449*724ba675SRob Herring }; 1450*724ba675SRob Herring 1451*724ba675SRob Herring dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { 1452*724ba675SRob Herring #clock-cells = <0>; 1453*724ba675SRob Herring compatible = "ti,divider-clock"; 1454*724ba675SRob Herring clock-output-names = "dpll_per_h14x2_ck"; 1455*724ba675SRob Herring clocks = <&dpll_per_x2_ck>; 1456*724ba675SRob Herring ti,max-div = <63>; 1457*724ba675SRob Herring ti,autoidle-shift = <8>; 1458*724ba675SRob Herring reg = <0x0164>; 1459*724ba675SRob Herring ti,index-starts-at-one; 1460*724ba675SRob Herring ti,invert-autoidle-bit; 1461*724ba675SRob Herring }; 1462*724ba675SRob Herring 1463*724ba675SRob Herring dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { 1464*724ba675SRob Herring #clock-cells = <0>; 1465*724ba675SRob Herring compatible = "ti,divider-clock"; 1466*724ba675SRob Herring clock-output-names = "dpll_per_m2x2_ck"; 1467*724ba675SRob Herring clocks = <&dpll_per_x2_ck>; 1468*724ba675SRob Herring ti,max-div = <31>; 1469*724ba675SRob Herring ti,autoidle-shift = <8>; 1470*724ba675SRob Herring reg = <0x0150>; 1471*724ba675SRob Herring ti,index-starts-at-one; 1472*724ba675SRob Herring ti,invert-autoidle-bit; 1473*724ba675SRob Herring }; 1474*724ba675SRob Herring 1475*724ba675SRob Herring dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { 1476*724ba675SRob Herring #clock-cells = <0>; 1477*724ba675SRob Herring compatible = "fixed-factor-clock"; 1478*724ba675SRob Herring clock-output-names = "dpll_usb_clkdcoldo"; 1479*724ba675SRob Herring clocks = <&dpll_usb_ck>; 1480*724ba675SRob Herring clock-mult = <1>; 1481*724ba675SRob Herring clock-div = <1>; 1482*724ba675SRob Herring }; 1483*724ba675SRob Herring 1484*724ba675SRob Herring func_128m_clk: clock-func-128m { 1485*724ba675SRob Herring #clock-cells = <0>; 1486*724ba675SRob Herring compatible = "fixed-factor-clock"; 1487*724ba675SRob Herring clock-output-names = "func_128m_clk"; 1488*724ba675SRob Herring clocks = <&dpll_per_h11x2_ck>; 1489*724ba675SRob Herring clock-mult = <1>; 1490*724ba675SRob Herring clock-div = <2>; 1491*724ba675SRob Herring }; 1492*724ba675SRob Herring 1493*724ba675SRob Herring func_12m_fclk: clock-func-12m-fclk { 1494*724ba675SRob Herring #clock-cells = <0>; 1495*724ba675SRob Herring compatible = "fixed-factor-clock"; 1496*724ba675SRob Herring clock-output-names = "func_12m_fclk"; 1497*724ba675SRob Herring clocks = <&dpll_per_m2x2_ck>; 1498*724ba675SRob Herring clock-mult = <1>; 1499*724ba675SRob Herring clock-div = <16>; 1500*724ba675SRob Herring }; 1501*724ba675SRob Herring 1502*724ba675SRob Herring func_24m_clk: clock-func-24m { 1503*724ba675SRob Herring #clock-cells = <0>; 1504*724ba675SRob Herring compatible = "fixed-factor-clock"; 1505*724ba675SRob Herring clock-output-names = "func_24m_clk"; 1506*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 1507*724ba675SRob Herring clock-mult = <1>; 1508*724ba675SRob Herring clock-div = <4>; 1509*724ba675SRob Herring }; 1510*724ba675SRob Herring 1511*724ba675SRob Herring func_48m_fclk: clock-func-48m-fclk { 1512*724ba675SRob Herring #clock-cells = <0>; 1513*724ba675SRob Herring compatible = "fixed-factor-clock"; 1514*724ba675SRob Herring clock-output-names = "func_48m_fclk"; 1515*724ba675SRob Herring clocks = <&dpll_per_m2x2_ck>; 1516*724ba675SRob Herring clock-mult = <1>; 1517*724ba675SRob Herring clock-div = <4>; 1518*724ba675SRob Herring }; 1519*724ba675SRob Herring 1520*724ba675SRob Herring func_96m_fclk: clock-func-96m-fclk { 1521*724ba675SRob Herring #clock-cells = <0>; 1522*724ba675SRob Herring compatible = "fixed-factor-clock"; 1523*724ba675SRob Herring clock-output-names = "func_96m_fclk"; 1524*724ba675SRob Herring clocks = <&dpll_per_m2x2_ck>; 1525*724ba675SRob Herring clock-mult = <1>; 1526*724ba675SRob Herring clock-div = <2>; 1527*724ba675SRob Herring }; 1528*724ba675SRob Herring 1529*724ba675SRob Herring l3init_60m_fclk: clock-l3init-60m@104 { 1530*724ba675SRob Herring #clock-cells = <0>; 1531*724ba675SRob Herring compatible = "ti,divider-clock"; 1532*724ba675SRob Herring clock-output-names = "l3init_60m_fclk"; 1533*724ba675SRob Herring clocks = <&dpll_usb_m2_ck>; 1534*724ba675SRob Herring reg = <0x0104>; 1535*724ba675SRob Herring ti,dividers = <1>, <8>; 1536*724ba675SRob Herring }; 1537*724ba675SRob Herring 1538*724ba675SRob Herring clkout2_clk: clock-clkout2-8@6b0 { 1539*724ba675SRob Herring #clock-cells = <0>; 1540*724ba675SRob Herring compatible = "ti,gate-clock"; 1541*724ba675SRob Herring clock-output-names = "clkout2_clk"; 1542*724ba675SRob Herring clocks = <&clkoutmux2_clk_mux>; 1543*724ba675SRob Herring ti,bit-shift = <8>; 1544*724ba675SRob Herring reg = <0x06b0>; 1545*724ba675SRob Herring }; 1546*724ba675SRob Herring 1547*724ba675SRob Herring l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { 1548*724ba675SRob Herring #clock-cells = <0>; 1549*724ba675SRob Herring compatible = "ti,gate-clock"; 1550*724ba675SRob Herring clock-output-names = "l3init_960m_gfclk"; 1551*724ba675SRob Herring clocks = <&dpll_usb_clkdcoldo>; 1552*724ba675SRob Herring ti,bit-shift = <8>; 1553*724ba675SRob Herring reg = <0x06c0>; 1554*724ba675SRob Herring }; 1555*724ba675SRob Herring 1556*724ba675SRob Herring usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { 1557*724ba675SRob Herring #clock-cells = <0>; 1558*724ba675SRob Herring compatible = "ti,gate-clock"; 1559*724ba675SRob Herring clock-output-names = "usb_phy1_always_on_clk32k"; 1560*724ba675SRob Herring clocks = <&sys_32k_ck>; 1561*724ba675SRob Herring ti,bit-shift = <8>; 1562*724ba675SRob Herring reg = <0x0640>; 1563*724ba675SRob Herring }; 1564*724ba675SRob Herring 1565*724ba675SRob Herring usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { 1566*724ba675SRob Herring #clock-cells = <0>; 1567*724ba675SRob Herring compatible = "ti,gate-clock"; 1568*724ba675SRob Herring clock-output-names = "usb_phy2_always_on_clk32k"; 1569*724ba675SRob Herring clocks = <&sys_32k_ck>; 1570*724ba675SRob Herring ti,bit-shift = <8>; 1571*724ba675SRob Herring reg = <0x0688>; 1572*724ba675SRob Herring }; 1573*724ba675SRob Herring 1574*724ba675SRob Herring usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { 1575*724ba675SRob Herring #clock-cells = <0>; 1576*724ba675SRob Herring compatible = "ti,gate-clock"; 1577*724ba675SRob Herring clock-output-names = "usb_phy3_always_on_clk32k"; 1578*724ba675SRob Herring clocks = <&sys_32k_ck>; 1579*724ba675SRob Herring ti,bit-shift = <8>; 1580*724ba675SRob Herring reg = <0x0698>; 1581*724ba675SRob Herring }; 1582*724ba675SRob Herring 1583*724ba675SRob Herring gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { 1584*724ba675SRob Herring #clock-cells = <0>; 1585*724ba675SRob Herring compatible = "ti,mux-clock"; 1586*724ba675SRob Herring clock-output-names = "gpu_core_gclk_mux"; 1587*724ba675SRob Herring clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; 1588*724ba675SRob Herring ti,bit-shift = <24>; 1589*724ba675SRob Herring reg = <0x1220>; 1590*724ba675SRob Herring assigned-clocks = <&gpu_core_gclk_mux>; 1591*724ba675SRob Herring assigned-clock-parents = <&dpll_gpu_m2_ck>; 1592*724ba675SRob Herring }; 1593*724ba675SRob Herring 1594*724ba675SRob Herring gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { 1595*724ba675SRob Herring #clock-cells = <0>; 1596*724ba675SRob Herring compatible = "ti,mux-clock"; 1597*724ba675SRob Herring clock-output-names = "gpu_hyd_gclk_mux"; 1598*724ba675SRob Herring clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; 1599*724ba675SRob Herring ti,bit-shift = <26>; 1600*724ba675SRob Herring reg = <0x1220>; 1601*724ba675SRob Herring assigned-clocks = <&gpu_hyd_gclk_mux>; 1602*724ba675SRob Herring assigned-clock-parents = <&dpll_gpu_m2_ck>; 1603*724ba675SRob Herring }; 1604*724ba675SRob Herring 1605*724ba675SRob Herring l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { 1606*724ba675SRob Herring #clock-cells = <0>; 1607*724ba675SRob Herring compatible = "ti,divider-clock"; 1608*724ba675SRob Herring clock-output-names = "l3instr_ts_gclk_div"; 1609*724ba675SRob Herring clocks = <&wkupaon_iclk_mux>; 1610*724ba675SRob Herring ti,bit-shift = <24>; 1611*724ba675SRob Herring reg = <0x0e50>; 1612*724ba675SRob Herring ti,dividers = <8>, <16>, <32>; 1613*724ba675SRob Herring }; 1614*724ba675SRob Herring 1615*724ba675SRob Herring vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { 1616*724ba675SRob Herring #clock-cells = <0>; 1617*724ba675SRob Herring compatible = "ti,mux-clock"; 1618*724ba675SRob Herring clock-output-names = "vip1_gclk_mux"; 1619*724ba675SRob Herring clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1620*724ba675SRob Herring ti,bit-shift = <24>; 1621*724ba675SRob Herring reg = <0x1020>; 1622*724ba675SRob Herring }; 1623*724ba675SRob Herring 1624*724ba675SRob Herring vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { 1625*724ba675SRob Herring #clock-cells = <0>; 1626*724ba675SRob Herring compatible = "ti,mux-clock"; 1627*724ba675SRob Herring clock-output-names = "vip2_gclk_mux"; 1628*724ba675SRob Herring clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1629*724ba675SRob Herring ti,bit-shift = <24>; 1630*724ba675SRob Herring reg = <0x1028>; 1631*724ba675SRob Herring }; 1632*724ba675SRob Herring 1633*724ba675SRob Herring vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 { 1634*724ba675SRob Herring #clock-cells = <0>; 1635*724ba675SRob Herring compatible = "ti,mux-clock"; 1636*724ba675SRob Herring clock-output-names = "vip3_gclk_mux"; 1637*724ba675SRob Herring clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; 1638*724ba675SRob Herring ti,bit-shift = <24>; 1639*724ba675SRob Herring reg = <0x1030>; 1640*724ba675SRob Herring }; 1641*724ba675SRob Herring}; 1642*724ba675SRob Herring 1643*724ba675SRob Herring&cm_core_clockdomains { 1644*724ba675SRob Herring coreaon_clkdm: clock-coreaon-clkdm { 1645*724ba675SRob Herring compatible = "ti,clockdomain"; 1646*724ba675SRob Herring clock-output-names = "coreaon_clkdm"; 1647*724ba675SRob Herring clocks = <&dpll_usb_ck>; 1648*724ba675SRob Herring }; 1649*724ba675SRob Herring}; 1650*724ba675SRob Herring 1651*724ba675SRob Herring&scm_conf_clocks { 1652*724ba675SRob Herring dss_deshdcp_clk: clock-dss-deshdcp-0@558 { 1653*724ba675SRob Herring #clock-cells = <0>; 1654*724ba675SRob Herring compatible = "ti,gate-clock"; 1655*724ba675SRob Herring clock-output-names = "dss_deshdcp_clk"; 1656*724ba675SRob Herring clocks = <&l3_iclk_div>; 1657*724ba675SRob Herring ti,bit-shift = <0>; 1658*724ba675SRob Herring reg = <0x558>; 1659*724ba675SRob Herring }; 1660*724ba675SRob Herring 1661*724ba675SRob Herring ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 { 1662*724ba675SRob Herring #clock-cells = <0>; 1663*724ba675SRob Herring compatible = "ti,gate-clock"; 1664*724ba675SRob Herring clock-output-names = "ehrpwm0_tbclk"; 1665*724ba675SRob Herring clocks = <&l4_root_clk_div>; 1666*724ba675SRob Herring ti,bit-shift = <20>; 1667*724ba675SRob Herring reg = <0x0558>; 1668*724ba675SRob Herring }; 1669*724ba675SRob Herring 1670*724ba675SRob Herring ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 { 1671*724ba675SRob Herring #clock-cells = <0>; 1672*724ba675SRob Herring compatible = "ti,gate-clock"; 1673*724ba675SRob Herring clock-output-names = "ehrpwm1_tbclk"; 1674*724ba675SRob Herring clocks = <&l4_root_clk_div>; 1675*724ba675SRob Herring ti,bit-shift = <21>; 1676*724ba675SRob Herring reg = <0x0558>; 1677*724ba675SRob Herring }; 1678*724ba675SRob Herring 1679*724ba675SRob Herring ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 { 1680*724ba675SRob Herring #clock-cells = <0>; 1681*724ba675SRob Herring compatible = "ti,gate-clock"; 1682*724ba675SRob Herring clock-output-names = "ehrpwm2_tbclk"; 1683*724ba675SRob Herring clocks = <&l4_root_clk_div>; 1684*724ba675SRob Herring ti,bit-shift = <22>; 1685*724ba675SRob Herring reg = <0x0558>; 1686*724ba675SRob Herring }; 1687*724ba675SRob Herring 1688*724ba675SRob Herring sys_32k_ck: clock-sys-32k { 1689*724ba675SRob Herring #clock-cells = <0>; 1690*724ba675SRob Herring compatible = "ti,mux-clock"; 1691*724ba675SRob Herring clock-output-names = "sys_32k_ck"; 1692*724ba675SRob Herring clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; 1693*724ba675SRob Herring ti,bit-shift = <8>; 1694*724ba675SRob Herring reg = <0x6c4>; 1695*724ba675SRob Herring }; 1696*724ba675SRob Herring}; 1697*724ba675SRob Herring 1698*724ba675SRob Herring&cm_core_aon { 1699*724ba675SRob Herring mpu_cm: clock@300 { 1700*724ba675SRob Herring compatible = "ti,omap4-cm"; 1701*724ba675SRob Herring clock-output-names = "mpu_cm"; 1702*724ba675SRob Herring reg = <0x300 0x100>; 1703*724ba675SRob Herring #address-cells = <1>; 1704*724ba675SRob Herring #size-cells = <1>; 1705*724ba675SRob Herring ranges = <0 0x300 0x100>; 1706*724ba675SRob Herring 1707*724ba675SRob Herring mpu_clkctrl: clock@20 { 1708*724ba675SRob Herring compatible = "ti,clkctrl"; 1709*724ba675SRob Herring clock-output-names = "mpu_clkctrl"; 1710*724ba675SRob Herring reg = <0x20 0x4>; 1711*724ba675SRob Herring #clock-cells = <2>; 1712*724ba675SRob Herring }; 1713*724ba675SRob Herring 1714*724ba675SRob Herring }; 1715*724ba675SRob Herring 1716*724ba675SRob Herring dsp1_cm: clock@400 { 1717*724ba675SRob Herring compatible = "ti,omap4-cm"; 1718*724ba675SRob Herring clock-output-names = "dsp1_cm"; 1719*724ba675SRob Herring reg = <0x400 0x100>; 1720*724ba675SRob Herring #address-cells = <1>; 1721*724ba675SRob Herring #size-cells = <1>; 1722*724ba675SRob Herring ranges = <0 0x400 0x100>; 1723*724ba675SRob Herring 1724*724ba675SRob Herring dsp1_clkctrl: clock@20 { 1725*724ba675SRob Herring compatible = "ti,clkctrl"; 1726*724ba675SRob Herring clock-output-names = "dsp1_clkctrl"; 1727*724ba675SRob Herring reg = <0x20 0x4>; 1728*724ba675SRob Herring #clock-cells = <2>; 1729*724ba675SRob Herring }; 1730*724ba675SRob Herring 1731*724ba675SRob Herring }; 1732*724ba675SRob Herring 1733*724ba675SRob Herring ipu_cm: clock@500 { 1734*724ba675SRob Herring compatible = "ti,omap4-cm"; 1735*724ba675SRob Herring clock-output-names = "ipu_cm"; 1736*724ba675SRob Herring reg = <0x500 0x100>; 1737*724ba675SRob Herring #address-cells = <1>; 1738*724ba675SRob Herring #size-cells = <1>; 1739*724ba675SRob Herring ranges = <0 0x500 0x100>; 1740*724ba675SRob Herring 1741*724ba675SRob Herring ipu1_clkctrl: clock@20 { 1742*724ba675SRob Herring compatible = "ti,clkctrl"; 1743*724ba675SRob Herring clock-output-names = "ipu1_clkctrl"; 1744*724ba675SRob Herring reg = <0x20 0x4>; 1745*724ba675SRob Herring #clock-cells = <2>; 1746*724ba675SRob Herring assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; 1747*724ba675SRob Herring assigned-clock-parents = <&dpll_core_h22x2_ck>; 1748*724ba675SRob Herring }; 1749*724ba675SRob Herring 1750*724ba675SRob Herring ipu_clkctrl: clock@50 { 1751*724ba675SRob Herring compatible = "ti,clkctrl"; 1752*724ba675SRob Herring clock-output-names = "ipu_clkctrl"; 1753*724ba675SRob Herring reg = <0x50 0x34>; 1754*724ba675SRob Herring #clock-cells = <2>; 1755*724ba675SRob Herring }; 1756*724ba675SRob Herring 1757*724ba675SRob Herring }; 1758*724ba675SRob Herring 1759*724ba675SRob Herring dsp2_cm: clock@600 { 1760*724ba675SRob Herring compatible = "ti,omap4-cm"; 1761*724ba675SRob Herring clock-output-names = "dsp2_cm"; 1762*724ba675SRob Herring reg = <0x600 0x100>; 1763*724ba675SRob Herring #address-cells = <1>; 1764*724ba675SRob Herring #size-cells = <1>; 1765*724ba675SRob Herring ranges = <0 0x600 0x100>; 1766*724ba675SRob Herring 1767*724ba675SRob Herring dsp2_clkctrl: clock@20 { 1768*724ba675SRob Herring compatible = "ti,clkctrl"; 1769*724ba675SRob Herring clock-output-names = "dsp2_clkctrl"; 1770*724ba675SRob Herring reg = <0x20 0x4>; 1771*724ba675SRob Herring #clock-cells = <2>; 1772*724ba675SRob Herring }; 1773*724ba675SRob Herring 1774*724ba675SRob Herring }; 1775*724ba675SRob Herring 1776*724ba675SRob Herring rtc_cm: clock@700 { 1777*724ba675SRob Herring compatible = "ti,omap4-cm"; 1778*724ba675SRob Herring clock-output-names = "rtc_cm"; 1779*724ba675SRob Herring reg = <0x700 0x60>; 1780*724ba675SRob Herring #address-cells = <1>; 1781*724ba675SRob Herring #size-cells = <1>; 1782*724ba675SRob Herring ranges = <0 0x700 0x60>; 1783*724ba675SRob Herring 1784*724ba675SRob Herring rtc_clkctrl: clock@20 { 1785*724ba675SRob Herring compatible = "ti,clkctrl"; 1786*724ba675SRob Herring clock-output-names = "rtc_clkctrl"; 1787*724ba675SRob Herring reg = <0x20 0x28>; 1788*724ba675SRob Herring #clock-cells = <2>; 1789*724ba675SRob Herring }; 1790*724ba675SRob Herring }; 1791*724ba675SRob Herring 1792*724ba675SRob Herring vpe_cm: clock@760 { 1793*724ba675SRob Herring compatible = "ti,omap4-cm"; 1794*724ba675SRob Herring clock-output-names = "vpe_cm"; 1795*724ba675SRob Herring reg = <0x760 0xc>; 1796*724ba675SRob Herring #address-cells = <1>; 1797*724ba675SRob Herring #size-cells = <1>; 1798*724ba675SRob Herring ranges = <0 0x760 0xc>; 1799*724ba675SRob Herring 1800*724ba675SRob Herring vpe_clkctrl: clock@0 { 1801*724ba675SRob Herring compatible = "ti,clkctrl"; 1802*724ba675SRob Herring clock-output-names = "vpe_clkctrl"; 1803*724ba675SRob Herring reg = <0x0 0xc>; 1804*724ba675SRob Herring #clock-cells = <2>; 1805*724ba675SRob Herring }; 1806*724ba675SRob Herring }; 1807*724ba675SRob Herring 1808*724ba675SRob Herring}; 1809*724ba675SRob Herring 1810*724ba675SRob Herring&cm_core { 1811*724ba675SRob Herring coreaon_cm: clock@600 { 1812*724ba675SRob Herring compatible = "ti,omap4-cm"; 1813*724ba675SRob Herring clock-output-names = "coreaon_cm"; 1814*724ba675SRob Herring reg = <0x600 0x100>; 1815*724ba675SRob Herring #address-cells = <1>; 1816*724ba675SRob Herring #size-cells = <1>; 1817*724ba675SRob Herring ranges = <0 0x600 0x100>; 1818*724ba675SRob Herring 1819*724ba675SRob Herring coreaon_clkctrl: clock@20 { 1820*724ba675SRob Herring compatible = "ti,clkctrl"; 1821*724ba675SRob Herring clock-output-names = "coreaon_clkctrl"; 1822*724ba675SRob Herring reg = <0x20 0x1c>; 1823*724ba675SRob Herring #clock-cells = <2>; 1824*724ba675SRob Herring }; 1825*724ba675SRob Herring }; 1826*724ba675SRob Herring 1827*724ba675SRob Herring l3main1_cm: clock@700 { 1828*724ba675SRob Herring compatible = "ti,omap4-cm"; 1829*724ba675SRob Herring clock-output-names = "l3main1_cm"; 1830*724ba675SRob Herring reg = <0x700 0x100>; 1831*724ba675SRob Herring #address-cells = <1>; 1832*724ba675SRob Herring #size-cells = <1>; 1833*724ba675SRob Herring ranges = <0 0x700 0x100>; 1834*724ba675SRob Herring 1835*724ba675SRob Herring l3main1_clkctrl: clock@20 { 1836*724ba675SRob Herring compatible = "ti,clkctrl"; 1837*724ba675SRob Herring clock-output-names = "l3main1_clkctrl"; 1838*724ba675SRob Herring reg = <0x20 0x74>; 1839*724ba675SRob Herring #clock-cells = <2>; 1840*724ba675SRob Herring }; 1841*724ba675SRob Herring 1842*724ba675SRob Herring }; 1843*724ba675SRob Herring 1844*724ba675SRob Herring ipu2_cm: clock@900 { 1845*724ba675SRob Herring compatible = "ti,omap4-cm"; 1846*724ba675SRob Herring clock-output-names = "ipu2_cm"; 1847*724ba675SRob Herring reg = <0x900 0x100>; 1848*724ba675SRob Herring #address-cells = <1>; 1849*724ba675SRob Herring #size-cells = <1>; 1850*724ba675SRob Herring ranges = <0 0x900 0x100>; 1851*724ba675SRob Herring 1852*724ba675SRob Herring ipu2_clkctrl: clock@20 { 1853*724ba675SRob Herring compatible = "ti,clkctrl"; 1854*724ba675SRob Herring clock-output-names = "ipu2_clkctrl"; 1855*724ba675SRob Herring reg = <0x20 0x4>; 1856*724ba675SRob Herring #clock-cells = <2>; 1857*724ba675SRob Herring }; 1858*724ba675SRob Herring 1859*724ba675SRob Herring }; 1860*724ba675SRob Herring 1861*724ba675SRob Herring dma_cm: clock@a00 { 1862*724ba675SRob Herring compatible = "ti,omap4-cm"; 1863*724ba675SRob Herring clock-output-names = "dma_cm"; 1864*724ba675SRob Herring reg = <0xa00 0x100>; 1865*724ba675SRob Herring #address-cells = <1>; 1866*724ba675SRob Herring #size-cells = <1>; 1867*724ba675SRob Herring ranges = <0 0xa00 0x100>; 1868*724ba675SRob Herring 1869*724ba675SRob Herring dma_clkctrl: clock@20 { 1870*724ba675SRob Herring compatible = "ti,clkctrl"; 1871*724ba675SRob Herring clock-output-names = "dma_clkctrl"; 1872*724ba675SRob Herring reg = <0x20 0x4>; 1873*724ba675SRob Herring #clock-cells = <2>; 1874*724ba675SRob Herring }; 1875*724ba675SRob Herring }; 1876*724ba675SRob Herring 1877*724ba675SRob Herring emif_cm: clock@b00 { 1878*724ba675SRob Herring compatible = "ti,omap4-cm"; 1879*724ba675SRob Herring clock-output-names = "emif_cm"; 1880*724ba675SRob Herring reg = <0xb00 0x100>; 1881*724ba675SRob Herring #address-cells = <1>; 1882*724ba675SRob Herring #size-cells = <1>; 1883*724ba675SRob Herring ranges = <0 0xb00 0x100>; 1884*724ba675SRob Herring 1885*724ba675SRob Herring emif_clkctrl: clock@20 { 1886*724ba675SRob Herring compatible = "ti,clkctrl"; 1887*724ba675SRob Herring clock-output-names = "emif_clkctrl"; 1888*724ba675SRob Herring reg = <0x20 0x4>; 1889*724ba675SRob Herring #clock-cells = <2>; 1890*724ba675SRob Herring }; 1891*724ba675SRob Herring }; 1892*724ba675SRob Herring 1893*724ba675SRob Herring atl_cm: clock@c00 { 1894*724ba675SRob Herring compatible = "ti,omap4-cm"; 1895*724ba675SRob Herring clock-output-names = "atl_cm"; 1896*724ba675SRob Herring reg = <0xc00 0x100>; 1897*724ba675SRob Herring #address-cells = <1>; 1898*724ba675SRob Herring #size-cells = <1>; 1899*724ba675SRob Herring ranges = <0 0xc00 0x100>; 1900*724ba675SRob Herring 1901*724ba675SRob Herring atl_clkctrl: clock@0 { 1902*724ba675SRob Herring compatible = "ti,clkctrl"; 1903*724ba675SRob Herring clock-output-names = "atl_clkctrl"; 1904*724ba675SRob Herring reg = <0x0 0x4>; 1905*724ba675SRob Herring #clock-cells = <2>; 1906*724ba675SRob Herring }; 1907*724ba675SRob Herring }; 1908*724ba675SRob Herring 1909*724ba675SRob Herring l4cfg_cm: clock@d00 { 1910*724ba675SRob Herring compatible = "ti,omap4-cm"; 1911*724ba675SRob Herring clock-output-names = "l4cfg_cm"; 1912*724ba675SRob Herring reg = <0xd00 0x100>; 1913*724ba675SRob Herring #address-cells = <1>; 1914*724ba675SRob Herring #size-cells = <1>; 1915*724ba675SRob Herring ranges = <0 0xd00 0x100>; 1916*724ba675SRob Herring 1917*724ba675SRob Herring l4cfg_clkctrl: clock@20 { 1918*724ba675SRob Herring compatible = "ti,clkctrl"; 1919*724ba675SRob Herring clock-output-names = "l4cfg_clkctrl"; 1920*724ba675SRob Herring reg = <0x20 0x84>; 1921*724ba675SRob Herring #clock-cells = <2>; 1922*724ba675SRob Herring }; 1923*724ba675SRob Herring }; 1924*724ba675SRob Herring 1925*724ba675SRob Herring l3instr_cm: clock@e00 { 1926*724ba675SRob Herring compatible = "ti,omap4-cm"; 1927*724ba675SRob Herring clock-output-names = "l3instr_cm"; 1928*724ba675SRob Herring reg = <0xe00 0x100>; 1929*724ba675SRob Herring #address-cells = <1>; 1930*724ba675SRob Herring #size-cells = <1>; 1931*724ba675SRob Herring ranges = <0 0xe00 0x100>; 1932*724ba675SRob Herring 1933*724ba675SRob Herring l3instr_clkctrl: clock@20 { 1934*724ba675SRob Herring compatible = "ti,clkctrl"; 1935*724ba675SRob Herring clock-output-names = "l3instr_clkctrl"; 1936*724ba675SRob Herring reg = <0x20 0xc>; 1937*724ba675SRob Herring #clock-cells = <2>; 1938*724ba675SRob Herring }; 1939*724ba675SRob Herring }; 1940*724ba675SRob Herring 1941*724ba675SRob Herring iva_cm: clock@f00 { 1942*724ba675SRob Herring compatible = "ti,omap4-cm"; 1943*724ba675SRob Herring clock-output-names = "iva_cm"; 1944*724ba675SRob Herring reg = <0xf00 0x100>; 1945*724ba675SRob Herring #address-cells = <1>; 1946*724ba675SRob Herring #size-cells = <1>; 1947*724ba675SRob Herring ranges = <0 0xf00 0x100>; 1948*724ba675SRob Herring 1949*724ba675SRob Herring iva_clkctrl: clock@20 { 1950*724ba675SRob Herring compatible = "ti,clkctrl"; 1951*724ba675SRob Herring clock-output-names = "iva_clkctrl"; 1952*724ba675SRob Herring reg = <0x20 0xc>; 1953*724ba675SRob Herring #clock-cells = <2>; 1954*724ba675SRob Herring }; 1955*724ba675SRob Herring }; 1956*724ba675SRob Herring 1957*724ba675SRob Herring cam_cm: clock@1000 { 1958*724ba675SRob Herring compatible = "ti,omap4-cm"; 1959*724ba675SRob Herring clock-output-names = "cam_cm"; 1960*724ba675SRob Herring reg = <0x1000 0x100>; 1961*724ba675SRob Herring #address-cells = <1>; 1962*724ba675SRob Herring #size-cells = <1>; 1963*724ba675SRob Herring ranges = <0 0x1000 0x100>; 1964*724ba675SRob Herring 1965*724ba675SRob Herring cam_clkctrl: clock@20 { 1966*724ba675SRob Herring compatible = "ti,clkctrl"; 1967*724ba675SRob Herring clock-output-names = "cam_clkctrl"; 1968*724ba675SRob Herring reg = <0x20 0x2c>; 1969*724ba675SRob Herring #clock-cells = <2>; 1970*724ba675SRob Herring }; 1971*724ba675SRob Herring }; 1972*724ba675SRob Herring 1973*724ba675SRob Herring dss_cm: clock@1100 { 1974*724ba675SRob Herring compatible = "ti,omap4-cm"; 1975*724ba675SRob Herring clock-output-names = "dss_cm"; 1976*724ba675SRob Herring reg = <0x1100 0x100>; 1977*724ba675SRob Herring #address-cells = <1>; 1978*724ba675SRob Herring #size-cells = <1>; 1979*724ba675SRob Herring ranges = <0 0x1100 0x100>; 1980*724ba675SRob Herring 1981*724ba675SRob Herring dss_clkctrl: clock@20 { 1982*724ba675SRob Herring compatible = "ti,clkctrl"; 1983*724ba675SRob Herring clock-output-names = "dss_clkctrl"; 1984*724ba675SRob Herring reg = <0x20 0x14>; 1985*724ba675SRob Herring #clock-cells = <2>; 1986*724ba675SRob Herring }; 1987*724ba675SRob Herring }; 1988*724ba675SRob Herring 1989*724ba675SRob Herring gpu_cm: clock@1200 { 1990*724ba675SRob Herring compatible = "ti,omap4-cm"; 1991*724ba675SRob Herring clock-output-names = "gpu_cm"; 1992*724ba675SRob Herring reg = <0x1200 0x100>; 1993*724ba675SRob Herring #address-cells = <1>; 1994*724ba675SRob Herring #size-cells = <1>; 1995*724ba675SRob Herring ranges = <0 0x1200 0x100>; 1996*724ba675SRob Herring 1997*724ba675SRob Herring gpu_clkctrl: clock@20 { 1998*724ba675SRob Herring compatible = "ti,clkctrl"; 1999*724ba675SRob Herring clock-output-names = "gpu_clkctrl"; 2000*724ba675SRob Herring reg = <0x20 0x4>; 2001*724ba675SRob Herring #clock-cells = <2>; 2002*724ba675SRob Herring }; 2003*724ba675SRob Herring }; 2004*724ba675SRob Herring 2005*724ba675SRob Herring l3init_cm: clock@1300 { 2006*724ba675SRob Herring compatible = "ti,omap4-cm"; 2007*724ba675SRob Herring clock-output-names = "l3init_cm"; 2008*724ba675SRob Herring reg = <0x1300 0x100>; 2009*724ba675SRob Herring #address-cells = <1>; 2010*724ba675SRob Herring #size-cells = <1>; 2011*724ba675SRob Herring ranges = <0 0x1300 0x100>; 2012*724ba675SRob Herring 2013*724ba675SRob Herring l3init_clkctrl: clock@20 { 2014*724ba675SRob Herring compatible = "ti,clkctrl"; 2015*724ba675SRob Herring clock-output-names = "l3init_clkctrl"; 2016*724ba675SRob Herring reg = <0x20 0x6c>, <0xe0 0x14>; 2017*724ba675SRob Herring #clock-cells = <2>; 2018*724ba675SRob Herring }; 2019*724ba675SRob Herring 2020*724ba675SRob Herring pcie_clkctrl: clock@b0 { 2021*724ba675SRob Herring compatible = "ti,clkctrl"; 2022*724ba675SRob Herring clock-output-names = "pcie_clkctrl"; 2023*724ba675SRob Herring reg = <0xb0 0xc>; 2024*724ba675SRob Herring #clock-cells = <2>; 2025*724ba675SRob Herring }; 2026*724ba675SRob Herring 2027*724ba675SRob Herring gmac_clkctrl: clock@d0 { 2028*724ba675SRob Herring compatible = "ti,clkctrl"; 2029*724ba675SRob Herring clock-output-names = "gmac_clkctrl"; 2030*724ba675SRob Herring reg = <0xd0 0x4>; 2031*724ba675SRob Herring #clock-cells = <2>; 2032*724ba675SRob Herring }; 2033*724ba675SRob Herring 2034*724ba675SRob Herring }; 2035*724ba675SRob Herring 2036*724ba675SRob Herring l4per_cm: clock@1700 { 2037*724ba675SRob Herring compatible = "ti,omap4-cm"; 2038*724ba675SRob Herring clock-output-names = "l4per_cm"; 2039*724ba675SRob Herring reg = <0x1700 0x300>; 2040*724ba675SRob Herring #address-cells = <1>; 2041*724ba675SRob Herring #size-cells = <1>; 2042*724ba675SRob Herring ranges = <0 0x1700 0x300>; 2043*724ba675SRob Herring 2044*724ba675SRob Herring l4per_clkctrl: clock@28 { 2045*724ba675SRob Herring compatible = "ti,clkctrl"; 2046*724ba675SRob Herring clock-output-names = "l4per_clkctrl"; 2047*724ba675SRob Herring reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; 2048*724ba675SRob Herring #clock-cells = <2>; 2049*724ba675SRob Herring 2050*724ba675SRob Herring assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2051*724ba675SRob Herring assigned-clock-parents = <&abe_24m_fclk>; 2052*724ba675SRob Herring }; 2053*724ba675SRob Herring 2054*724ba675SRob Herring l4sec_clkctrl: clock@1a0 { 2055*724ba675SRob Herring compatible = "ti,clkctrl"; 2056*724ba675SRob Herring clock-output-names = "l4sec_clkctrl"; 2057*724ba675SRob Herring reg = <0x1a0 0x2c>; 2058*724ba675SRob Herring #clock-cells = <2>; 2059*724ba675SRob Herring }; 2060*724ba675SRob Herring 2061*724ba675SRob Herring l4per2_clkctrl: clock@c { 2062*724ba675SRob Herring compatible = "ti,clkctrl"; 2063*724ba675SRob Herring clock-output-names = "l4per2_clkctrl"; 2064*724ba675SRob Herring reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; 2065*724ba675SRob Herring #clock-cells = <2>; 2066*724ba675SRob Herring }; 2067*724ba675SRob Herring 2068*724ba675SRob Herring l4per3_clkctrl: clock@14 { 2069*724ba675SRob Herring compatible = "ti,clkctrl"; 2070*724ba675SRob Herring clock-output-names = "l4per3_clkctrl"; 2071*724ba675SRob Herring reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; 2072*724ba675SRob Herring #clock-cells = <2>; 2073*724ba675SRob Herring }; 2074*724ba675SRob Herring }; 2075*724ba675SRob Herring 2076*724ba675SRob Herring}; 2077*724ba675SRob Herring 2078*724ba675SRob Herring&prm { 2079*724ba675SRob Herring wkupaon_cm: clock@1800 { 2080*724ba675SRob Herring compatible = "ti,omap4-cm"; 2081*724ba675SRob Herring clock-output-names = "wkupaon_cm"; 2082*724ba675SRob Herring reg = <0x1800 0x100>; 2083*724ba675SRob Herring #address-cells = <1>; 2084*724ba675SRob Herring #size-cells = <1>; 2085*724ba675SRob Herring ranges = <0 0x1800 0x100>; 2086*724ba675SRob Herring 2087*724ba675SRob Herring wkupaon_clkctrl: clock@20 { 2088*724ba675SRob Herring compatible = "ti,clkctrl"; 2089*724ba675SRob Herring clock-output-names = "wkupaon_clkctrl"; 2090*724ba675SRob Herring reg = <0x20 0x6c>; 2091*724ba675SRob Herring #clock-cells = <2>; 2092*724ba675SRob Herring }; 2093*724ba675SRob Herring }; 2094*724ba675SRob Herring}; 2095