1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
4*724ba675SRob Herring *
5*724ba675SRob Herring * Based on "omap4.dtsi"
6*724ba675SRob Herring */
7*724ba675SRob Herring
8*724ba675SRob Herring#include "dra7.dtsi"
9*724ba675SRob Herring
10*724ba675SRob Herring/ {
11*724ba675SRob Herring	compatible = "ti,dra722", "ti,dra72", "ti,dra7";
12*724ba675SRob Herring
13*724ba675SRob Herring	aliases {
14*724ba675SRob Herring		rproc0 = &ipu1;
15*724ba675SRob Herring		rproc1 = &ipu2;
16*724ba675SRob Herring		rproc2 = &dsp1;
17*724ba675SRob Herring	};
18*724ba675SRob Herring
19*724ba675SRob Herring	pmu {
20*724ba675SRob Herring		compatible = "arm,cortex-a15-pmu";
21*724ba675SRob Herring		interrupt-parent = <&wakeupgen>;
22*724ba675SRob Herring		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
23*724ba675SRob Herring	};
24*724ba675SRob Herring};
25*724ba675SRob Herring
26*724ba675SRob Herring&l4_per2 {
27*724ba675SRob Herring	target-module@5b000 {			/* 0x4845b000, ap 59 46.0 */
28*724ba675SRob Herring		compatible = "ti,sysc-omap4", "ti,sysc";
29*724ba675SRob Herring		reg = <0x5b000 0x4>,
30*724ba675SRob Herring		      <0x5b010 0x4>;
31*724ba675SRob Herring		reg-names = "rev", "sysc";
32*724ba675SRob Herring		ti,sysc-midle = <SYSC_IDLE_FORCE>,
33*724ba675SRob Herring				<SYSC_IDLE_NO>;
34*724ba675SRob Herring		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
35*724ba675SRob Herring				<SYSC_IDLE_NO>;
36*724ba675SRob Herring		clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
37*724ba675SRob Herring		clock-names = "fck";
38*724ba675SRob Herring		#address-cells = <1>;
39*724ba675SRob Herring		#size-cells = <1>;
40*724ba675SRob Herring		ranges = <0x0 0x5b000 0x1000>;
41*724ba675SRob Herring
42*724ba675SRob Herring		cal: cal@0 {
43*724ba675SRob Herring			compatible = "ti,dra72-cal";
44*724ba675SRob Herring			reg = <0x0000 0x400>,
45*724ba675SRob Herring			      <0x0800 0x40>,
46*724ba675SRob Herring			      <0x0900 0x40>;
47*724ba675SRob Herring			reg-names = "cal_top",
48*724ba675SRob Herring				    "cal_rx_core0",
49*724ba675SRob Herring				    "cal_rx_core1";
50*724ba675SRob Herring			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
51*724ba675SRob Herring			ti,camerrx-control = <&scm_conf 0xE94>;
52*724ba675SRob Herring
53*724ba675SRob Herring			ports {
54*724ba675SRob Herring				#address-cells = <1>;
55*724ba675SRob Herring				#size-cells = <0>;
56*724ba675SRob Herring
57*724ba675SRob Herring				csi2_0: port@0 {
58*724ba675SRob Herring					reg = <0>;
59*724ba675SRob Herring				};
60*724ba675SRob Herring				csi2_1: port@1 {
61*724ba675SRob Herring					reg = <1>;
62*724ba675SRob Herring				};
63*724ba675SRob Herring			};
64*724ba675SRob Herring		};
65*724ba675SRob Herring	};
66*724ba675SRob Herring};
67*724ba675SRob Herring
68*724ba675SRob Herring&dss {
69*724ba675SRob Herring	reg = <0 0x80>,
70*724ba675SRob Herring	      <0x4054 0x4>,
71*724ba675SRob Herring	      <0x4300 0x20>;
72*724ba675SRob Herring	reg-names = "dss", "pll1_clkctrl", "pll1";
73*724ba675SRob Herring
74*724ba675SRob Herring	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
75*724ba675SRob Herring		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
76*724ba675SRob Herring	clock-names = "fck", "video1_clk";
77*724ba675SRob Herring};
78*724ba675SRob Herring
79*724ba675SRob Herring&mailbox5 {
80*724ba675SRob Herring	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
81*724ba675SRob Herring		ti,mbox-tx = <6 2 2>;
82*724ba675SRob Herring		ti,mbox-rx = <4 2 2>;
83*724ba675SRob Herring		status = "disabled";
84*724ba675SRob Herring	};
85*724ba675SRob Herring	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
86*724ba675SRob Herring		ti,mbox-tx = <5 2 2>;
87*724ba675SRob Herring		ti,mbox-rx = <1 2 2>;
88*724ba675SRob Herring		status = "disabled";
89*724ba675SRob Herring	};
90*724ba675SRob Herring};
91*724ba675SRob Herring
92*724ba675SRob Herring&mailbox6 {
93*724ba675SRob Herring	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
94*724ba675SRob Herring		ti,mbox-tx = <6 2 2>;
95*724ba675SRob Herring		ti,mbox-rx = <4 2 2>;
96*724ba675SRob Herring		status = "disabled";
97*724ba675SRob Herring	};
98*724ba675SRob Herring};
99*724ba675SRob Herring
100*724ba675SRob Herring&pcie1_rc {
101*724ba675SRob Herring	compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
102*724ba675SRob Herring};
103*724ba675SRob Herring
104*724ba675SRob Herring&pcie1_ep {
105*724ba675SRob Herring	compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
106*724ba675SRob Herring};
107*724ba675SRob Herring
108*724ba675SRob Herring&pcie2_rc {
109*724ba675SRob Herring	compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
110*724ba675SRob Herring};
111