1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include <dt-bindings/clock/berlin2q.h> 7*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring model = "Marvell Armada 1500 pro (BG2-Q) SoC"; 11*724ba675SRob Herring compatible = "marvell,berlin2q", "marvell,berlin"; 12*724ba675SRob Herring #address-cells = <1>; 13*724ba675SRob Herring #size-cells = <1>; 14*724ba675SRob Herring 15*724ba675SRob Herring aliases { 16*724ba675SRob Herring serial0 = &uart0; 17*724ba675SRob Herring serial1 = &uart1; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring cpus { 21*724ba675SRob Herring #address-cells = <1>; 22*724ba675SRob Herring #size-cells = <0>; 23*724ba675SRob Herring enable-method = "marvell,berlin-smp"; 24*724ba675SRob Herring 25*724ba675SRob Herring cpu0: cpu@0 { 26*724ba675SRob Herring compatible = "arm,cortex-a9"; 27*724ba675SRob Herring device_type = "cpu"; 28*724ba675SRob Herring next-level-cache = <&l2>; 29*724ba675SRob Herring reg = <0>; 30*724ba675SRob Herring 31*724ba675SRob Herring clocks = <&chip_clk CLKID_CPU>; 32*724ba675SRob Herring clock-latency = <100000>; 33*724ba675SRob Herring /* Can be modified by the bootloader */ 34*724ba675SRob Herring operating-points = < 35*724ba675SRob Herring /* kHz uV */ 36*724ba675SRob Herring 1200000 1200000 37*724ba675SRob Herring 1000000 1200000 38*724ba675SRob Herring 800000 1200000 39*724ba675SRob Herring 600000 1200000 40*724ba675SRob Herring >; 41*724ba675SRob Herring }; 42*724ba675SRob Herring 43*724ba675SRob Herring cpu1: cpu@1 { 44*724ba675SRob Herring compatible = "arm,cortex-a9"; 45*724ba675SRob Herring device_type = "cpu"; 46*724ba675SRob Herring next-level-cache = <&l2>; 47*724ba675SRob Herring reg = <1>; 48*724ba675SRob Herring 49*724ba675SRob Herring clocks = <&chip_clk CLKID_CPU>; 50*724ba675SRob Herring clock-latency = <100000>; 51*724ba675SRob Herring /* Can be modified by the bootloader */ 52*724ba675SRob Herring operating-points = < 53*724ba675SRob Herring /* kHz uV */ 54*724ba675SRob Herring 1200000 1200000 55*724ba675SRob Herring 1000000 1200000 56*724ba675SRob Herring 800000 1200000 57*724ba675SRob Herring 600000 1200000 58*724ba675SRob Herring >; 59*724ba675SRob Herring }; 60*724ba675SRob Herring 61*724ba675SRob Herring cpu2: cpu@2 { 62*724ba675SRob Herring compatible = "arm,cortex-a9"; 63*724ba675SRob Herring device_type = "cpu"; 64*724ba675SRob Herring next-level-cache = <&l2>; 65*724ba675SRob Herring reg = <2>; 66*724ba675SRob Herring 67*724ba675SRob Herring clocks = <&chip_clk CLKID_CPU>; 68*724ba675SRob Herring clock-latency = <100000>; 69*724ba675SRob Herring /* Can be modified by the bootloader */ 70*724ba675SRob Herring operating-points = < 71*724ba675SRob Herring /* kHz uV */ 72*724ba675SRob Herring 1200000 1200000 73*724ba675SRob Herring 1000000 1200000 74*724ba675SRob Herring 800000 1200000 75*724ba675SRob Herring 600000 1200000 76*724ba675SRob Herring >; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring cpu3: cpu@3 { 80*724ba675SRob Herring compatible = "arm,cortex-a9"; 81*724ba675SRob Herring device_type = "cpu"; 82*724ba675SRob Herring next-level-cache = <&l2>; 83*724ba675SRob Herring reg = <3>; 84*724ba675SRob Herring 85*724ba675SRob Herring clocks = <&chip_clk CLKID_CPU>; 86*724ba675SRob Herring clock-latency = <100000>; 87*724ba675SRob Herring /* Can be modified by the bootloader */ 88*724ba675SRob Herring operating-points = < 89*724ba675SRob Herring /* kHz uV */ 90*724ba675SRob Herring 1200000 1200000 91*724ba675SRob Herring 1000000 1200000 92*724ba675SRob Herring 800000 1200000 93*724ba675SRob Herring 600000 1200000 94*724ba675SRob Herring >; 95*724ba675SRob Herring }; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring pmu { 99*724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 100*724ba675SRob Herring interrupt-parent = <&gic>; 101*724ba675SRob Herring interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 102*724ba675SRob Herring <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 103*724ba675SRob Herring <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 104*724ba675SRob Herring <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 105*724ba675SRob Herring interrupt-affinity = <&cpu0>, 106*724ba675SRob Herring <&cpu1>, 107*724ba675SRob Herring <&cpu2>, 108*724ba675SRob Herring <&cpu3>; 109*724ba675SRob Herring }; 110*724ba675SRob Herring 111*724ba675SRob Herring refclk: oscillator { 112*724ba675SRob Herring compatible = "fixed-clock"; 113*724ba675SRob Herring #clock-cells = <0>; 114*724ba675SRob Herring clock-frequency = <25000000>; 115*724ba675SRob Herring }; 116*724ba675SRob Herring 117*724ba675SRob Herring soc@f7000000 { 118*724ba675SRob Herring compatible = "simple-bus"; 119*724ba675SRob Herring #address-cells = <1>; 120*724ba675SRob Herring #size-cells = <1>; 121*724ba675SRob Herring 122*724ba675SRob Herring ranges = <0 0xf7000000 0x1000000>; 123*724ba675SRob Herring interrupt-parent = <&gic>; 124*724ba675SRob Herring 125*724ba675SRob Herring sdhci0: mmc@ab0000 { 126*724ba675SRob Herring compatible = "mrvl,pxav3-mmc"; 127*724ba675SRob Herring reg = <0xab0000 0x200>; 128*724ba675SRob Herring clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; 129*724ba675SRob Herring clock-names = "io", "core"; 130*724ba675SRob Herring interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 131*724ba675SRob Herring status = "disabled"; 132*724ba675SRob Herring }; 133*724ba675SRob Herring 134*724ba675SRob Herring sdhci1: mmc@ab0800 { 135*724ba675SRob Herring compatible = "mrvl,pxav3-mmc"; 136*724ba675SRob Herring reg = <0xab0800 0x200>; 137*724ba675SRob Herring clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; 138*724ba675SRob Herring clock-names = "io", "core"; 139*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 140*724ba675SRob Herring status = "disabled"; 141*724ba675SRob Herring }; 142*724ba675SRob Herring 143*724ba675SRob Herring sdhci2: mmc@ab1000 { 144*724ba675SRob Herring compatible = "mrvl,pxav3-mmc"; 145*724ba675SRob Herring reg = <0xab1000 0x200>; 146*724ba675SRob Herring interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 147*724ba675SRob Herring clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>; 148*724ba675SRob Herring clock-names = "io", "core"; 149*724ba675SRob Herring status = "disabled"; 150*724ba675SRob Herring }; 151*724ba675SRob Herring 152*724ba675SRob Herring l2: cache-controller@ac0000 { 153*724ba675SRob Herring compatible = "arm,pl310-cache"; 154*724ba675SRob Herring reg = <0xac0000 0x1000>; 155*724ba675SRob Herring cache-unified; 156*724ba675SRob Herring cache-level = <2>; 157*724ba675SRob Herring arm,data-latency = <2 2 2>; 158*724ba675SRob Herring arm,tag-latency = <2 2 2>; 159*724ba675SRob Herring }; 160*724ba675SRob Herring 161*724ba675SRob Herring scu: snoop-control-unit@ad0000 { 162*724ba675SRob Herring compatible = "arm,cortex-a9-scu"; 163*724ba675SRob Herring reg = <0xad0000 0x58>; 164*724ba675SRob Herring }; 165*724ba675SRob Herring 166*724ba675SRob Herring local-timer@ad0600 { 167*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 168*724ba675SRob Herring reg = <0xad0600 0x20>; 169*724ba675SRob Herring clocks = <&chip_clk CLKID_TWD>; 170*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 171*724ba675SRob Herring }; 172*724ba675SRob Herring 173*724ba675SRob Herring gic: interrupt-controller@ad1000 { 174*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 175*724ba675SRob Herring reg = <0xad1000 0x1000>, <0xad0100 0x100>; 176*724ba675SRob Herring interrupt-controller; 177*724ba675SRob Herring #interrupt-cells = <3>; 178*724ba675SRob Herring }; 179*724ba675SRob Herring 180*724ba675SRob Herring usb_phy2: phy@a2f400 { 181*724ba675SRob Herring compatible = "marvell,berlin2cd-usb-phy"; 182*724ba675SRob Herring reg = <0xa2f400 0x128>; 183*724ba675SRob Herring #phy-cells = <0>; 184*724ba675SRob Herring resets = <&chip_rst 0x104 14>; 185*724ba675SRob Herring status = "disabled"; 186*724ba675SRob Herring }; 187*724ba675SRob Herring 188*724ba675SRob Herring usb2: usb@a30000 { 189*724ba675SRob Herring compatible = "chipidea,usb2"; 190*724ba675SRob Herring reg = <0xa30000 0x10000>; 191*724ba675SRob Herring interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 192*724ba675SRob Herring clocks = <&chip_clk CLKID_USB2>; 193*724ba675SRob Herring phys = <&usb_phy2>; 194*724ba675SRob Herring phy-names = "usb-phy"; 195*724ba675SRob Herring status = "disabled"; 196*724ba675SRob Herring }; 197*724ba675SRob Herring 198*724ba675SRob Herring usb_phy0: phy@b74000 { 199*724ba675SRob Herring compatible = "marvell,berlin2cd-usb-phy"; 200*724ba675SRob Herring reg = <0xb74000 0x128>; 201*724ba675SRob Herring #phy-cells = <0>; 202*724ba675SRob Herring resets = <&chip_rst 0x104 12>; 203*724ba675SRob Herring status = "disabled"; 204*724ba675SRob Herring }; 205*724ba675SRob Herring 206*724ba675SRob Herring usb_phy1: phy@b78000 { 207*724ba675SRob Herring compatible = "marvell,berlin2cd-usb-phy"; 208*724ba675SRob Herring reg = <0xb78000 0x128>; 209*724ba675SRob Herring #phy-cells = <0>; 210*724ba675SRob Herring resets = <&chip_rst 0x104 13>; 211*724ba675SRob Herring status = "disabled"; 212*724ba675SRob Herring }; 213*724ba675SRob Herring 214*724ba675SRob Herring eth0: ethernet@b90000 { 215*724ba675SRob Herring compatible = "marvell,pxa168-eth"; 216*724ba675SRob Herring reg = <0xb90000 0x10000>; 217*724ba675SRob Herring clocks = <&chip_clk CLKID_GETH0>; 218*724ba675SRob Herring interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 219*724ba675SRob Herring /* set by bootloader */ 220*724ba675SRob Herring local-mac-address = [00 00 00 00 00 00]; 221*724ba675SRob Herring #address-cells = <1>; 222*724ba675SRob Herring #size-cells = <0>; 223*724ba675SRob Herring phy-connection-type = "mii"; 224*724ba675SRob Herring phy-handle = <ðphy0>; 225*724ba675SRob Herring status = "disabled"; 226*724ba675SRob Herring 227*724ba675SRob Herring ethphy0: ethernet-phy@0 { 228*724ba675SRob Herring reg = <0>; 229*724ba675SRob Herring }; 230*724ba675SRob Herring }; 231*724ba675SRob Herring 232*724ba675SRob Herring cpu-ctrl@dd0000 { 233*724ba675SRob Herring compatible = "marvell,berlin-cpu-ctrl"; 234*724ba675SRob Herring reg = <0xdd0000 0x10000>; 235*724ba675SRob Herring }; 236*724ba675SRob Herring 237*724ba675SRob Herring apb@e80000 { 238*724ba675SRob Herring compatible = "simple-bus"; 239*724ba675SRob Herring #address-cells = <1>; 240*724ba675SRob Herring #size-cells = <1>; 241*724ba675SRob Herring 242*724ba675SRob Herring ranges = <0 0xe80000 0x10000>; 243*724ba675SRob Herring interrupt-parent = <&aic>; 244*724ba675SRob Herring 245*724ba675SRob Herring gpio0: gpio@400 { 246*724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 247*724ba675SRob Herring reg = <0x0400 0x400>; 248*724ba675SRob Herring #address-cells = <1>; 249*724ba675SRob Herring #size-cells = <0>; 250*724ba675SRob Herring 251*724ba675SRob Herring porta: gpio-port@0 { 252*724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 253*724ba675SRob Herring gpio-controller; 254*724ba675SRob Herring #gpio-cells = <2>; 255*724ba675SRob Herring ngpios = <32>; 256*724ba675SRob Herring reg = <0>; 257*724ba675SRob Herring interrupt-controller; 258*724ba675SRob Herring #interrupt-cells = <2>; 259*724ba675SRob Herring interrupts = <0>; 260*724ba675SRob Herring }; 261*724ba675SRob Herring }; 262*724ba675SRob Herring 263*724ba675SRob Herring gpio1: gpio@800 { 264*724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 265*724ba675SRob Herring reg = <0x0800 0x400>; 266*724ba675SRob Herring #address-cells = <1>; 267*724ba675SRob Herring #size-cells = <0>; 268*724ba675SRob Herring 269*724ba675SRob Herring portb: gpio-port@1 { 270*724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 271*724ba675SRob Herring gpio-controller; 272*724ba675SRob Herring #gpio-cells = <2>; 273*724ba675SRob Herring ngpios = <32>; 274*724ba675SRob Herring reg = <0>; 275*724ba675SRob Herring interrupt-controller; 276*724ba675SRob Herring #interrupt-cells = <2>; 277*724ba675SRob Herring interrupts = <1>; 278*724ba675SRob Herring }; 279*724ba675SRob Herring }; 280*724ba675SRob Herring 281*724ba675SRob Herring gpio2: gpio@c00 { 282*724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 283*724ba675SRob Herring reg = <0x0c00 0x400>; 284*724ba675SRob Herring #address-cells = <1>; 285*724ba675SRob Herring #size-cells = <0>; 286*724ba675SRob Herring 287*724ba675SRob Herring portc: gpio-port@2 { 288*724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 289*724ba675SRob Herring gpio-controller; 290*724ba675SRob Herring #gpio-cells = <2>; 291*724ba675SRob Herring ngpios = <32>; 292*724ba675SRob Herring reg = <0>; 293*724ba675SRob Herring interrupt-controller; 294*724ba675SRob Herring #interrupt-cells = <2>; 295*724ba675SRob Herring interrupts = <2>; 296*724ba675SRob Herring }; 297*724ba675SRob Herring }; 298*724ba675SRob Herring 299*724ba675SRob Herring gpio3: gpio@1000 { 300*724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 301*724ba675SRob Herring reg = <0x1000 0x400>; 302*724ba675SRob Herring #address-cells = <1>; 303*724ba675SRob Herring #size-cells = <0>; 304*724ba675SRob Herring 305*724ba675SRob Herring portd: gpio-port@3 { 306*724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 307*724ba675SRob Herring gpio-controller; 308*724ba675SRob Herring #gpio-cells = <2>; 309*724ba675SRob Herring ngpios = <32>; 310*724ba675SRob Herring reg = <0>; 311*724ba675SRob Herring interrupt-controller; 312*724ba675SRob Herring #interrupt-cells = <2>; 313*724ba675SRob Herring interrupts = <3>; 314*724ba675SRob Herring }; 315*724ba675SRob Herring }; 316*724ba675SRob Herring 317*724ba675SRob Herring i2c0: i2c@1400 { 318*724ba675SRob Herring compatible = "snps,designware-i2c"; 319*724ba675SRob Herring #address-cells = <1>; 320*724ba675SRob Herring #size-cells = <0>; 321*724ba675SRob Herring reg = <0x1400 0x100>; 322*724ba675SRob Herring interrupts = <4>; 323*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 324*724ba675SRob Herring pinctrl-0 = <&twsi0_pmux>; 325*724ba675SRob Herring pinctrl-names = "default"; 326*724ba675SRob Herring status = "disabled"; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring i2c1: i2c@1800 { 330*724ba675SRob Herring compatible = "snps,designware-i2c"; 331*724ba675SRob Herring #address-cells = <1>; 332*724ba675SRob Herring #size-cells = <0>; 333*724ba675SRob Herring reg = <0x1800 0x100>; 334*724ba675SRob Herring interrupts = <5>; 335*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 336*724ba675SRob Herring pinctrl-0 = <&twsi1_pmux>; 337*724ba675SRob Herring pinctrl-names = "default"; 338*724ba675SRob Herring status = "disabled"; 339*724ba675SRob Herring }; 340*724ba675SRob Herring 341*724ba675SRob Herring timer0: timer@2c00 { 342*724ba675SRob Herring compatible = "snps,dw-apb-timer"; 343*724ba675SRob Herring reg = <0x2c00 0x14>; 344*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 345*724ba675SRob Herring clock-names = "timer"; 346*724ba675SRob Herring interrupts = <8>; 347*724ba675SRob Herring }; 348*724ba675SRob Herring 349*724ba675SRob Herring timer1: timer@2c14 { 350*724ba675SRob Herring compatible = "snps,dw-apb-timer"; 351*724ba675SRob Herring reg = <0x2c14 0x14>; 352*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 353*724ba675SRob Herring clock-names = "timer"; 354*724ba675SRob Herring }; 355*724ba675SRob Herring 356*724ba675SRob Herring timer2: timer@2c28 { 357*724ba675SRob Herring compatible = "snps,dw-apb-timer"; 358*724ba675SRob Herring reg = <0x2c28 0x14>; 359*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 360*724ba675SRob Herring clock-names = "timer"; 361*724ba675SRob Herring status = "disabled"; 362*724ba675SRob Herring }; 363*724ba675SRob Herring 364*724ba675SRob Herring timer3: timer@2c3c { 365*724ba675SRob Herring compatible = "snps,dw-apb-timer"; 366*724ba675SRob Herring reg = <0x2c3c 0x14>; 367*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 368*724ba675SRob Herring clock-names = "timer"; 369*724ba675SRob Herring status = "disabled"; 370*724ba675SRob Herring }; 371*724ba675SRob Herring 372*724ba675SRob Herring timer4: timer@2c50 { 373*724ba675SRob Herring compatible = "snps,dw-apb-timer"; 374*724ba675SRob Herring reg = <0x2c50 0x14>; 375*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 376*724ba675SRob Herring clock-names = "timer"; 377*724ba675SRob Herring status = "disabled"; 378*724ba675SRob Herring }; 379*724ba675SRob Herring 380*724ba675SRob Herring timer5: timer@2c64 { 381*724ba675SRob Herring compatible = "snps,dw-apb-timer"; 382*724ba675SRob Herring reg = <0x2c64 0x14>; 383*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 384*724ba675SRob Herring clock-names = "timer"; 385*724ba675SRob Herring status = "disabled"; 386*724ba675SRob Herring }; 387*724ba675SRob Herring 388*724ba675SRob Herring timer6: timer@2c78 { 389*724ba675SRob Herring compatible = "snps,dw-apb-timer"; 390*724ba675SRob Herring reg = <0x2c78 0x14>; 391*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 392*724ba675SRob Herring clock-names = "timer"; 393*724ba675SRob Herring status = "disabled"; 394*724ba675SRob Herring }; 395*724ba675SRob Herring 396*724ba675SRob Herring timer7: timer@2c8c { 397*724ba675SRob Herring compatible = "snps,dw-apb-timer"; 398*724ba675SRob Herring reg = <0x2c8c 0x14>; 399*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 400*724ba675SRob Herring clock-names = "timer"; 401*724ba675SRob Herring status = "disabled"; 402*724ba675SRob Herring }; 403*724ba675SRob Herring 404*724ba675SRob Herring aic: interrupt-controller@3800 { 405*724ba675SRob Herring compatible = "snps,dw-apb-ictl"; 406*724ba675SRob Herring reg = <0x3800 0x30>; 407*724ba675SRob Herring interrupt-controller; 408*724ba675SRob Herring #interrupt-cells = <1>; 409*724ba675SRob Herring interrupt-parent = <&gic>; 410*724ba675SRob Herring interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 411*724ba675SRob Herring }; 412*724ba675SRob Herring }; 413*724ba675SRob Herring 414*724ba675SRob Herring chip: chip-control@ea0000 { 415*724ba675SRob Herring compatible = "simple-mfd", "syscon"; 416*724ba675SRob Herring reg = <0xea0000 0x400>, <0xdd0170 0x10>; 417*724ba675SRob Herring 418*724ba675SRob Herring chip_clk: clock { 419*724ba675SRob Herring compatible = "marvell,berlin2q-clk"; 420*724ba675SRob Herring #clock-cells = <1>; 421*724ba675SRob Herring clocks = <&refclk>; 422*724ba675SRob Herring clock-names = "refclk"; 423*724ba675SRob Herring }; 424*724ba675SRob Herring 425*724ba675SRob Herring soc_pinctrl: pin-controller { 426*724ba675SRob Herring compatible = "marvell,berlin2q-soc-pinctrl"; 427*724ba675SRob Herring 428*724ba675SRob Herring sd1_pmux: sd1-pmux { 429*724ba675SRob Herring groups = "G31"; 430*724ba675SRob Herring function = "sd1"; 431*724ba675SRob Herring }; 432*724ba675SRob Herring 433*724ba675SRob Herring twsi0_pmux: twsi0-pmux { 434*724ba675SRob Herring groups = "G6"; 435*724ba675SRob Herring function = "twsi0"; 436*724ba675SRob Herring }; 437*724ba675SRob Herring 438*724ba675SRob Herring twsi1_pmux: twsi1-pmux { 439*724ba675SRob Herring groups = "G7"; 440*724ba675SRob Herring function = "twsi1"; 441*724ba675SRob Herring }; 442*724ba675SRob Herring }; 443*724ba675SRob Herring 444*724ba675SRob Herring chip_rst: reset { 445*724ba675SRob Herring compatible = "marvell,berlin2-reset"; 446*724ba675SRob Herring #reset-cells = <2>; 447*724ba675SRob Herring }; 448*724ba675SRob Herring }; 449*724ba675SRob Herring 450*724ba675SRob Herring ahci: sata@e90000 { 451*724ba675SRob Herring compatible = "marvell,berlin2q-ahci", "generic-ahci"; 452*724ba675SRob Herring reg = <0xe90000 0x1000>; 453*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 454*724ba675SRob Herring clocks = <&chip_clk CLKID_SATA>; 455*724ba675SRob Herring #address-cells = <1>; 456*724ba675SRob Herring #size-cells = <0>; 457*724ba675SRob Herring 458*724ba675SRob Herring sata0: sata-port@0 { 459*724ba675SRob Herring reg = <0>; 460*724ba675SRob Herring phys = <&sata_phy 0>; 461*724ba675SRob Herring status = "disabled"; 462*724ba675SRob Herring }; 463*724ba675SRob Herring 464*724ba675SRob Herring sata1: sata-port@1 { 465*724ba675SRob Herring reg = <1>; 466*724ba675SRob Herring phys = <&sata_phy 1>; 467*724ba675SRob Herring status = "disabled"; 468*724ba675SRob Herring }; 469*724ba675SRob Herring }; 470*724ba675SRob Herring 471*724ba675SRob Herring sata_phy: phy@e900a0 { 472*724ba675SRob Herring compatible = "marvell,berlin2q-sata-phy"; 473*724ba675SRob Herring reg = <0xe900a0 0x200>; 474*724ba675SRob Herring clocks = <&chip_clk CLKID_SATA>; 475*724ba675SRob Herring #address-cells = <1>; 476*724ba675SRob Herring #size-cells = <0>; 477*724ba675SRob Herring #phy-cells = <1>; 478*724ba675SRob Herring status = "disabled"; 479*724ba675SRob Herring 480*724ba675SRob Herring sata-phy@0 { 481*724ba675SRob Herring reg = <0>; 482*724ba675SRob Herring }; 483*724ba675SRob Herring 484*724ba675SRob Herring sata-phy@1 { 485*724ba675SRob Herring reg = <1>; 486*724ba675SRob Herring }; 487*724ba675SRob Herring }; 488*724ba675SRob Herring 489*724ba675SRob Herring usb0: usb@ed0000 { 490*724ba675SRob Herring compatible = "chipidea,usb2"; 491*724ba675SRob Herring reg = <0xed0000 0x10000>; 492*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 493*724ba675SRob Herring clocks = <&chip_clk CLKID_USB0>; 494*724ba675SRob Herring phys = <&usb_phy0>; 495*724ba675SRob Herring phy-names = "usb-phy"; 496*724ba675SRob Herring status = "disabled"; 497*724ba675SRob Herring }; 498*724ba675SRob Herring 499*724ba675SRob Herring usb1: usb@ee0000 { 500*724ba675SRob Herring compatible = "chipidea,usb2"; 501*724ba675SRob Herring reg = <0xee0000 0x10000>; 502*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 503*724ba675SRob Herring clocks = <&chip_clk CLKID_USB1>; 504*724ba675SRob Herring phys = <&usb_phy1>; 505*724ba675SRob Herring phy-names = "usb-phy"; 506*724ba675SRob Herring status = "disabled"; 507*724ba675SRob Herring }; 508*724ba675SRob Herring 509*724ba675SRob Herring pwm: pwm@f20000 { 510*724ba675SRob Herring compatible = "marvell,berlin-pwm"; 511*724ba675SRob Herring reg = <0xf20000 0x40>; 512*724ba675SRob Herring clocks = <&chip_clk CLKID_CFG>; 513*724ba675SRob Herring #pwm-cells = <3>; 514*724ba675SRob Herring }; 515*724ba675SRob Herring 516*724ba675SRob Herring apb@fc0000 { 517*724ba675SRob Herring compatible = "simple-bus"; 518*724ba675SRob Herring #address-cells = <1>; 519*724ba675SRob Herring #size-cells = <1>; 520*724ba675SRob Herring 521*724ba675SRob Herring ranges = <0 0xfc0000 0x10000>; 522*724ba675SRob Herring interrupt-parent = <&sic>; 523*724ba675SRob Herring 524*724ba675SRob Herring wdt0: watchdog@1000 { 525*724ba675SRob Herring compatible = "snps,dw-wdt"; 526*724ba675SRob Herring reg = <0x1000 0x100>; 527*724ba675SRob Herring clocks = <&refclk>; 528*724ba675SRob Herring interrupts = <0>; 529*724ba675SRob Herring }; 530*724ba675SRob Herring 531*724ba675SRob Herring wdt1: watchdog@2000 { 532*724ba675SRob Herring compatible = "snps,dw-wdt"; 533*724ba675SRob Herring reg = <0x2000 0x100>; 534*724ba675SRob Herring clocks = <&refclk>; 535*724ba675SRob Herring interrupts = <1>; 536*724ba675SRob Herring }; 537*724ba675SRob Herring 538*724ba675SRob Herring wdt2: watchdog@3000 { 539*724ba675SRob Herring compatible = "snps,dw-wdt"; 540*724ba675SRob Herring reg = <0x3000 0x100>; 541*724ba675SRob Herring clocks = <&refclk>; 542*724ba675SRob Herring interrupts = <2>; 543*724ba675SRob Herring }; 544*724ba675SRob Herring 545*724ba675SRob Herring sm_gpio1: gpio@5000 { 546*724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 547*724ba675SRob Herring reg = <0x5000 0x400>; 548*724ba675SRob Herring #address-cells = <1>; 549*724ba675SRob Herring #size-cells = <0>; 550*724ba675SRob Herring 551*724ba675SRob Herring portf: gpio-port@5 { 552*724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 553*724ba675SRob Herring gpio-controller; 554*724ba675SRob Herring #gpio-cells = <2>; 555*724ba675SRob Herring ngpios = <32>; 556*724ba675SRob Herring reg = <0>; 557*724ba675SRob Herring }; 558*724ba675SRob Herring }; 559*724ba675SRob Herring 560*724ba675SRob Herring i2c2: i2c@7000 { 561*724ba675SRob Herring compatible = "snps,designware-i2c"; 562*724ba675SRob Herring #address-cells = <1>; 563*724ba675SRob Herring #size-cells = <0>; 564*724ba675SRob Herring reg = <0x7000 0x100>; 565*724ba675SRob Herring interrupts = <6>; 566*724ba675SRob Herring clocks = <&refclk>; 567*724ba675SRob Herring pinctrl-0 = <&twsi2_pmux>; 568*724ba675SRob Herring pinctrl-names = "default"; 569*724ba675SRob Herring status = "disabled"; 570*724ba675SRob Herring }; 571*724ba675SRob Herring 572*724ba675SRob Herring i2c3: i2c@8000 { 573*724ba675SRob Herring compatible = "snps,designware-i2c"; 574*724ba675SRob Herring #address-cells = <1>; 575*724ba675SRob Herring #size-cells = <0>; 576*724ba675SRob Herring reg = <0x8000 0x100>; 577*724ba675SRob Herring interrupts = <7>; 578*724ba675SRob Herring clocks = <&refclk>; 579*724ba675SRob Herring pinctrl-0 = <&twsi3_pmux>; 580*724ba675SRob Herring pinctrl-names = "default"; 581*724ba675SRob Herring status = "disabled"; 582*724ba675SRob Herring }; 583*724ba675SRob Herring 584*724ba675SRob Herring uart0: serial@9000 { 585*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 586*724ba675SRob Herring reg = <0x9000 0x100>; 587*724ba675SRob Herring interrupts = <8>; 588*724ba675SRob Herring clocks = <&refclk>; 589*724ba675SRob Herring reg-shift = <2>; 590*724ba675SRob Herring pinctrl-0 = <&uart0_pmux>; 591*724ba675SRob Herring pinctrl-names = "default"; 592*724ba675SRob Herring status = "disabled"; 593*724ba675SRob Herring }; 594*724ba675SRob Herring 595*724ba675SRob Herring uart1: serial@a000 { 596*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 597*724ba675SRob Herring reg = <0xa000 0x100>; 598*724ba675SRob Herring interrupts = <9>; 599*724ba675SRob Herring clocks = <&refclk>; 600*724ba675SRob Herring reg-shift = <2>; 601*724ba675SRob Herring pinctrl-0 = <&uart1_pmux>; 602*724ba675SRob Herring pinctrl-names = "default"; 603*724ba675SRob Herring status = "disabled"; 604*724ba675SRob Herring }; 605*724ba675SRob Herring 606*724ba675SRob Herring sm_gpio0: gpio@c000 { 607*724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 608*724ba675SRob Herring reg = <0xc000 0x400>; 609*724ba675SRob Herring #address-cells = <1>; 610*724ba675SRob Herring #size-cells = <0>; 611*724ba675SRob Herring 612*724ba675SRob Herring porte: gpio-port@4 { 613*724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 614*724ba675SRob Herring gpio-controller; 615*724ba675SRob Herring #gpio-cells = <2>; 616*724ba675SRob Herring ngpios = <32>; 617*724ba675SRob Herring reg = <0>; 618*724ba675SRob Herring }; 619*724ba675SRob Herring }; 620*724ba675SRob Herring 621*724ba675SRob Herring sysctrl: pin-controller@d000 { 622*724ba675SRob Herring compatible = "simple-mfd", "syscon"; 623*724ba675SRob Herring reg = <0xd000 0x100>; 624*724ba675SRob Herring 625*724ba675SRob Herring sys_pinctrl: pin-controller { 626*724ba675SRob Herring compatible = "marvell,berlin2q-system-pinctrl"; 627*724ba675SRob Herring 628*724ba675SRob Herring uart0_pmux: uart0-pmux { 629*724ba675SRob Herring groups = "GSM12"; 630*724ba675SRob Herring function = "uart0"; 631*724ba675SRob Herring }; 632*724ba675SRob Herring 633*724ba675SRob Herring uart1_pmux: uart1-pmux { 634*724ba675SRob Herring groups = "GSM14"; 635*724ba675SRob Herring function = "uart1"; 636*724ba675SRob Herring }; 637*724ba675SRob Herring 638*724ba675SRob Herring twsi2_pmux: twsi2-pmux { 639*724ba675SRob Herring groups = "GSM13"; 640*724ba675SRob Herring function = "twsi2"; 641*724ba675SRob Herring }; 642*724ba675SRob Herring 643*724ba675SRob Herring twsi3_pmux: twsi3-pmux { 644*724ba675SRob Herring groups = "GSM14"; 645*724ba675SRob Herring function = "twsi3"; 646*724ba675SRob Herring }; 647*724ba675SRob Herring }; 648*724ba675SRob Herring 649*724ba675SRob Herring adc: adc { 650*724ba675SRob Herring compatible = "marvell,berlin2-adc"; 651*724ba675SRob Herring interrupts = <12>, <14>; 652*724ba675SRob Herring interrupt-names = "adc", "tsen"; 653*724ba675SRob Herring }; 654*724ba675SRob Herring }; 655*724ba675SRob Herring 656*724ba675SRob Herring sic: interrupt-controller@e000 { 657*724ba675SRob Herring compatible = "snps,dw-apb-ictl"; 658*724ba675SRob Herring reg = <0xe000 0x30>; 659*724ba675SRob Herring interrupt-controller; 660*724ba675SRob Herring #interrupt-cells = <1>; 661*724ba675SRob Herring interrupt-parent = <&gic>; 662*724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 663*724ba675SRob Herring }; 664*724ba675SRob Herring }; 665*724ba675SRob Herring }; 666*724ba675SRob Herring}; 667