1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for Sunplus SP7021 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2021 Sunplus Technology Co. 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring#include "sunplus-sp7021.dtsi" 9*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring compatible = "sunplus,sp7021-achip", "sunplus,sp7021"; 13*724ba675SRob Herring model = "Sunplus SP7021 (CA7)"; 14*724ba675SRob Herring #address-cells = <1>; 15*724ba675SRob Herring #size-cells = <1>; 16*724ba675SRob Herring interrupt-parent = <&gic>; 17*724ba675SRob Herring 18*724ba675SRob Herring cpus { 19*724ba675SRob Herring #address-cells = <1>; 20*724ba675SRob Herring #size-cells = <0>; 21*724ba675SRob Herring 22*724ba675SRob Herring cpu0: cpu@0 { 23*724ba675SRob Herring compatible = "arm,cortex-a7"; 24*724ba675SRob Herring device_type = "cpu"; 25*724ba675SRob Herring reg = <0>; 26*724ba675SRob Herring clock-frequency = <931000000>; 27*724ba675SRob Herring }; 28*724ba675SRob Herring cpu1: cpu@1 { 29*724ba675SRob Herring compatible = "arm,cortex-a7"; 30*724ba675SRob Herring device_type = "cpu"; 31*724ba675SRob Herring reg = <1>; 32*724ba675SRob Herring clock-frequency = <931000000>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring cpu2: cpu@2 { 35*724ba675SRob Herring compatible = "arm,cortex-a7"; 36*724ba675SRob Herring device_type = "cpu"; 37*724ba675SRob Herring reg = <2>; 38*724ba675SRob Herring clock-frequency = <931000000>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring cpu3: cpu@3 { 41*724ba675SRob Herring compatible = "arm,cortex-a7"; 42*724ba675SRob Herring device_type = "cpu"; 43*724ba675SRob Herring reg = <3>; 44*724ba675SRob Herring clock-frequency = <931000000>; 45*724ba675SRob Herring }; 46*724ba675SRob Herring }; 47*724ba675SRob Herring 48*724ba675SRob Herring gic: interrupt-controller@9f101000 { 49*724ba675SRob Herring compatible = "arm,cortex-a7-gic"; 50*724ba675SRob Herring interrupt-controller; 51*724ba675SRob Herring #interrupt-cells = <3>; 52*724ba675SRob Herring reg = <0x9f101000 0x1000>, 53*724ba675SRob Herring <0x9f102000 0x2000>, 54*724ba675SRob Herring <0x9f104000 0x2000>, 55*724ba675SRob Herring <0x9f106000 0x2000>; 56*724ba675SRob Herring }; 57*724ba675SRob Herring 58*724ba675SRob Herring timer { 59*724ba675SRob Herring compatible = "arm,armv7-timer"; 60*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 62*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 63*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 64*724ba675SRob Herring clock-frequency = <XTAL>; 65*724ba675SRob Herring arm,cpu-registers-not-fw-configured; 66*724ba675SRob Herring }; 67*724ba675SRob Herring 68*724ba675SRob Herring arm-pmu { 69*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 70*724ba675SRob Herring interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 71*724ba675SRob Herring <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 72*724ba675SRob Herring <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 73*724ba675SRob Herring <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 74*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring soc@9c000000 { 78*724ba675SRob Herring intc: interrupt-controller@780 { 79*724ba675SRob Herring interrupt-parent = <&gic>; 80*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */ 81*724ba675SRob Herring <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */ 82*724ba675SRob Herring }; 83*724ba675SRob Herring }; 84*724ba675SRob Herring}; 85