1724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2724ba675SRob Herring/*
3724ba675SRob Herring * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
4724ba675SRob Herring * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5724ba675SRob Herring */
6724ba675SRob Herring
7724ba675SRob Herring#include "stm32mp153.dtsi"
8724ba675SRob Herring
9724ba675SRob Herring/ {
10724ba675SRob Herring	soc {
11724ba675SRob Herring		gpu: gpu@59000000 {
12724ba675SRob Herring			compatible = "vivante,gc";
13724ba675SRob Herring			reg = <0x59000000 0x800>;
14724ba675SRob Herring			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
15724ba675SRob Herring			clocks = <&rcc GPU>, <&rcc GPU_K>;
16724ba675SRob Herring			clock-names = "bus" ,"core";
17724ba675SRob Herring			resets = <&rcc GPU_R>;
18724ba675SRob Herring		};
19724ba675SRob Herring
20724ba675SRob Herring		dsi: dsi@5a000000 {
21724ba675SRob Herring			compatible = "st,stm32-dsi";
22724ba675SRob Herring			reg = <0x5a000000 0x800>;
23724ba675SRob Herring			clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
24724ba675SRob Herring			clock-names = "pclk", "ref", "px_clk";
25*5408d518SMarek Vasut			phy-dsi-supply = <&reg18>;
26724ba675SRob Herring			resets = <&rcc DSI_R>;
27724ba675SRob Herring			reset-names = "apb";
28724ba675SRob Herring			status = "disabled";
29*5408d518SMarek Vasut
30*5408d518SMarek Vasut			ports {
31*5408d518SMarek Vasut				#address-cells = <1>;
32*5408d518SMarek Vasut				#size-cells = <0>;
33*5408d518SMarek Vasut
34*5408d518SMarek Vasut				port@0 {
35*5408d518SMarek Vasut					reg = <0>;
36*5408d518SMarek Vasut					dsi_in: endpoint {
37*5408d518SMarek Vasut					};
38*5408d518SMarek Vasut				};
39*5408d518SMarek Vasut
40*5408d518SMarek Vasut				port@1 {
41*5408d518SMarek Vasut					reg = <1>;
42*5408d518SMarek Vasut					dsi_out: endpoint {
43*5408d518SMarek Vasut					};
44*5408d518SMarek Vasut				};
45*5408d518SMarek Vasut			};
46724ba675SRob Herring		};
47724ba675SRob Herring	};
48724ba675SRob Herring};
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