1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) STMicroelectronics 2019 - All Rights Reserved 4*724ba675SRob Herring * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring#include "stm32mp151.dtsi" 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring cpus { 11*724ba675SRob Herring cpu1: cpu@1 { 12*724ba675SRob Herring compatible = "arm,cortex-a7"; 13*724ba675SRob Herring clock-frequency = <650000000>; 14*724ba675SRob Herring device_type = "cpu"; 15*724ba675SRob Herring reg = <1>; 16*724ba675SRob Herring }; 17*724ba675SRob Herring }; 18*724ba675SRob Herring 19*724ba675SRob Herring arm-pmu { 20*724ba675SRob Herring interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 21*724ba675SRob Herring <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 22*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>; 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring timer { 26*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 27*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 28*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 29*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 30*724ba675SRob Herring }; 31*724ba675SRob Herring 32*724ba675SRob Herring soc { 33*724ba675SRob Herring m_can1: can@4400e000 { 34*724ba675SRob Herring compatible = "bosch,m_can"; 35*724ba675SRob Herring reg = <0x4400e000 0x400>, <0x44011000 0x1400>; 36*724ba675SRob Herring reg-names = "m_can", "message_ram"; 37*724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 38*724ba675SRob Herring <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 39*724ba675SRob Herring interrupt-names = "int0", "int1"; 40*724ba675SRob Herring clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; 41*724ba675SRob Herring clock-names = "hclk", "cclk"; 42*724ba675SRob Herring bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; 43*724ba675SRob Herring status = "disabled"; 44*724ba675SRob Herring }; 45*724ba675SRob Herring 46*724ba675SRob Herring m_can2: can@4400f000 { 47*724ba675SRob Herring compatible = "bosch,m_can"; 48*724ba675SRob Herring reg = <0x4400f000 0x400>, <0x44011000 0x2800>; 49*724ba675SRob Herring reg-names = "m_can", "message_ram"; 50*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 51*724ba675SRob Herring <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 52*724ba675SRob Herring interrupt-names = "int0", "int1"; 53*724ba675SRob Herring clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; 54*724ba675SRob Herring clock-names = "hclk", "cclk"; 55*724ba675SRob Herring bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; 56*724ba675SRob Herring status = "disabled"; 57*724ba675SRob Herring }; 58*724ba675SRob Herring }; 59*724ba675SRob Herring}; 60