1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) Protonic Holland 4*724ba675SRob Herring * Author: David Jander <david@protonic.nl> 5*724ba675SRob Herring */ 6*724ba675SRob Herring/dts-v1/; 7*724ba675SRob Herring 8*724ba675SRob Herring#include "stm32mp151a-prtt1l.dtsi" 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring model = "Protonic PRTT1C"; 12*724ba675SRob Herring compatible = "prt,prtt1c", "st,stm32mp151"; 13*724ba675SRob Herring 14*724ba675SRob Herring clock_ksz9031: clock-ksz9031 { 15*724ba675SRob Herring compatible = "fixed-clock"; 16*724ba675SRob Herring #clock-cells = <0>; 17*724ba675SRob Herring clock-frequency = <25000000>; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring clock_sja1105: clock-sja1105 { 21*724ba675SRob Herring compatible = "fixed-clock"; 22*724ba675SRob Herring #clock-cells = <0>; 23*724ba675SRob Herring clock-frequency = <25000000>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring mdio0: mdio { 27*724ba675SRob Herring compatible = "virtual,mdio-gpio"; 28*724ba675SRob Herring #address-cells = <1>; 29*724ba675SRob Herring #size-cells = <0>; 30*724ba675SRob Herring gpios = <&gpioc 1 GPIO_ACTIVE_HIGH 31*724ba675SRob Herring &gpioa 2 GPIO_ACTIVE_HIGH>; 32*724ba675SRob Herring 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring wifi_pwrseq: wifi-pwrseq { 36*724ba675SRob Herring compatible = "mmc-pwrseq-simple"; 37*724ba675SRob Herring reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; 38*724ba675SRob Herring }; 39*724ba675SRob Herring}; 40*724ba675SRob Herring 41*724ba675SRob Herringðernet0 { 42*724ba675SRob Herring fixed-link { 43*724ba675SRob Herring speed = <100>; 44*724ba675SRob Herring full-duplex; 45*724ba675SRob Herring }; 46*724ba675SRob Herring}; 47*724ba675SRob Herring 48*724ba675SRob Herring&gpioa { 49*724ba675SRob Herring gpio-line-names = 50*724ba675SRob Herring "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "", 51*724ba675SRob Herring "", "", "", "", "", "", "", "SPI1_nSS"; 52*724ba675SRob Herring}; 53*724ba675SRob Herring 54*724ba675SRob Herring&gpiod { 55*724ba675SRob Herring gpio-line-names = 56*724ba675SRob Herring "", "", "", "", "", "", "", "", 57*724ba675SRob Herring "WFM_RESET", "", "", "", "", "", "", ""; 58*724ba675SRob Herring}; 59*724ba675SRob Herring 60*724ba675SRob Herring&gpioe { 61*724ba675SRob Herring gpio-line-names = 62*724ba675SRob Herring "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "", 63*724ba675SRob Herring "", "", "", "", "WFM_nIRQ", "", "", ""; 64*724ba675SRob Herring}; 65*724ba675SRob Herring 66*724ba675SRob Herring&gpiog { 67*724ba675SRob Herring gpio-line-names = 68*724ba675SRob Herring "", "", "", "", "", "", "", "PHY3_nINT", 69*724ba675SRob Herring "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET", 70*724ba675SRob Herring "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", ""; 71*724ba675SRob Herring}; 72*724ba675SRob Herring 73*724ba675SRob Herring&mdio0 { 74*724ba675SRob Herring /* All this DP83TD510E PHYs can't be probed before switch@0 is 75*724ba675SRob Herring * probed so we need to use compatible with PHYid 76*724ba675SRob Herring */ 77*724ba675SRob Herring /* TI DP83TD510E */ 78*724ba675SRob Herring t1l0_phy: ethernet-phy@6 { 79*724ba675SRob Herring compatible = "ethernet-phy-id2000.0181"; 80*724ba675SRob Herring reg = <6>; 81*724ba675SRob Herring interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; 82*724ba675SRob Herring reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; 83*724ba675SRob Herring reset-assert-us = <10>; 84*724ba675SRob Herring reset-deassert-us = <35>; 85*724ba675SRob Herring }; 86*724ba675SRob Herring 87*724ba675SRob Herring /* TI DP83TD510E */ 88*724ba675SRob Herring t1l1_phy: ethernet-phy@7 { 89*724ba675SRob Herring compatible = "ethernet-phy-id2000.0181"; 90*724ba675SRob Herring reg = <7>; 91*724ba675SRob Herring interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>; 92*724ba675SRob Herring reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; 93*724ba675SRob Herring reset-assert-us = <10>; 94*724ba675SRob Herring reset-deassert-us = <35>; 95*724ba675SRob Herring }; 96*724ba675SRob Herring 97*724ba675SRob Herring /* TI DP83TD510E */ 98*724ba675SRob Herring t1l2_phy: ethernet-phy@10 { 99*724ba675SRob Herring compatible = "ethernet-phy-id2000.0181"; 100*724ba675SRob Herring reg = <10>; 101*724ba675SRob Herring interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>; 102*724ba675SRob Herring reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; 103*724ba675SRob Herring reset-assert-us = <10>; 104*724ba675SRob Herring reset-deassert-us = <35>; 105*724ba675SRob Herring }; 106*724ba675SRob Herring 107*724ba675SRob Herring /* Micrel KSZ9031 */ 108*724ba675SRob Herring rj45_phy: ethernet-phy@2 { 109*724ba675SRob Herring reg = <2>; 110*724ba675SRob Herring interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; 111*724ba675SRob Herring reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; 112*724ba675SRob Herring reset-assert-us = <10000>; 113*724ba675SRob Herring reset-deassert-us = <1000>; 114*724ba675SRob Herring 115*724ba675SRob Herring clocks = <&clock_ksz9031>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring}; 118*724ba675SRob Herring 119*724ba675SRob Herring&qspi { 120*724ba675SRob Herring status = "disabled"; 121*724ba675SRob Herring}; 122*724ba675SRob Herring 123*724ba675SRob Herring&sdmmc2 { 124*724ba675SRob Herring pinctrl-names = "default", "opendrain", "sleep"; 125*724ba675SRob Herring pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 126*724ba675SRob Herring pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; 127*724ba675SRob Herring pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; 128*724ba675SRob Herring non-removable; 129*724ba675SRob Herring no-sd; 130*724ba675SRob Herring no-sdio; 131*724ba675SRob Herring no-1-8-v; 132*724ba675SRob Herring st,neg-edge; 133*724ba675SRob Herring bus-width = <8>; 134*724ba675SRob Herring vmmc-supply = <®_3v3>; 135*724ba675SRob Herring vqmmc-supply = <®_3v3>; 136*724ba675SRob Herring status = "okay"; 137*724ba675SRob Herring}; 138*724ba675SRob Herring 139*724ba675SRob Herring&sdmmc2_b4_od_pins_a { 140*724ba675SRob Herring pins1 { 141*724ba675SRob Herring pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 142*724ba675SRob Herring <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ 143*724ba675SRob Herring <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 144*724ba675SRob Herring <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 145*724ba675SRob Herring }; 146*724ba675SRob Herring}; 147*724ba675SRob Herring 148*724ba675SRob Herring&sdmmc2_b4_pins_a { 149*724ba675SRob Herring pins1 { 150*724ba675SRob Herring pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 151*724ba675SRob Herring <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ 152*724ba675SRob Herring <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 153*724ba675SRob Herring <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 154*724ba675SRob Herring <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 155*724ba675SRob Herring }; 156*724ba675SRob Herring}; 157*724ba675SRob Herring 158*724ba675SRob Herring&sdmmc2_b4_sleep_pins_a { 159*724ba675SRob Herring pins { 160*724ba675SRob Herring pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 161*724ba675SRob Herring <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */ 162*724ba675SRob Herring <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 163*724ba675SRob Herring <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 164*724ba675SRob Herring <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 165*724ba675SRob Herring <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 166*724ba675SRob Herring }; 167*724ba675SRob Herring}; 168*724ba675SRob Herring 169*724ba675SRob Herring&sdmmc2_d47_pins_a { 170*724ba675SRob Herring pins { 171*724ba675SRob Herring pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 172*724ba675SRob Herring <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 173*724ba675SRob Herring <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 174*724ba675SRob Herring <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 175*724ba675SRob Herring }; 176*724ba675SRob Herring}; 177*724ba675SRob Herring 178*724ba675SRob Herring&sdmmc2_d47_sleep_pins_a { 179*724ba675SRob Herring pins { 180*724ba675SRob Herring pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 181*724ba675SRob Herring <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 182*724ba675SRob Herring <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 183*724ba675SRob Herring <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ 184*724ba675SRob Herring }; 185*724ba675SRob Herring}; 186*724ba675SRob Herring 187*724ba675SRob Herring&sdmmc3 { 188*724ba675SRob Herring pinctrl-names = "default", "opendrain", "sleep"; 189*724ba675SRob Herring pinctrl-0 = <&sdmmc3_b4_pins_b>; 190*724ba675SRob Herring pinctrl-1 = <&sdmmc3_b4_od_pins_b>; 191*724ba675SRob Herring pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; 192*724ba675SRob Herring non-removable; 193*724ba675SRob Herring no-1-8-v; 194*724ba675SRob Herring st,neg-edge; 195*724ba675SRob Herring bus-width = <4>; 196*724ba675SRob Herring vmmc-supply = <®_3v3>; 197*724ba675SRob Herring vqmmc-supply = <®_3v3>; 198*724ba675SRob Herring mmc-pwrseq = <&wifi_pwrseq>; 199*724ba675SRob Herring #address-cells = <1>; 200*724ba675SRob Herring #size-cells = <0>; 201*724ba675SRob Herring status = "okay"; 202*724ba675SRob Herring 203*724ba675SRob Herring mmc@1 { 204*724ba675SRob Herring compatible = "prt,prtt1c-wfm200", "silabs,wf200"; 205*724ba675SRob Herring reg = <1>; 206*724ba675SRob Herring }; 207*724ba675SRob Herring}; 208*724ba675SRob Herring 209*724ba675SRob Herring&sdmmc3_b4_od_pins_b { 210*724ba675SRob Herring pins1 { 211*724ba675SRob Herring pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ 212*724ba675SRob Herring <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ 213*724ba675SRob Herring <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 214*724ba675SRob Herring <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 215*724ba675SRob Herring }; 216*724ba675SRob Herring}; 217*724ba675SRob Herring 218*724ba675SRob Herring&sdmmc3_b4_pins_b { 219*724ba675SRob Herring pins1 { 220*724ba675SRob Herring pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ 221*724ba675SRob Herring <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ 222*724ba675SRob Herring <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 223*724ba675SRob Herring <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 224*724ba675SRob Herring <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ 225*724ba675SRob Herring }; 226*724ba675SRob Herring}; 227*724ba675SRob Herring 228*724ba675SRob Herring&sdmmc3_b4_sleep_pins_b { 229*724ba675SRob Herring pins { 230*724ba675SRob Herring pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */ 231*724ba675SRob Herring <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */ 232*724ba675SRob Herring <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ 233*724ba675SRob Herring <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 234*724ba675SRob Herring <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 235*724ba675SRob Herring <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ 236*724ba675SRob Herring }; 237*724ba675SRob Herring}; 238*724ba675SRob Herring 239*724ba675SRob Herring&spi1 { 240*724ba675SRob Herring pinctrl-0 = <&spi1_pins_b>; 241*724ba675SRob Herring pinctrl-names = "default"; 242*724ba675SRob Herring cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; 243*724ba675SRob Herring /delete-property/dmas; 244*724ba675SRob Herring /delete-property/dma-names; 245*724ba675SRob Herring status = "okay"; 246*724ba675SRob Herring 247*724ba675SRob Herring switch@0 { 248*724ba675SRob Herring compatible = "nxp,sja1105q"; 249*724ba675SRob Herring reg = <0>; 250*724ba675SRob Herring spi-max-frequency = <4000000>; 251*724ba675SRob Herring spi-rx-delay-us = <1>; 252*724ba675SRob Herring spi-tx-delay-us = <1>; 253*724ba675SRob Herring spi-cpha; 254*724ba675SRob Herring 255*724ba675SRob Herring reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>; 256*724ba675SRob Herring 257*724ba675SRob Herring clocks = <&clock_sja1105>; 258*724ba675SRob Herring 259*724ba675SRob Herring ports { 260*724ba675SRob Herring #address-cells = <1>; 261*724ba675SRob Herring #size-cells = <0>; 262*724ba675SRob Herring 263*724ba675SRob Herring port@0 { 264*724ba675SRob Herring reg = <0>; 265*724ba675SRob Herring label = "t1l0"; 266*724ba675SRob Herring phy-mode = "rmii"; 267*724ba675SRob Herring phy-handle = <&t1l0_phy>; 268*724ba675SRob Herring }; 269*724ba675SRob Herring 270*724ba675SRob Herring port@1 { 271*724ba675SRob Herring reg = <1>; 272*724ba675SRob Herring label = "t1l1"; 273*724ba675SRob Herring phy-mode = "rmii"; 274*724ba675SRob Herring phy-handle = <&t1l1_phy>; 275*724ba675SRob Herring }; 276*724ba675SRob Herring 277*724ba675SRob Herring port@2 { 278*724ba675SRob Herring reg = <2>; 279*724ba675SRob Herring label = "t1l2"; 280*724ba675SRob Herring phy-mode = "rmii"; 281*724ba675SRob Herring phy-handle = <&t1l2_phy>; 282*724ba675SRob Herring }; 283*724ba675SRob Herring 284*724ba675SRob Herring port@3 { 285*724ba675SRob Herring reg = <3>; 286*724ba675SRob Herring label = "rj45"; 287*724ba675SRob Herring phy-handle = <&rj45_phy>; 288*724ba675SRob Herring phy-mode = "rgmii-id"; 289*724ba675SRob Herring }; 290*724ba675SRob Herring 291*724ba675SRob Herring port@4 { 292*724ba675SRob Herring reg = <4>; 293*724ba675SRob Herring label = "cpu"; 294*724ba675SRob Herring ethernet = <ðernet0>; 295*724ba675SRob Herring phy-mode = "rmii"; 296*724ba675SRob Herring 297*724ba675SRob Herring fixed-link { 298*724ba675SRob Herring speed = <100>; 299*724ba675SRob Herring full-duplex; 300*724ba675SRob Herring }; 301*724ba675SRob Herring }; 302*724ba675SRob Herring }; 303*724ba675SRob Herring }; 304*724ba675SRob Herring}; 305