1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp13-clks.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23	};
24
25	arm-pmu {
26		compatible = "arm,cortex-a7-pmu";
27		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
28		interrupt-affinity = <&cpu0>;
29		interrupt-parent = <&intc>;
30	};
31
32	firmware {
33		optee {
34			method = "smc";
35			compatible = "linaro,optee-tz";
36		};
37
38		scmi: scmi {
39			compatible = "linaro,scmi-optee";
40			#address-cells = <1>;
41			#size-cells = <0>;
42			linaro,optee-channel-id = <0>;
43
44			scmi_clk: protocol@14 {
45				reg = <0x14>;
46				#clock-cells = <1>;
47			};
48
49			scmi_reset: protocol@16 {
50				reg = <0x16>;
51				#reset-cells = <1>;
52			};
53		};
54	};
55
56	intc: interrupt-controller@a0021000 {
57		compatible = "arm,cortex-a7-gic";
58		#interrupt-cells = <3>;
59		interrupt-controller;
60		reg = <0xa0021000 0x1000>,
61		      <0xa0022000 0x2000>;
62	};
63
64	psci {
65		compatible = "arm,psci-1.0";
66		method = "smc";
67	};
68
69	timer {
70		compatible = "arm,armv7-timer";
71		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
72			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
73			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
74			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
75		interrupt-parent = <&intc>;
76		always-on;
77	};
78
79	/* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
80	reg11: reg11 {
81		compatible = "regulator-fixed";
82		regulator-name = "reg11";
83		regulator-min-microvolt = <1100000>;
84		regulator-max-microvolt = <1100000>;
85	};
86
87	reg18: reg18 {
88		compatible = "regulator-fixed";
89		regulator-name = "reg18";
90		regulator-min-microvolt = <1800000>;
91		regulator-max-microvolt = <1800000>;
92	};
93
94	usb33: usb33 {
95		compatible = "regulator-fixed";
96		regulator-name = "usb33";
97		regulator-min-microvolt = <3300000>;
98		regulator-max-microvolt = <3300000>;
99	};
100
101	soc {
102		compatible = "simple-bus";
103		#address-cells = <1>;
104		#size-cells = <1>;
105		interrupt-parent = <&intc>;
106		ranges;
107
108		timers2: timer@40000000 {
109			#address-cells = <1>;
110			#size-cells = <0>;
111			compatible = "st,stm32-timers";
112			reg = <0x40000000 0x400>;
113			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
114			interrupt-names = "global";
115			clocks = <&rcc TIM2_K>;
116			clock-names = "int";
117			dmas = <&dmamux1 18 0x400 0x1>,
118			       <&dmamux1 19 0x400 0x1>,
119			       <&dmamux1 20 0x400 0x1>,
120			       <&dmamux1 21 0x400 0x1>,
121			       <&dmamux1 22 0x400 0x1>;
122			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
123			status = "disabled";
124
125			pwm {
126				compatible = "st,stm32-pwm";
127				#pwm-cells = <3>;
128				status = "disabled";
129			};
130
131			timer@1 {
132				compatible = "st,stm32h7-timer-trigger";
133				reg = <1>;
134				status = "disabled";
135			};
136
137			counter {
138				compatible = "st,stm32-timer-counter";
139				status = "disabled";
140			};
141		};
142
143		timers3: timer@40001000 {
144			#address-cells = <1>;
145			#size-cells = <0>;
146			compatible = "st,stm32-timers";
147			reg = <0x40001000 0x400>;
148			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
149			interrupt-names = "global";
150			clocks = <&rcc TIM3_K>;
151			clock-names = "int";
152			dmas = <&dmamux1 23 0x400 0x1>,
153			       <&dmamux1 24 0x400 0x1>,
154			       <&dmamux1 25 0x400 0x1>,
155			       <&dmamux1 26 0x400 0x1>,
156			       <&dmamux1 27 0x400 0x1>,
157			       <&dmamux1 28 0x400 0x1>;
158			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
159			status = "disabled";
160
161			pwm {
162				compatible = "st,stm32-pwm";
163				#pwm-cells = <3>;
164				status = "disabled";
165			};
166
167			timer@2 {
168				compatible = "st,stm32h7-timer-trigger";
169				reg = <2>;
170				status = "disabled";
171			};
172
173			counter {
174				compatible = "st,stm32-timer-counter";
175				status = "disabled";
176			};
177		};
178
179		timers4: timer@40002000 {
180			#address-cells = <1>;
181			#size-cells = <0>;
182			compatible = "st,stm32-timers";
183			reg = <0x40002000 0x400>;
184			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
185			interrupt-names = "global";
186			clocks = <&rcc TIM4_K>;
187			clock-names = "int";
188			dmas = <&dmamux1 29 0x400 0x1>,
189			       <&dmamux1 30 0x400 0x1>,
190			       <&dmamux1 31 0x400 0x1>,
191			       <&dmamux1 32 0x400 0x1>;
192			dma-names = "ch1", "ch2", "ch3", "up";
193			status = "disabled";
194
195			pwm {
196				compatible = "st,stm32-pwm";
197				#pwm-cells = <3>;
198				status = "disabled";
199			};
200
201			timer@3 {
202				compatible = "st,stm32h7-timer-trigger";
203				reg = <3>;
204				status = "disabled";
205			};
206
207			counter {
208				compatible = "st,stm32-timer-counter";
209				status = "disabled";
210			};
211		};
212
213		timers5: timer@40003000 {
214			#address-cells = <1>;
215			#size-cells = <0>;
216			compatible = "st,stm32-timers";
217			reg = <0x40003000 0x400>;
218			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
219			interrupt-names = "global";
220			clocks = <&rcc TIM5_K>;
221			clock-names = "int";
222			dmas = <&dmamux1 55 0x400 0x1>,
223			       <&dmamux1 56 0x400 0x1>,
224			       <&dmamux1 57 0x400 0x1>,
225			       <&dmamux1 58 0x400 0x1>,
226			       <&dmamux1 59 0x400 0x1>,
227			       <&dmamux1 60 0x400 0x1>;
228			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
229			status = "disabled";
230
231			pwm {
232				compatible = "st,stm32-pwm";
233				#pwm-cells = <3>;
234				status = "disabled";
235			};
236
237			timer@4 {
238				compatible = "st,stm32h7-timer-trigger";
239				reg = <4>;
240				status = "disabled";
241			};
242
243			counter {
244				compatible = "st,stm32-timer-counter";
245				status = "disabled";
246			};
247		};
248
249		timers6: timer@40004000 {
250			#address-cells = <1>;
251			#size-cells = <0>;
252			compatible = "st,stm32-timers";
253			reg = <0x40004000 0x400>;
254			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
255			interrupt-names = "global";
256			clocks = <&rcc TIM6_K>;
257			clock-names = "int";
258			dmas = <&dmamux1 69 0x400 0x1>;
259			dma-names = "up";
260			status = "disabled";
261
262			timer@5 {
263				compatible = "st,stm32h7-timer-trigger";
264				reg = <5>;
265				status = "disabled";
266			};
267		};
268
269		timers7: timer@40005000 {
270			#address-cells = <1>;
271			#size-cells = <0>;
272			compatible = "st,stm32-timers";
273			reg = <0x40005000 0x400>;
274			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
275			interrupt-names = "global";
276			clocks = <&rcc TIM7_K>;
277			clock-names = "int";
278			dmas = <&dmamux1 70 0x400 0x1>;
279			dma-names = "up";
280			status = "disabled";
281
282			timer@6 {
283				compatible = "st,stm32h7-timer-trigger";
284				reg = <6>;
285				status = "disabled";
286			};
287		};
288
289		lptimer1: timer@40009000 {
290			#address-cells = <1>;
291			#size-cells = <0>;
292			compatible = "st,stm32-lptimer";
293			reg = <0x40009000 0x400>;
294			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
295			clocks = <&rcc LPTIM1_K>;
296			clock-names = "mux";
297			wakeup-source;
298			status = "disabled";
299
300			pwm {
301				compatible = "st,stm32-pwm-lp";
302				#pwm-cells = <3>;
303				status = "disabled";
304			};
305
306			trigger@0 {
307				compatible = "st,stm32-lptimer-trigger";
308				reg = <0>;
309				status = "disabled";
310			};
311
312			counter {
313				compatible = "st,stm32-lptimer-counter";
314				status = "disabled";
315			};
316
317			timer {
318				compatible = "st,stm32-lptimer-timer";
319				status = "disabled";
320			};
321		};
322
323		i2s2: audio-controller@4000b000 {
324			compatible = "st,stm32h7-i2s";
325			reg = <0x4000b000 0x400>;
326			#sound-dai-cells = <0>;
327			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
328			dmas = <&dmamux1 39 0x400 0x01>,
329			       <&dmamux1 40 0x400 0x01>;
330			dma-names = "rx", "tx";
331			status = "disabled";
332		};
333
334		spi2: spi@4000b000 {
335			compatible = "st,stm32h7-spi";
336			reg = <0x4000b000 0x400>;
337			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
338			clocks = <&rcc SPI2_K>;
339			resets = <&rcc SPI2_R>;
340			#address-cells = <1>;
341			#size-cells = <0>;
342			dmas = <&dmamux1 39 0x400 0x01>,
343			       <&dmamux1 40 0x400 0x01>;
344			dma-names = "rx", "tx";
345			status = "disabled";
346		};
347
348		i2s3: audio-controller@4000c000 {
349			compatible = "st,stm32h7-i2s";
350			reg = <0x4000c000 0x400>;
351			#sound-dai-cells = <0>;
352			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
353			dmas = <&dmamux1 61 0x400 0x01>,
354			       <&dmamux1 62 0x400 0x01>;
355			dma-names = "rx", "tx";
356			status = "disabled";
357		};
358
359		spi3: spi@4000c000 {
360			compatible = "st,stm32h7-spi";
361			reg = <0x4000c000 0x400>;
362			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
363			clocks = <&rcc SPI3_K>;
364			resets = <&rcc SPI3_R>;
365			#address-cells = <1>;
366			#size-cells = <0>;
367			dmas = <&dmamux1 61 0x400 0x01>,
368			       <&dmamux1 62 0x400 0x01>;
369			dma-names = "rx", "tx";
370			status = "disabled";
371		};
372
373		spdifrx: audio-controller@4000d000 {
374			compatible = "st,stm32h7-spdifrx";
375			reg = <0x4000d000 0x400>;
376			#sound-dai-cells = <0>;
377			clocks = <&rcc SPDIF_K>;
378			clock-names = "kclk";
379			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
380			dmas = <&dmamux1 93 0x400 0x01>,
381			       <&dmamux1 94 0x400 0x01>;
382			dma-names = "rx", "rx-ctrl";
383			status = "disabled";
384		};
385
386		usart3: serial@4000f000 {
387			compatible = "st,stm32h7-uart";
388			reg = <0x4000f000 0x400>;
389			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
390			clocks = <&rcc USART3_K>;
391			resets = <&rcc USART3_R>;
392			wakeup-source;
393			dmas = <&dmamux1 45 0x400 0x5>,
394			       <&dmamux1 46 0x400 0x1>;
395			dma-names = "rx", "tx";
396			status = "disabled";
397		};
398
399		uart4: serial@40010000 {
400			compatible = "st,stm32h7-uart";
401			reg = <0x40010000 0x400>;
402			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
403			clocks = <&rcc UART4_K>;
404			resets = <&rcc UART4_R>;
405			wakeup-source;
406			dmas = <&dmamux1 63 0x400 0x5>,
407			       <&dmamux1 64 0x400 0x1>;
408			dma-names = "rx", "tx";
409			status = "disabled";
410		};
411
412		uart5: serial@40011000 {
413			compatible = "st,stm32h7-uart";
414			reg = <0x40011000 0x400>;
415			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
416			clocks = <&rcc UART5_K>;
417			resets = <&rcc UART5_R>;
418			wakeup-source;
419			dmas = <&dmamux1 65 0x400 0x5>,
420			       <&dmamux1 66 0x400 0x1>;
421			dma-names = "rx", "tx";
422			status = "disabled";
423		};
424
425		i2c1: i2c@40012000 {
426			compatible = "st,stm32mp13-i2c";
427			reg = <0x40012000 0x400>;
428			interrupt-names = "event", "error";
429			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
430				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
431			clocks = <&rcc I2C1_K>;
432			resets = <&rcc I2C1_R>;
433			#address-cells = <1>;
434			#size-cells = <0>;
435			dmas = <&dmamux1 33 0x400 0x1>,
436			       <&dmamux1 34 0x400 0x1>;
437			dma-names = "rx", "tx";
438			st,syscfg-fmp = <&syscfg 0x4 0x1>;
439			i2c-analog-filter;
440			status = "disabled";
441		};
442
443		i2c2: i2c@40013000 {
444			compatible = "st,stm32mp13-i2c";
445			reg = <0x40013000 0x400>;
446			interrupt-names = "event", "error";
447			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
448				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
449			clocks = <&rcc I2C2_K>;
450			resets = <&rcc I2C2_R>;
451			#address-cells = <1>;
452			#size-cells = <0>;
453			dmas = <&dmamux1 35 0x400 0x1>,
454			       <&dmamux1 36 0x400 0x1>;
455			dma-names = "rx", "tx";
456			st,syscfg-fmp = <&syscfg 0x4 0x2>;
457			i2c-analog-filter;
458			status = "disabled";
459		};
460
461		uart7: serial@40018000 {
462			compatible = "st,stm32h7-uart";
463			reg = <0x40018000 0x400>;
464			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
465			clocks = <&rcc UART7_K>;
466			resets = <&rcc UART7_R>;
467			wakeup-source;
468			dmas = <&dmamux1 79 0x400 0x5>,
469			       <&dmamux1 80 0x400 0x1>;
470			dma-names = "rx", "tx";
471			status = "disabled";
472		};
473
474		uart8: serial@40019000 {
475			compatible = "st,stm32h7-uart";
476			reg = <0x40019000 0x400>;
477			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
478			clocks = <&rcc UART8_K>;
479			resets = <&rcc UART8_R>;
480			wakeup-source;
481			dmas = <&dmamux1 81 0x400 0x5>,
482			       <&dmamux1 82 0x400 0x1>;
483			dma-names = "rx", "tx";
484			status = "disabled";
485		};
486
487		timers1: timer@44000000 {
488			#address-cells = <1>;
489			#size-cells = <0>;
490			compatible = "st,stm32-timers";
491			reg = <0x44000000 0x400>;
492			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
493				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
494				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
495				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
496			interrupt-names = "brk", "up", "trg-com", "cc";
497			clocks = <&rcc TIM1_K>;
498			clock-names = "int";
499			dmas = <&dmamux1 11 0x400 0x1>,
500			       <&dmamux1 12 0x400 0x1>,
501			       <&dmamux1 13 0x400 0x1>,
502			       <&dmamux1 14 0x400 0x1>,
503			       <&dmamux1 15 0x400 0x1>,
504			       <&dmamux1 16 0x400 0x1>,
505			       <&dmamux1 17 0x400 0x1>;
506			dma-names = "ch1", "ch2", "ch3", "ch4",
507				    "up", "trig", "com";
508			status = "disabled";
509
510			pwm {
511				compatible = "st,stm32-pwm";
512				#pwm-cells = <3>;
513				status = "disabled";
514			};
515
516			timer@0 {
517				compatible = "st,stm32h7-timer-trigger";
518				reg = <0>;
519				status = "disabled";
520			};
521
522			counter {
523				compatible = "st,stm32-timer-counter";
524				status = "disabled";
525			};
526		};
527
528		timers8: timer@44001000 {
529			#address-cells = <1>;
530			#size-cells = <0>;
531			compatible = "st,stm32-timers";
532			reg = <0x44001000 0x400>;
533			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
534				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
535				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
536				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
537			interrupt-names = "brk", "up", "trg-com", "cc";
538			clocks = <&rcc TIM8_K>;
539			clock-names = "int";
540			dmas = <&dmamux1 47 0x400 0x1>,
541			       <&dmamux1 48 0x400 0x1>,
542			       <&dmamux1 49 0x400 0x1>,
543			       <&dmamux1 50 0x400 0x1>,
544			       <&dmamux1 51 0x400 0x1>,
545			       <&dmamux1 52 0x400 0x1>,
546			       <&dmamux1 53 0x400 0x1>;
547			dma-names = "ch1", "ch2", "ch3", "ch4",
548				    "up", "trig", "com";
549			status = "disabled";
550
551			pwm {
552				compatible = "st,stm32-pwm";
553				#pwm-cells = <3>;
554				status = "disabled";
555			};
556
557			timer@7 {
558				compatible = "st,stm32h7-timer-trigger";
559				reg = <7>;
560				status = "disabled";
561			};
562
563			counter {
564				compatible = "st,stm32-timer-counter";
565				status = "disabled";
566			};
567		};
568
569		usart6: serial@44003000 {
570			compatible = "st,stm32h7-uart";
571			reg = <0x44003000 0x400>;
572			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
573			clocks = <&rcc USART6_K>;
574			resets = <&rcc USART6_R>;
575			wakeup-source;
576			dmas = <&dmamux1 71 0x400 0x5>,
577			       <&dmamux1 72 0x400 0x1>;
578			dma-names = "rx", "tx";
579			status = "disabled";
580		};
581
582		i2s1: audio-controller@44004000 {
583			compatible = "st,stm32h7-i2s";
584			reg = <0x44004000 0x400>;
585			#sound-dai-cells = <0>;
586			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
587			dmas = <&dmamux1 37 0x400 0x01>,
588			       <&dmamux1 38 0x400 0x01>;
589			dma-names = "rx", "tx";
590			status = "disabled";
591		};
592
593		spi1: spi@44004000 {
594			compatible = "st,stm32h7-spi";
595			reg = <0x44004000 0x400>;
596			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
597			clocks = <&rcc SPI1_K>;
598			resets = <&rcc SPI1_R>;
599			#address-cells = <1>;
600			#size-cells = <0>;
601			dmas = <&dmamux1 37 0x400 0x01>,
602			       <&dmamux1 38 0x400 0x01>;
603			dma-names = "rx", "tx";
604			status = "disabled";
605		};
606
607		sai1: sai@4400a000 {
608			compatible = "st,stm32h7-sai";
609			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
610			ranges = <0 0x4400a000 0x400>;
611			#address-cells = <1>;
612			#size-cells = <1>;
613			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
614			resets = <&rcc SAI1_R>;
615			status = "disabled";
616
617			sai1a: audio-controller@4400a004 {
618				compatible = "st,stm32-sai-sub-a";
619				reg = <0x4 0x20>;
620				#sound-dai-cells = <0>;
621				clocks = <&rcc SAI1_K>;
622				clock-names = "sai_ck";
623				dmas = <&dmamux1 87 0x400 0x01>;
624				status = "disabled";
625			};
626
627			sai1b: audio-controller@4400a024 {
628				compatible = "st,stm32-sai-sub-b";
629				reg = <0x24 0x20>;
630				#sound-dai-cells = <0>;
631				clocks = <&rcc SAI1_K>;
632				clock-names = "sai_ck";
633				dmas = <&dmamux1 88 0x400 0x01>;
634				status = "disabled";
635			};
636		};
637
638		sai2: sai@4400b000 {
639			compatible = "st,stm32h7-sai";
640			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
641			ranges = <0 0x4400b000 0x400>;
642			#address-cells = <1>;
643			#size-cells = <1>;
644			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
645			resets = <&rcc SAI2_R>;
646			status = "disabled";
647
648			sai2a: audio-controller@4400b004 {
649				compatible = "st,stm32-sai-sub-a";
650				reg = <0x4 0x20>;
651				#sound-dai-cells = <0>;
652				clocks = <&rcc SAI2_K>;
653				clock-names = "sai_ck";
654				dmas = <&dmamux1 89 0x400 0x01>;
655				status = "disabled";
656			};
657
658			sai2b: audio-controller@4400b024 {
659				compatible = "st,stm32-sai-sub-b";
660				reg = <0x24 0x20>;
661				#sound-dai-cells = <0>;
662				clocks = <&rcc SAI2_K>;
663				clock-names = "sai_ck";
664				dmas = <&dmamux1 90 0x400 0x01>;
665				status = "disabled";
666			};
667		};
668
669		dfsdm: dfsdm@4400d000 {
670			compatible = "st,stm32mp1-dfsdm";
671			reg = <0x4400d000 0x800>;
672			clocks = <&rcc DFSDM_K>;
673			clock-names = "dfsdm";
674			#address-cells = <1>;
675			#size-cells = <0>;
676			status = "disabled";
677
678			dfsdm0: filter@0 {
679				compatible = "st,stm32-dfsdm-adc";
680				reg = <0>;
681				#io-channel-cells = <1>;
682				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
683				dmas = <&dmamux1 101 0x400 0x01>;
684				dma-names = "rx";
685				status = "disabled";
686			};
687
688			dfsdm1: filter@1 {
689				compatible = "st,stm32-dfsdm-adc";
690				reg = <1>;
691				#io-channel-cells = <1>;
692				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
693				dmas = <&dmamux1 102 0x400 0x01>;
694				dma-names = "rx";
695				status = "disabled";
696			};
697		};
698
699		dma1: dma-controller@48000000 {
700			compatible = "st,stm32-dma";
701			reg = <0x48000000 0x400>;
702			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
703				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
704				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
705				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
706				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
707				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
708				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
709				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
710			clocks = <&rcc DMA1>;
711			resets = <&rcc DMA1_R>;
712			#dma-cells = <4>;
713			st,mem2mem;
714			dma-requests = <8>;
715		};
716
717		dma2: dma-controller@48001000 {
718			compatible = "st,stm32-dma";
719			reg = <0x48001000 0x400>;
720			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
721				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
722				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
723				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
724				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
725				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
726				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
727				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
728			clocks = <&rcc DMA2>;
729			resets = <&rcc DMA2_R>;
730			#dma-cells = <4>;
731			st,mem2mem;
732			dma-requests = <8>;
733		};
734
735		dmamux1: dma-router@48002000 {
736			compatible = "st,stm32h7-dmamux";
737			reg = <0x48002000 0x40>;
738			clocks = <&rcc DMAMUX1>;
739			resets = <&rcc DMAMUX1_R>;
740			#dma-cells = <3>;
741			dma-masters = <&dma1 &dma2>;
742			dma-requests = <128>;
743			dma-channels = <16>;
744		};
745
746		adc_2: adc@48004000 {
747			compatible = "st,stm32mp13-adc-core";
748			reg = <0x48004000 0x400>;
749			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
750			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
751			clock-names = "bus", "adc";
752			interrupt-controller;
753			#interrupt-cells = <1>;
754			#address-cells = <1>;
755			#size-cells = <0>;
756			status = "disabled";
757
758			adc2: adc@0 {
759				compatible = "st,stm32mp13-adc";
760				#io-channel-cells = <1>;
761				#address-cells = <1>;
762				#size-cells = <0>;
763				reg = <0x0>;
764				interrupt-parent = <&adc_2>;
765				interrupts = <0>;
766				dmas = <&dmamux1 10 0x400 0x80000001>;
767				dma-names = "rx";
768				status = "disabled";
769
770				channel@13 {
771					reg = <13>;
772					label = "vrefint";
773				};
774				channel@14 {
775					reg = <14>;
776					label = "vddcore";
777				};
778				channel@16 {
779					reg = <16>;
780					label = "vddcpu";
781				};
782				channel@17 {
783					reg = <17>;
784					label = "vddq_ddr";
785				};
786			};
787		};
788
789		usbotg_hs: usb@49000000 {
790			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
791			reg = <0x49000000 0x40000>;
792			clocks = <&rcc USBO_K>;
793			clock-names = "otg";
794			resets = <&rcc USBO_R>;
795			reset-names = "dwc2";
796			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
797			g-rx-fifo-size = <512>;
798			g-np-tx-fifo-size = <32>;
799			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
800			dr_mode = "otg";
801			otg-rev = <0x200>;
802			usb33d-supply = <&usb33>;
803			status = "disabled";
804		};
805
806		usart1: serial@4c000000 {
807			compatible = "st,stm32h7-uart";
808			reg = <0x4c000000 0x400>;
809			interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
810			clocks = <&rcc USART1_K>;
811			resets = <&rcc USART1_R>;
812			wakeup-source;
813			dmas = <&dmamux1 41 0x400 0x5>,
814			       <&dmamux1 42 0x400 0x1>;
815			dma-names = "rx", "tx";
816			status = "disabled";
817		};
818
819		usart2: serial@4c001000 {
820			compatible = "st,stm32h7-uart";
821			reg = <0x4c001000 0x400>;
822			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
823			clocks = <&rcc USART2_K>;
824			resets = <&rcc USART2_R>;
825			wakeup-source;
826			dmas = <&dmamux1 43 0x400 0x5>,
827			       <&dmamux1 44 0x400 0x1>;
828			dma-names = "rx", "tx";
829			status = "disabled";
830		};
831
832		i2s4: audio-controller@4c002000 {
833			compatible = "st,stm32h7-i2s";
834			reg = <0x4c002000 0x400>;
835			#sound-dai-cells = <0>;
836			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
837			dmas = <&dmamux1 83 0x400 0x01>,
838			       <&dmamux1 84 0x400 0x01>;
839			dma-names = "rx", "tx";
840			status = "disabled";
841		};
842
843		spi4: spi@4c002000 {
844			compatible = "st,stm32h7-spi";
845			reg = <0x4c002000 0x400>;
846			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
847			clocks = <&rcc SPI4_K>;
848			resets = <&rcc SPI4_R>;
849			#address-cells = <1>;
850			#size-cells = <0>;
851			dmas = <&dmamux1 83 0x400 0x01>,
852			       <&dmamux1 84 0x400 0x01>;
853			dma-names = "rx", "tx";
854			status = "disabled";
855		};
856
857		spi5: spi@4c003000 {
858			compatible = "st,stm32h7-spi";
859			reg = <0x4c003000 0x400>;
860			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
861			clocks = <&rcc SPI5_K>;
862			resets = <&rcc SPI5_R>;
863			#address-cells = <1>;
864			#size-cells = <0>;
865			dmas = <&dmamux1 85 0x400 0x01>,
866			       <&dmamux1 86 0x400 0x01>;
867			dma-names = "rx", "tx";
868			status = "disabled";
869		};
870
871		i2c3: i2c@4c004000 {
872			compatible = "st,stm32mp13-i2c";
873			reg = <0x4c004000 0x400>;
874			interrupt-names = "event", "error";
875			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
876				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
877			clocks = <&rcc I2C3_K>;
878			resets = <&rcc I2C3_R>;
879			#address-cells = <1>;
880			#size-cells = <0>;
881			dmas = <&dmamux1 73 0x400 0x1>,
882			       <&dmamux1 74 0x400 0x1>;
883			dma-names = "rx", "tx";
884			st,syscfg-fmp = <&syscfg 0x4 0x4>;
885			i2c-analog-filter;
886			status = "disabled";
887		};
888
889		i2c4: i2c@4c005000 {
890			compatible = "st,stm32mp13-i2c";
891			reg = <0x4c005000 0x400>;
892			interrupt-names = "event", "error";
893			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
894				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
895			clocks = <&rcc I2C4_K>;
896			resets = <&rcc I2C4_R>;
897			#address-cells = <1>;
898			#size-cells = <0>;
899			dmas = <&dmamux1 75 0x400 0x1>,
900			       <&dmamux1 76 0x400 0x1>;
901			dma-names = "rx", "tx";
902			st,syscfg-fmp = <&syscfg 0x4 0x8>;
903			i2c-analog-filter;
904			status = "disabled";
905		};
906
907		i2c5: i2c@4c006000 {
908			compatible = "st,stm32mp13-i2c";
909			reg = <0x4c006000 0x400>;
910			interrupt-names = "event", "error";
911			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
912				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
913			clocks = <&rcc I2C5_K>;
914			resets = <&rcc I2C5_R>;
915			#address-cells = <1>;
916			#size-cells = <0>;
917			dmas = <&dmamux1 115 0x400 0x1>,
918			       <&dmamux1 116 0x400 0x1>;
919			dma-names = "rx", "tx";
920			st,syscfg-fmp = <&syscfg 0x4 0x10>;
921			i2c-analog-filter;
922			status = "disabled";
923		};
924
925		timers12: timer@4c007000 {
926			#address-cells = <1>;
927			#size-cells = <0>;
928			compatible = "st,stm32-timers";
929			reg = <0x4c007000 0x400>;
930			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
931			interrupt-names = "global";
932			clocks = <&rcc TIM12_K>;
933			clock-names = "int";
934			status = "disabled";
935
936			pwm {
937				compatible = "st,stm32-pwm";
938				#pwm-cells = <3>;
939				status = "disabled";
940			};
941
942			timer@11 {
943				compatible = "st,stm32h7-timer-trigger";
944				reg = <11>;
945				status = "disabled";
946			};
947		};
948
949		timers13: timer@4c008000 {
950			#address-cells = <1>;
951			#size-cells = <0>;
952			compatible = "st,stm32-timers";
953			reg = <0x4c008000 0x400>;
954			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
955			interrupt-names = "global";
956			clocks = <&rcc TIM13_K>;
957			clock-names = "int";
958			status = "disabled";
959
960			pwm {
961				compatible = "st,stm32-pwm";
962				#pwm-cells = <3>;
963				status = "disabled";
964			};
965
966			timer@12 {
967				compatible = "st,stm32h7-timer-trigger";
968				reg = <12>;
969				status = "disabled";
970			};
971		};
972
973		timers14: timer@4c009000 {
974			#address-cells = <1>;
975			#size-cells = <0>;
976			compatible = "st,stm32-timers";
977			reg = <0x4c009000 0x400>;
978			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
979			interrupt-names = "global";
980			clocks = <&rcc TIM14_K>;
981			clock-names = "int";
982			status = "disabled";
983
984			pwm {
985				compatible = "st,stm32-pwm";
986				#pwm-cells = <3>;
987				status = "disabled";
988			};
989
990			timer@13 {
991				compatible = "st,stm32h7-timer-trigger";
992				reg = <13>;
993				status = "disabled";
994			};
995		};
996
997		timers15: timer@4c00a000 {
998			#address-cells = <1>;
999			#size-cells = <0>;
1000			compatible = "st,stm32-timers";
1001			reg = <0x4c00a000 0x400>;
1002			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1003			interrupt-names = "global";
1004			clocks = <&rcc TIM15_K>;
1005			clock-names = "int";
1006			dmas = <&dmamux1 105 0x400 0x1>,
1007			       <&dmamux1 106 0x400 0x1>,
1008			       <&dmamux1 107 0x400 0x1>,
1009			       <&dmamux1 108 0x400 0x1>;
1010			dma-names = "ch1", "up", "trig", "com";
1011			status = "disabled";
1012
1013			pwm {
1014				compatible = "st,stm32-pwm";
1015				#pwm-cells = <3>;
1016				status = "disabled";
1017			};
1018
1019			timer@14 {
1020				compatible = "st,stm32h7-timer-trigger";
1021				reg = <14>;
1022				status = "disabled";
1023			};
1024		};
1025
1026		timers16: timer@4c00b000 {
1027			#address-cells = <1>;
1028			#size-cells = <0>;
1029			compatible = "st,stm32-timers";
1030			reg = <0x4c00b000 0x400>;
1031			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1032			interrupt-names = "global";
1033			clocks = <&rcc TIM16_K>;
1034			clock-names = "int";
1035			dmas = <&dmamux1 109 0x400 0x1>,
1036			       <&dmamux1 110 0x400 0x1>;
1037			dma-names = "ch1", "up";
1038			status = "disabled";
1039
1040			pwm {
1041				compatible = "st,stm32-pwm";
1042				#pwm-cells = <3>;
1043				status = "disabled";
1044			};
1045
1046			timer@15 {
1047				compatible = "st,stm32h7-timer-trigger";
1048				reg = <15>;
1049				status = "disabled";
1050			};
1051		};
1052
1053		timers17: timer@4c00c000 {
1054			#address-cells = <1>;
1055			#size-cells = <0>;
1056			compatible = "st,stm32-timers";
1057			reg = <0x4c00c000 0x400>;
1058			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1059			interrupt-names = "global";
1060			clocks = <&rcc TIM17_K>;
1061			clock-names = "int";
1062			dmas = <&dmamux1 111 0x400 0x1>,
1063			       <&dmamux1 112 0x400 0x1>;
1064			dma-names = "ch1", "up";
1065			status = "disabled";
1066
1067			pwm {
1068				compatible = "st,stm32-pwm";
1069				#pwm-cells = <3>;
1070				status = "disabled";
1071			};
1072
1073			timer@16 {
1074				compatible = "st,stm32h7-timer-trigger";
1075				reg = <16>;
1076				status = "disabled";
1077			};
1078		};
1079
1080		rcc: rcc@50000000 {
1081			compatible = "st,stm32mp13-rcc", "syscon";
1082			reg = <0x50000000 0x1000>;
1083			#clock-cells = <1>;
1084			#reset-cells = <1>;
1085			clock-names = "hse", "hsi", "csi", "lse", "lsi";
1086			clocks = <&scmi_clk CK_SCMI_HSE>,
1087				 <&scmi_clk CK_SCMI_HSI>,
1088				 <&scmi_clk CK_SCMI_CSI>,
1089				 <&scmi_clk CK_SCMI_LSE>,
1090				 <&scmi_clk CK_SCMI_LSI>;
1091		};
1092
1093		exti: interrupt-controller@5000d000 {
1094			compatible = "st,stm32mp13-exti", "syscon";
1095			interrupt-controller;
1096			#interrupt-cells = <2>;
1097			reg = <0x5000d000 0x400>;
1098		};
1099
1100		syscfg: syscon@50020000 {
1101			compatible = "st,stm32mp157-syscfg", "syscon";
1102			reg = <0x50020000 0x400>;
1103			clocks = <&rcc SYSCFG>;
1104		};
1105
1106		lptimer2: timer@50021000 {
1107			#address-cells = <1>;
1108			#size-cells = <0>;
1109			compatible = "st,stm32-lptimer";
1110			reg = <0x50021000 0x400>;
1111			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1112			clocks = <&rcc LPTIM2_K>;
1113			clock-names = "mux";
1114			wakeup-source;
1115			status = "disabled";
1116
1117			pwm {
1118				compatible = "st,stm32-pwm-lp";
1119				#pwm-cells = <3>;
1120				status = "disabled";
1121			};
1122
1123			trigger@1 {
1124				compatible = "st,stm32-lptimer-trigger";
1125				reg = <1>;
1126				status = "disabled";
1127			};
1128
1129			counter {
1130				compatible = "st,stm32-lptimer-counter";
1131				status = "disabled";
1132			};
1133
1134			timer {
1135				compatible = "st,stm32-lptimer-timer";
1136				status = "disabled";
1137			};
1138		};
1139
1140		lptimer3: timer@50022000 {
1141			#address-cells = <1>;
1142			#size-cells = <0>;
1143			compatible = "st,stm32-lptimer";
1144			reg = <0x50022000 0x400>;
1145			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1146			clocks = <&rcc LPTIM3_K>;
1147			clock-names = "mux";
1148			wakeup-source;
1149			status = "disabled";
1150
1151			pwm {
1152				compatible = "st,stm32-pwm-lp";
1153				#pwm-cells = <3>;
1154				status = "disabled";
1155			};
1156
1157			trigger@2 {
1158				compatible = "st,stm32-lptimer-trigger";
1159				reg = <2>;
1160				status = "disabled";
1161			};
1162
1163			timer {
1164				compatible = "st,stm32-lptimer-timer";
1165				status = "disabled";
1166			};
1167		};
1168
1169		lptimer4: timer@50023000 {
1170			compatible = "st,stm32-lptimer";
1171			reg = <0x50023000 0x400>;
1172			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1173			clocks = <&rcc LPTIM4_K>;
1174			clock-names = "mux";
1175			wakeup-source;
1176			status = "disabled";
1177
1178			pwm {
1179				compatible = "st,stm32-pwm-lp";
1180				#pwm-cells = <3>;
1181				status = "disabled";
1182			};
1183
1184			timer {
1185				compatible = "st,stm32-lptimer-timer";
1186				status = "disabled";
1187			};
1188		};
1189
1190		lptimer5: timer@50024000 {
1191			compatible = "st,stm32-lptimer";
1192			reg = <0x50024000 0x400>;
1193			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1194			clocks = <&rcc LPTIM5_K>;
1195			clock-names = "mux";
1196			wakeup-source;
1197			status = "disabled";
1198
1199			pwm {
1200				compatible = "st,stm32-pwm-lp";
1201				#pwm-cells = <3>;
1202				status = "disabled";
1203			};
1204
1205			timer {
1206				compatible = "st,stm32-lptimer-timer";
1207				status = "disabled";
1208			};
1209		};
1210
1211		mdma: dma-controller@58000000 {
1212			compatible = "st,stm32h7-mdma";
1213			reg = <0x58000000 0x1000>;
1214			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1215			clocks = <&rcc MDMA>;
1216			#dma-cells = <5>;
1217			dma-channels = <32>;
1218			dma-requests = <48>;
1219		};
1220
1221		fmc: memory-controller@58002000 {
1222			compatible = "st,stm32mp1-fmc2-ebi";
1223			reg = <0x58002000 0x1000>;
1224			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1225				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1226				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1227				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1228				 <4 0 0x80000000 0x10000000>; /* NAND */
1229			#address-cells = <2>;
1230			#size-cells = <1>;
1231			clocks = <&rcc FMC_K>;
1232			resets = <&rcc FMC_R>;
1233			status = "disabled";
1234
1235			nand-controller@4,0 {
1236				compatible = "st,stm32mp1-fmc2-nfc";
1237				reg = <4 0x00000000 0x1000>,
1238				      <4 0x08010000 0x1000>,
1239				      <4 0x08020000 0x1000>,
1240				      <4 0x01000000 0x1000>,
1241				      <4 0x09010000 0x1000>,
1242				      <4 0x09020000 0x1000>;
1243				#address-cells = <1>;
1244				#size-cells = <0>;
1245				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1246				dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
1247				       <&mdma 24 0x2 0x12000a08 0x0 0x0>,
1248				       <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
1249				dma-names = "tx", "rx", "ecc";
1250				status = "disabled";
1251			};
1252		};
1253
1254		qspi: spi@58003000 {
1255			compatible = "st,stm32f469-qspi";
1256			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1257			reg-names = "qspi", "qspi_mm";
1258			#address-cells = <1>;
1259			#size-cells = <0>;
1260			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1261			dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
1262			       <&mdma 26 0x2 0x10100008 0x0 0x0>;
1263			dma-names = "tx", "rx";
1264			clocks = <&rcc QSPI_K>;
1265			resets = <&rcc QSPI_R>;
1266			status = "disabled";
1267		};
1268
1269		sdmmc1: mmc@58005000 {
1270			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1271			arm,primecell-periphid = <0x20253180>;
1272			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
1273			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1274			clocks = <&rcc SDMMC1_K>;
1275			clock-names = "apb_pclk";
1276			resets = <&rcc SDMMC1_R>;
1277			cap-sd-highspeed;
1278			cap-mmc-highspeed;
1279			max-frequency = <130000000>;
1280			status = "disabled";
1281		};
1282
1283		sdmmc2: mmc@58007000 {
1284			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1285			arm,primecell-periphid = <0x20253180>;
1286			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
1287			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1288			clocks = <&rcc SDMMC2_K>;
1289			clock-names = "apb_pclk";
1290			resets = <&rcc SDMMC2_R>;
1291			cap-sd-highspeed;
1292			cap-mmc-highspeed;
1293			max-frequency = <130000000>;
1294			status = "disabled";
1295		};
1296
1297		usbh_ohci: usb@5800c000 {
1298			compatible = "generic-ohci";
1299			reg = <0x5800c000 0x1000>;
1300			clocks = <&usbphyc>, <&rcc USBH>;
1301			resets = <&rcc USBH_R>;
1302			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1303			status = "disabled";
1304		};
1305
1306		usbh_ehci: usb@5800d000 {
1307			compatible = "generic-ehci";
1308			reg = <0x5800d000 0x1000>;
1309			clocks = <&usbphyc>, <&rcc USBH>;
1310			resets = <&rcc USBH_R>;
1311			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1312			companion = <&usbh_ohci>;
1313			status = "disabled";
1314		};
1315
1316		iwdg2: watchdog@5a002000 {
1317			compatible = "st,stm32mp1-iwdg";
1318			reg = <0x5a002000 0x400>;
1319			clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
1320			clock-names = "pclk", "lsi";
1321			status = "disabled";
1322		};
1323
1324		usbphyc: usbphyc@5a006000 {
1325			#address-cells = <1>;
1326			#size-cells = <0>;
1327			#clock-cells = <0>;
1328			compatible = "st,stm32mp1-usbphyc";
1329			reg = <0x5a006000 0x1000>;
1330			clocks = <&rcc USBPHY_K>;
1331			resets = <&rcc USBPHY_R>;
1332			vdda1v1-supply = <&reg11>;
1333			vdda1v8-supply = <&reg18>;
1334			status = "disabled";
1335
1336			usbphyc_port0: usb-phy@0 {
1337				#phy-cells = <0>;
1338				reg = <0>;
1339			};
1340
1341			usbphyc_port1: usb-phy@1 {
1342				#phy-cells = <1>;
1343				reg = <1>;
1344			};
1345		};
1346
1347		rtc: rtc@5c004000 {
1348			compatible = "st,stm32mp1-rtc";
1349			reg = <0x5c004000 0x400>;
1350			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1351			clocks = <&scmi_clk CK_SCMI_RTCAPB>,
1352				 <&scmi_clk CK_SCMI_RTC>;
1353			clock-names = "pclk", "rtc_ck";
1354			status = "disabled";
1355		};
1356
1357		bsec: efuse@5c005000 {
1358			compatible = "st,stm32mp13-bsec";
1359			reg = <0x5c005000 0x400>;
1360			#address-cells = <1>;
1361			#size-cells = <1>;
1362
1363			part_number_otp: part_number_otp@4 {
1364				reg = <0x4 0x2>;
1365				bits = <0 12>;
1366			};
1367			ts_cal1: calib@5c {
1368				reg = <0x5c 0x2>;
1369			};
1370			ts_cal2: calib@5e {
1371				reg = <0x5e 0x2>;
1372			};
1373		};
1374
1375		/*
1376		 * Break node order to solve dependency probe issue between
1377		 * pinctrl and exti.
1378		 */
1379		pinctrl: pinctrl@50002000 {
1380			#address-cells = <1>;
1381			#size-cells = <1>;
1382			compatible = "st,stm32mp135-pinctrl";
1383			ranges = <0 0x50002000 0x8400>;
1384			interrupt-parent = <&exti>;
1385			st,syscfg = <&exti 0x60 0xff>;
1386
1387			gpioa: gpio@50002000 {
1388				gpio-controller;
1389				#gpio-cells = <2>;
1390				interrupt-controller;
1391				#interrupt-cells = <2>;
1392				reg = <0x0 0x400>;
1393				clocks = <&rcc GPIOA>;
1394				st,bank-name = "GPIOA";
1395				ngpios = <16>;
1396				gpio-ranges = <&pinctrl 0 0 16>;
1397			};
1398
1399			gpiob: gpio@50003000 {
1400				gpio-controller;
1401				#gpio-cells = <2>;
1402				interrupt-controller;
1403				#interrupt-cells = <2>;
1404				reg = <0x1000 0x400>;
1405				clocks = <&rcc GPIOB>;
1406				st,bank-name = "GPIOB";
1407				ngpios = <16>;
1408				gpio-ranges = <&pinctrl 0 16 16>;
1409			};
1410
1411			gpioc: gpio@50004000 {
1412				gpio-controller;
1413				#gpio-cells = <2>;
1414				interrupt-controller;
1415				#interrupt-cells = <2>;
1416				reg = <0x2000 0x400>;
1417				clocks = <&rcc GPIOC>;
1418				st,bank-name = "GPIOC";
1419				ngpios = <16>;
1420				gpio-ranges = <&pinctrl 0 32 16>;
1421			};
1422
1423			gpiod: gpio@50005000 {
1424				gpio-controller;
1425				#gpio-cells = <2>;
1426				interrupt-controller;
1427				#interrupt-cells = <2>;
1428				reg = <0x3000 0x400>;
1429				clocks = <&rcc GPIOD>;
1430				st,bank-name = "GPIOD";
1431				ngpios = <16>;
1432				gpio-ranges = <&pinctrl 0 48 16>;
1433			};
1434
1435			gpioe: gpio@50006000 {
1436				gpio-controller;
1437				#gpio-cells = <2>;
1438				interrupt-controller;
1439				#interrupt-cells = <2>;
1440				reg = <0x4000 0x400>;
1441				clocks = <&rcc GPIOE>;
1442				st,bank-name = "GPIOE";
1443				ngpios = <16>;
1444				gpio-ranges = <&pinctrl 0 64 16>;
1445			};
1446
1447			gpiof: gpio@50007000 {
1448				gpio-controller;
1449				#gpio-cells = <2>;
1450				interrupt-controller;
1451				#interrupt-cells = <2>;
1452				reg = <0x5000 0x400>;
1453				clocks = <&rcc GPIOF>;
1454				st,bank-name = "GPIOF";
1455				ngpios = <16>;
1456				gpio-ranges = <&pinctrl 0 80 16>;
1457			};
1458
1459			gpiog: gpio@50008000 {
1460				gpio-controller;
1461				#gpio-cells = <2>;
1462				interrupt-controller;
1463				#interrupt-cells = <2>;
1464				reg = <0x6000 0x400>;
1465				clocks = <&rcc GPIOG>;
1466				st,bank-name = "GPIOG";
1467				ngpios = <16>;
1468				gpio-ranges = <&pinctrl 0 96 16>;
1469			};
1470
1471			gpioh: gpio@50009000 {
1472				gpio-controller;
1473				#gpio-cells = <2>;
1474				interrupt-controller;
1475				#interrupt-cells = <2>;
1476				reg = <0x7000 0x400>;
1477				clocks = <&rcc GPIOH>;
1478				st,bank-name = "GPIOH";
1479				ngpios = <15>;
1480				gpio-ranges = <&pinctrl 0 112 15>;
1481			};
1482
1483			gpioi: gpio@5000a000 {
1484				gpio-controller;
1485				#gpio-cells = <2>;
1486				interrupt-controller;
1487				#interrupt-cells = <2>;
1488				reg = <0x8000 0x400>;
1489				clocks = <&rcc GPIOI>;
1490				st,bank-name = "GPIOI";
1491				ngpios = <8>;
1492				gpio-ranges = <&pinctrl 0 128 8>;
1493			};
1494		};
1495	};
1496};
1497