1724ba675SRob Herring/* 2724ba675SRob Herring * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3724ba675SRob Herring * 4724ba675SRob Herring * This file is dual-licensed: you can use it either under the terms 5724ba675SRob Herring * of the GPL or the X11 license, at your option. Note that this dual 6724ba675SRob Herring * licensing only applies to this file, and not this project as a 7724ba675SRob Herring * whole. 8724ba675SRob Herring * 9724ba675SRob Herring * a) This file is free software; you can redistribute it and/or 10724ba675SRob Herring * modify it under the terms of the GNU General Public License as 11724ba675SRob Herring * published by the Free Software Foundation; either version 2 of the 12724ba675SRob Herring * License, or (at your option) any later version. 13724ba675SRob Herring * 14724ba675SRob Herring * This file is distributed in the hope that it will be useful, 15724ba675SRob Herring * but WITHOUT ANY WARRANTY; without even the implied warranty of 16724ba675SRob Herring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17724ba675SRob Herring * GNU General Public License for more details. 18724ba675SRob Herring * 19724ba675SRob Herring * Or, alternatively, 20724ba675SRob Herring * 21724ba675SRob Herring * b) Permission is hereby granted, free of charge, to any person 22724ba675SRob Herring * obtaining a copy of this software and associated documentation 23724ba675SRob Herring * files (the "Software"), to deal in the Software without 24724ba675SRob Herring * restriction, including without limitation the rights to use, 25724ba675SRob Herring * copy, modify, merge, publish, distribute, sublicense, and/or 26724ba675SRob Herring * sell copies of the Software, and to permit persons to whom the 27724ba675SRob Herring * Software is furnished to do so, subject to the following 28724ba675SRob Herring * conditions: 29724ba675SRob Herring * 30724ba675SRob Herring * The above copyright notice and this permission notice shall be 31724ba675SRob Herring * included in all copies or substantial portions of the Software. 32724ba675SRob Herring * 33724ba675SRob Herring * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34724ba675SRob Herring * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35724ba675SRob Herring * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36724ba675SRob Herring * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37724ba675SRob Herring * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38724ba675SRob Herring * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39724ba675SRob Herring * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40724ba675SRob Herring * OTHER DEALINGS IN THE SOFTWARE. 41724ba675SRob Herring */ 42724ba675SRob Herring 43724ba675SRob Herring#include "../armv7-m.dtsi" 44724ba675SRob Herring#include <dt-bindings/clock/stm32fx-clock.h> 45724ba675SRob Herring#include <dt-bindings/mfd/stm32f7-rcc.h> 46724ba675SRob Herring 47724ba675SRob Herring/ { 48724ba675SRob Herring #address-cells = <1>; 49724ba675SRob Herring #size-cells = <1>; 50724ba675SRob Herring 51724ba675SRob Herring clocks { 52724ba675SRob Herring clk_hse: clk-hse { 53724ba675SRob Herring #clock-cells = <0>; 54724ba675SRob Herring compatible = "fixed-clock"; 55724ba675SRob Herring clock-frequency = <0>; 56724ba675SRob Herring }; 57724ba675SRob Herring 58724ba675SRob Herring clk-lse { 59724ba675SRob Herring #clock-cells = <0>; 60724ba675SRob Herring compatible = "fixed-clock"; 61724ba675SRob Herring clock-frequency = <32768>; 62724ba675SRob Herring }; 63724ba675SRob Herring 64724ba675SRob Herring clk-lsi { 65724ba675SRob Herring #clock-cells = <0>; 66724ba675SRob Herring compatible = "fixed-clock"; 67724ba675SRob Herring clock-frequency = <32000>; 68724ba675SRob Herring }; 69724ba675SRob Herring 70724ba675SRob Herring clk_i2s_ckin: clk-i2s-ckin { 71724ba675SRob Herring #clock-cells = <0>; 72724ba675SRob Herring compatible = "fixed-clock"; 73724ba675SRob Herring clock-frequency = <48000000>; 74724ba675SRob Herring }; 75724ba675SRob Herring }; 76724ba675SRob Herring 77724ba675SRob Herring soc { 78724ba675SRob Herring timers2: timers@40000000 { 79724ba675SRob Herring #address-cells = <1>; 80724ba675SRob Herring #size-cells = <0>; 81724ba675SRob Herring compatible = "st,stm32-timers"; 82724ba675SRob Herring reg = <0x40000000 0x400>; 83724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 84724ba675SRob Herring clock-names = "int"; 85724ba675SRob Herring status = "disabled"; 86724ba675SRob Herring 87724ba675SRob Herring pwm { 88724ba675SRob Herring compatible = "st,stm32-pwm"; 89724ba675SRob Herring #pwm-cells = <3>; 90724ba675SRob Herring status = "disabled"; 91724ba675SRob Herring }; 92724ba675SRob Herring 93724ba675SRob Herring timer@1 { 94724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 95724ba675SRob Herring reg = <1>; 96724ba675SRob Herring status = "disabled"; 97724ba675SRob Herring }; 98724ba675SRob Herring }; 99724ba675SRob Herring 100724ba675SRob Herring timers3: timers@40000400 { 101724ba675SRob Herring #address-cells = <1>; 102724ba675SRob Herring #size-cells = <0>; 103724ba675SRob Herring compatible = "st,stm32-timers"; 104724ba675SRob Herring reg = <0x40000400 0x400>; 105724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 106724ba675SRob Herring clock-names = "int"; 107724ba675SRob Herring status = "disabled"; 108724ba675SRob Herring 109724ba675SRob Herring pwm { 110724ba675SRob Herring compatible = "st,stm32-pwm"; 111724ba675SRob Herring #pwm-cells = <3>; 112724ba675SRob Herring status = "disabled"; 113724ba675SRob Herring }; 114724ba675SRob Herring 115724ba675SRob Herring timer@2 { 116724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 117724ba675SRob Herring reg = <2>; 118724ba675SRob Herring status = "disabled"; 119724ba675SRob Herring }; 120724ba675SRob Herring }; 121724ba675SRob Herring 122724ba675SRob Herring timers4: timers@40000800 { 123724ba675SRob Herring #address-cells = <1>; 124724ba675SRob Herring #size-cells = <0>; 125724ba675SRob Herring compatible = "st,stm32-timers"; 126724ba675SRob Herring reg = <0x40000800 0x400>; 127724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 128724ba675SRob Herring clock-names = "int"; 129724ba675SRob Herring status = "disabled"; 130724ba675SRob Herring 131724ba675SRob Herring pwm { 132724ba675SRob Herring compatible = "st,stm32-pwm"; 133724ba675SRob Herring #pwm-cells = <3>; 134724ba675SRob Herring status = "disabled"; 135724ba675SRob Herring }; 136724ba675SRob Herring 137724ba675SRob Herring timer@3 { 138724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 139724ba675SRob Herring reg = <3>; 140724ba675SRob Herring status = "disabled"; 141724ba675SRob Herring }; 142724ba675SRob Herring }; 143724ba675SRob Herring 144724ba675SRob Herring timers5: timers@40000c00 { 145724ba675SRob Herring #address-cells = <1>; 146724ba675SRob Herring #size-cells = <0>; 147724ba675SRob Herring compatible = "st,stm32-timers"; 148724ba675SRob Herring reg = <0x40000C00 0x400>; 149724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 150724ba675SRob Herring clock-names = "int"; 151724ba675SRob Herring status = "disabled"; 152724ba675SRob Herring 153724ba675SRob Herring pwm { 154724ba675SRob Herring compatible = "st,stm32-pwm"; 155724ba675SRob Herring #pwm-cells = <3>; 156724ba675SRob Herring status = "disabled"; 157724ba675SRob Herring }; 158724ba675SRob Herring 159724ba675SRob Herring timer@4 { 160724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 161724ba675SRob Herring reg = <4>; 162724ba675SRob Herring status = "disabled"; 163724ba675SRob Herring }; 164724ba675SRob Herring }; 165724ba675SRob Herring 166724ba675SRob Herring timers6: timers@40001000 { 167724ba675SRob Herring #address-cells = <1>; 168724ba675SRob Herring #size-cells = <0>; 169724ba675SRob Herring compatible = "st,stm32-timers"; 170724ba675SRob Herring reg = <0x40001000 0x400>; 171724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 172724ba675SRob Herring clock-names = "int"; 173724ba675SRob Herring status = "disabled"; 174724ba675SRob Herring 175724ba675SRob Herring timer@5 { 176724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 177724ba675SRob Herring reg = <5>; 178724ba675SRob Herring status = "disabled"; 179724ba675SRob Herring }; 180724ba675SRob Herring }; 181724ba675SRob Herring 182724ba675SRob Herring timers7: timers@40001400 { 183724ba675SRob Herring #address-cells = <1>; 184724ba675SRob Herring #size-cells = <0>; 185724ba675SRob Herring compatible = "st,stm32-timers"; 186724ba675SRob Herring reg = <0x40001400 0x400>; 187724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 188724ba675SRob Herring clock-names = "int"; 189724ba675SRob Herring status = "disabled"; 190724ba675SRob Herring 191724ba675SRob Herring timer@6 { 192724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 193724ba675SRob Herring reg = <6>; 194724ba675SRob Herring status = "disabled"; 195724ba675SRob Herring }; 196724ba675SRob Herring }; 197724ba675SRob Herring 198724ba675SRob Herring timers12: timers@40001800 { 199724ba675SRob Herring #address-cells = <1>; 200724ba675SRob Herring #size-cells = <0>; 201724ba675SRob Herring compatible = "st,stm32-timers"; 202724ba675SRob Herring reg = <0x40001800 0x400>; 203724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; 204724ba675SRob Herring clock-names = "int"; 205724ba675SRob Herring status = "disabled"; 206724ba675SRob Herring 207724ba675SRob Herring pwm { 208724ba675SRob Herring compatible = "st,stm32-pwm"; 209724ba675SRob Herring #pwm-cells = <3>; 210724ba675SRob Herring status = "disabled"; 211724ba675SRob Herring }; 212724ba675SRob Herring 213724ba675SRob Herring timer@11 { 214724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 215724ba675SRob Herring reg = <11>; 216724ba675SRob Herring status = "disabled"; 217724ba675SRob Herring }; 218724ba675SRob Herring }; 219724ba675SRob Herring 220724ba675SRob Herring timers13: timers@40001c00 { 221724ba675SRob Herring compatible = "st,stm32-timers"; 222724ba675SRob Herring reg = <0x40001C00 0x400>; 223724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; 224724ba675SRob Herring clock-names = "int"; 225724ba675SRob Herring status = "disabled"; 226724ba675SRob Herring 227724ba675SRob Herring pwm { 228724ba675SRob Herring compatible = "st,stm32-pwm"; 229724ba675SRob Herring #pwm-cells = <3>; 230724ba675SRob Herring status = "disabled"; 231724ba675SRob Herring }; 232724ba675SRob Herring }; 233724ba675SRob Herring 234724ba675SRob Herring timers14: timers@40002000 { 235724ba675SRob Herring compatible = "st,stm32-timers"; 236724ba675SRob Herring reg = <0x40002000 0x400>; 237724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; 238724ba675SRob Herring clock-names = "int"; 239724ba675SRob Herring status = "disabled"; 240724ba675SRob Herring 241724ba675SRob Herring pwm { 242724ba675SRob Herring compatible = "st,stm32-pwm"; 243724ba675SRob Herring #pwm-cells = <3>; 244724ba675SRob Herring status = "disabled"; 245724ba675SRob Herring }; 246724ba675SRob Herring }; 247724ba675SRob Herring 248724ba675SRob Herring rtc: rtc@40002800 { 249724ba675SRob Herring compatible = "st,stm32-rtc"; 250724ba675SRob Herring reg = <0x40002800 0x400>; 251724ba675SRob Herring clocks = <&rcc 1 CLK_RTC>; 252724ba675SRob Herring assigned-clocks = <&rcc 1 CLK_RTC>; 253724ba675SRob Herring assigned-clock-parents = <&rcc 1 CLK_LSE>; 254724ba675SRob Herring interrupt-parent = <&exti>; 255724ba675SRob Herring interrupts = <17 1>; 256724ba675SRob Herring st,syscfg = <&pwrcfg 0x00 0x100>; 257724ba675SRob Herring status = "disabled"; 258724ba675SRob Herring }; 259724ba675SRob Herring 260df362914SDario Binacchi can3: can@40003400 { 261df362914SDario Binacchi compatible = "st,stm32f4-bxcan"; 262df362914SDario Binacchi reg = <0x40003400 0x200>; 263df362914SDario Binacchi interrupts = <104>, <105>, <106>, <107>; 264df362914SDario Binacchi interrupt-names = "tx", "rx0", "rx1", "sce"; 265df362914SDario Binacchi resets = <&rcc STM32F7_APB1_RESET(CAN3)>; 266df362914SDario Binacchi clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; 267df362914SDario Binacchi st,gcan = <&gcan3>; 268df362914SDario Binacchi status = "disabled"; 269df362914SDario Binacchi }; 270df362914SDario Binacchi 271df362914SDario Binacchi gcan3: gcan@40003600 { 272df362914SDario Binacchi compatible = "st,stm32f4-gcan", "syscon"; 273df362914SDario Binacchi reg = <0x40003600 0x200>; 274df362914SDario Binacchi clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; 275df362914SDario Binacchi }; 276df362914SDario Binacchi 277724ba675SRob Herring usart2: serial@40004400 { 278724ba675SRob Herring compatible = "st,stm32f7-uart"; 279724ba675SRob Herring reg = <0x40004400 0x400>; 280724ba675SRob Herring interrupts = <38>; 281724ba675SRob Herring clocks = <&rcc 1 CLK_USART2>; 282724ba675SRob Herring status = "disabled"; 283724ba675SRob Herring }; 284724ba675SRob Herring 285724ba675SRob Herring usart3: serial@40004800 { 286724ba675SRob Herring compatible = "st,stm32f7-uart"; 287724ba675SRob Herring reg = <0x40004800 0x400>; 288724ba675SRob Herring interrupts = <39>; 289724ba675SRob Herring clocks = <&rcc 1 CLK_USART3>; 290724ba675SRob Herring status = "disabled"; 291724ba675SRob Herring }; 292724ba675SRob Herring 293724ba675SRob Herring usart4: serial@40004c00 { 294724ba675SRob Herring compatible = "st,stm32f7-uart"; 295724ba675SRob Herring reg = <0x40004c00 0x400>; 296724ba675SRob Herring interrupts = <52>; 297724ba675SRob Herring clocks = <&rcc 1 CLK_UART4>; 298724ba675SRob Herring status = "disabled"; 299724ba675SRob Herring }; 300724ba675SRob Herring 301724ba675SRob Herring usart5: serial@40005000 { 302724ba675SRob Herring compatible = "st,stm32f7-uart"; 303724ba675SRob Herring reg = <0x40005000 0x400>; 304724ba675SRob Herring interrupts = <53>; 305724ba675SRob Herring clocks = <&rcc 1 CLK_UART5>; 306724ba675SRob Herring status = "disabled"; 307724ba675SRob Herring }; 308724ba675SRob Herring 309724ba675SRob Herring i2c1: i2c@40005400 { 310724ba675SRob Herring compatible = "st,stm32f7-i2c"; 311724ba675SRob Herring reg = <0x40005400 0x400>; 312724ba675SRob Herring interrupts = <31>, 313724ba675SRob Herring <32>; 314724ba675SRob Herring resets = <&rcc STM32F7_APB1_RESET(I2C1)>; 315724ba675SRob Herring clocks = <&rcc 1 CLK_I2C1>; 316724ba675SRob Herring #address-cells = <1>; 317724ba675SRob Herring #size-cells = <0>; 318724ba675SRob Herring status = "disabled"; 319724ba675SRob Herring }; 320724ba675SRob Herring 321724ba675SRob Herring i2c2: i2c@40005800 { 322724ba675SRob Herring compatible = "st,stm32f7-i2c"; 323724ba675SRob Herring reg = <0x40005800 0x400>; 324724ba675SRob Herring interrupts = <33>, 325724ba675SRob Herring <34>; 326724ba675SRob Herring resets = <&rcc STM32F7_APB1_RESET(I2C2)>; 327724ba675SRob Herring clocks = <&rcc 1 CLK_I2C2>; 328724ba675SRob Herring #address-cells = <1>; 329724ba675SRob Herring #size-cells = <0>; 330724ba675SRob Herring status = "disabled"; 331724ba675SRob Herring }; 332724ba675SRob Herring 333724ba675SRob Herring i2c3: i2c@40005c00 { 334724ba675SRob Herring compatible = "st,stm32f7-i2c"; 335724ba675SRob Herring reg = <0x40005c00 0x400>; 336724ba675SRob Herring interrupts = <72>, 337724ba675SRob Herring <73>; 338724ba675SRob Herring resets = <&rcc STM32F7_APB1_RESET(I2C3)>; 339724ba675SRob Herring clocks = <&rcc 1 CLK_I2C3>; 340724ba675SRob Herring #address-cells = <1>; 341724ba675SRob Herring #size-cells = <0>; 342724ba675SRob Herring status = "disabled"; 343724ba675SRob Herring }; 344724ba675SRob Herring 345724ba675SRob Herring i2c4: i2c@40006000 { 346724ba675SRob Herring compatible = "st,stm32f7-i2c"; 347724ba675SRob Herring reg = <0x40006000 0x400>; 348724ba675SRob Herring interrupts = <95>, 349724ba675SRob Herring <96>; 350724ba675SRob Herring resets = <&rcc STM32F7_APB1_RESET(I2C4)>; 351724ba675SRob Herring clocks = <&rcc 1 CLK_I2C4>; 352724ba675SRob Herring #address-cells = <1>; 353724ba675SRob Herring #size-cells = <0>; 354724ba675SRob Herring status = "disabled"; 355724ba675SRob Herring }; 356724ba675SRob Herring 357df362914SDario Binacchi can1: can@40006400 { 358df362914SDario Binacchi compatible = "st,stm32f4-bxcan"; 359df362914SDario Binacchi reg = <0x40006400 0x200>; 360df362914SDario Binacchi interrupts = <19>, <20>, <21>, <22>; 361df362914SDario Binacchi interrupt-names = "tx", "rx0", "rx1", "sce"; 362df362914SDario Binacchi resets = <&rcc STM32F7_APB1_RESET(CAN1)>; 363df362914SDario Binacchi clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; 364df362914SDario Binacchi st,can-primary; 365df362914SDario Binacchi st,gcan = <&gcan1>; 366df362914SDario Binacchi status = "disabled"; 367df362914SDario Binacchi }; 368df362914SDario Binacchi 369df362914SDario Binacchi gcan1: gcan@40006600 { 370df362914SDario Binacchi compatible = "st,stm32f4-gcan", "syscon"; 371df362914SDario Binacchi reg = <0x40006600 0x200>; 372df362914SDario Binacchi clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; 373df362914SDario Binacchi }; 374df362914SDario Binacchi 375df362914SDario Binacchi can2: can@40006800 { 376df362914SDario Binacchi compatible = "st,stm32f4-bxcan"; 377df362914SDario Binacchi reg = <0x40006800 0x200>; 378df362914SDario Binacchi interrupts = <63>, <64>, <65>, <66>; 379df362914SDario Binacchi interrupt-names = "tx", "rx0", "rx1", "sce"; 380df362914SDario Binacchi resets = <&rcc STM32F7_APB1_RESET(CAN2)>; 381df362914SDario Binacchi clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; 382df362914SDario Binacchi st,can-secondary; 383df362914SDario Binacchi st,gcan = <&gcan1>; 384df362914SDario Binacchi status = "disabled"; 385df362914SDario Binacchi }; 386df362914SDario Binacchi 387724ba675SRob Herring cec: cec@40006c00 { 388724ba675SRob Herring compatible = "st,stm32-cec"; 389724ba675SRob Herring reg = <0x40006C00 0x400>; 390724ba675SRob Herring interrupts = <94>; 391724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; 392724ba675SRob Herring clock-names = "cec", "hdmi-cec"; 393724ba675SRob Herring status = "disabled"; 394724ba675SRob Herring }; 395724ba675SRob Herring 396724ba675SRob Herring usart7: serial@40007800 { 397724ba675SRob Herring compatible = "st,stm32f7-uart"; 398724ba675SRob Herring reg = <0x40007800 0x400>; 399724ba675SRob Herring interrupts = <82>; 400724ba675SRob Herring clocks = <&rcc 1 CLK_UART7>; 401724ba675SRob Herring status = "disabled"; 402724ba675SRob Herring }; 403724ba675SRob Herring 404724ba675SRob Herring usart8: serial@40007c00 { 405724ba675SRob Herring compatible = "st,stm32f7-uart"; 406724ba675SRob Herring reg = <0x40007c00 0x400>; 407724ba675SRob Herring interrupts = <83>; 408724ba675SRob Herring clocks = <&rcc 1 CLK_UART8>; 409724ba675SRob Herring status = "disabled"; 410724ba675SRob Herring }; 411724ba675SRob Herring 412724ba675SRob Herring timers1: timers@40010000 { 413724ba675SRob Herring #address-cells = <1>; 414724ba675SRob Herring #size-cells = <0>; 415724ba675SRob Herring compatible = "st,stm32-timers"; 416724ba675SRob Herring reg = <0x40010000 0x400>; 417724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; 418724ba675SRob Herring clock-names = "int"; 419724ba675SRob Herring status = "disabled"; 420724ba675SRob Herring 421724ba675SRob Herring pwm { 422724ba675SRob Herring compatible = "st,stm32-pwm"; 423724ba675SRob Herring #pwm-cells = <3>; 424724ba675SRob Herring status = "disabled"; 425724ba675SRob Herring }; 426724ba675SRob Herring 427724ba675SRob Herring timer@0 { 428724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 429724ba675SRob Herring reg = <0>; 430724ba675SRob Herring status = "disabled"; 431724ba675SRob Herring }; 432724ba675SRob Herring }; 433724ba675SRob Herring 434724ba675SRob Herring timers8: timers@40010400 { 435724ba675SRob Herring #address-cells = <1>; 436724ba675SRob Herring #size-cells = <0>; 437724ba675SRob Herring compatible = "st,stm32-timers"; 438724ba675SRob Herring reg = <0x40010400 0x400>; 439724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; 440724ba675SRob Herring clock-names = "int"; 441724ba675SRob Herring status = "disabled"; 442724ba675SRob Herring 443724ba675SRob Herring pwm { 444724ba675SRob Herring compatible = "st,stm32-pwm"; 445724ba675SRob Herring #pwm-cells = <3>; 446724ba675SRob Herring status = "disabled"; 447724ba675SRob Herring }; 448724ba675SRob Herring 449724ba675SRob Herring timer@7 { 450724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 451724ba675SRob Herring reg = <7>; 452724ba675SRob Herring status = "disabled"; 453724ba675SRob Herring }; 454724ba675SRob Herring }; 455724ba675SRob Herring 456724ba675SRob Herring usart1: serial@40011000 { 457724ba675SRob Herring compatible = "st,stm32f7-uart"; 458724ba675SRob Herring reg = <0x40011000 0x400>; 459724ba675SRob Herring interrupts = <37>; 460724ba675SRob Herring clocks = <&rcc 1 CLK_USART1>; 461724ba675SRob Herring status = "disabled"; 462724ba675SRob Herring }; 463724ba675SRob Herring 464724ba675SRob Herring usart6: serial@40011400 { 465724ba675SRob Herring compatible = "st,stm32f7-uart"; 466724ba675SRob Herring reg = <0x40011400 0x400>; 467724ba675SRob Herring interrupts = <71>; 468724ba675SRob Herring clocks = <&rcc 1 CLK_USART6>; 469724ba675SRob Herring status = "disabled"; 470724ba675SRob Herring }; 471724ba675SRob Herring 472724ba675SRob Herring sdio2: mmc@40011c00 { 473724ba675SRob Herring compatible = "arm,pl180", "arm,primecell"; 474724ba675SRob Herring arm,primecell-periphid = <0x00880180>; 475724ba675SRob Herring reg = <0x40011c00 0x400>; 476724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; 477724ba675SRob Herring clock-names = "apb_pclk"; 478724ba675SRob Herring interrupts = <103>; 479724ba675SRob Herring max-frequency = <48000000>; 480724ba675SRob Herring status = "disabled"; 481724ba675SRob Herring }; 482724ba675SRob Herring 483724ba675SRob Herring sdio1: mmc@40012c00 { 484724ba675SRob Herring compatible = "arm,pl180", "arm,primecell"; 485724ba675SRob Herring arm,primecell-periphid = <0x00880180>; 486724ba675SRob Herring reg = <0x40012c00 0x400>; 487724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; 488724ba675SRob Herring clock-names = "apb_pclk"; 489724ba675SRob Herring interrupts = <49>; 490724ba675SRob Herring max-frequency = <48000000>; 491724ba675SRob Herring status = "disabled"; 492724ba675SRob Herring }; 493724ba675SRob Herring 494724ba675SRob Herring syscfg: syscon@40013800 { 495724ba675SRob Herring compatible = "st,stm32-syscfg", "syscon"; 496724ba675SRob Herring reg = <0x40013800 0x400>; 497724ba675SRob Herring }; 498724ba675SRob Herring 499724ba675SRob Herring exti: interrupt-controller@40013c00 { 500724ba675SRob Herring compatible = "st,stm32-exti"; 501724ba675SRob Herring interrupt-controller; 502724ba675SRob Herring #interrupt-cells = <2>; 503724ba675SRob Herring reg = <0x40013C00 0x400>; 504724ba675SRob Herring interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 505724ba675SRob Herring }; 506724ba675SRob Herring 507724ba675SRob Herring timers9: timers@40014000 { 508724ba675SRob Herring #address-cells = <1>; 509724ba675SRob Herring #size-cells = <0>; 510724ba675SRob Herring compatible = "st,stm32-timers"; 511724ba675SRob Herring reg = <0x40014000 0x400>; 512724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; 513724ba675SRob Herring clock-names = "int"; 514724ba675SRob Herring status = "disabled"; 515724ba675SRob Herring 516724ba675SRob Herring pwm { 517724ba675SRob Herring compatible = "st,stm32-pwm"; 518724ba675SRob Herring #pwm-cells = <3>; 519724ba675SRob Herring status = "disabled"; 520724ba675SRob Herring }; 521724ba675SRob Herring 522724ba675SRob Herring timer@8 { 523724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 524724ba675SRob Herring reg = <8>; 525724ba675SRob Herring status = "disabled"; 526724ba675SRob Herring }; 527724ba675SRob Herring }; 528724ba675SRob Herring 529724ba675SRob Herring timers10: timers@40014400 { 530724ba675SRob Herring compatible = "st,stm32-timers"; 531724ba675SRob Herring reg = <0x40014400 0x400>; 532724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; 533724ba675SRob Herring clock-names = "int"; 534724ba675SRob Herring status = "disabled"; 535724ba675SRob Herring 536724ba675SRob Herring pwm { 537724ba675SRob Herring compatible = "st,stm32-pwm"; 538724ba675SRob Herring #pwm-cells = <3>; 539724ba675SRob Herring status = "disabled"; 540724ba675SRob Herring }; 541724ba675SRob Herring }; 542724ba675SRob Herring 543724ba675SRob Herring timers11: timers@40014800 { 544724ba675SRob Herring compatible = "st,stm32-timers"; 545724ba675SRob Herring reg = <0x40014800 0x400>; 546724ba675SRob Herring clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; 547724ba675SRob Herring clock-names = "int"; 548724ba675SRob Herring status = "disabled"; 549724ba675SRob Herring 550724ba675SRob Herring pwm { 551724ba675SRob Herring compatible = "st,stm32-pwm"; 552724ba675SRob Herring #pwm-cells = <3>; 553724ba675SRob Herring status = "disabled"; 554724ba675SRob Herring }; 555724ba675SRob Herring }; 556724ba675SRob Herring 557*008ef8b3SDario Binacchi ltdc: display-controller@40016800 { 558*008ef8b3SDario Binacchi compatible = "st,stm32-ltdc"; 559*008ef8b3SDario Binacchi reg = <0x40016800 0x200>; 560*008ef8b3SDario Binacchi interrupts = <88>, <89>; 561*008ef8b3SDario Binacchi resets = <&rcc STM32F7_APB2_RESET(LTDC)>; 562*008ef8b3SDario Binacchi clocks = <&rcc 1 CLK_LCD>; 563*008ef8b3SDario Binacchi clock-names = "lcd"; 564*008ef8b3SDario Binacchi status = "disabled"; 565*008ef8b3SDario Binacchi }; 566*008ef8b3SDario Binacchi 567724ba675SRob Herring pwrcfg: power-config@40007000 { 568724ba675SRob Herring compatible = "st,stm32-power-config", "syscon"; 569724ba675SRob Herring reg = <0x40007000 0x400>; 570724ba675SRob Herring }; 571724ba675SRob Herring 572724ba675SRob Herring crc: crc@40023000 { 573724ba675SRob Herring compatible = "st,stm32f7-crc"; 574724ba675SRob Herring reg = <0x40023000 0x400>; 575724ba675SRob Herring clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; 576724ba675SRob Herring status = "disabled"; 577724ba675SRob Herring }; 578724ba675SRob Herring 579724ba675SRob Herring rcc: rcc@40023800 { 580724ba675SRob Herring #reset-cells = <1>; 581724ba675SRob Herring #clock-cells = <2>; 582724ba675SRob Herring compatible = "st,stm32f746-rcc", "st,stm32-rcc"; 583724ba675SRob Herring reg = <0x40023800 0x400>; 584724ba675SRob Herring clocks = <&clk_hse>, <&clk_i2s_ckin>; 585724ba675SRob Herring st,syscfg = <&pwrcfg>; 586724ba675SRob Herring assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 587724ba675SRob Herring assigned-clock-rates = <1000000>; 588724ba675SRob Herring }; 589724ba675SRob Herring 590724ba675SRob Herring dma1: dma-controller@40026000 { 591724ba675SRob Herring compatible = "st,stm32-dma"; 592724ba675SRob Herring reg = <0x40026000 0x400>; 593724ba675SRob Herring interrupts = <11>, 594724ba675SRob Herring <12>, 595724ba675SRob Herring <13>, 596724ba675SRob Herring <14>, 597724ba675SRob Herring <15>, 598724ba675SRob Herring <16>, 599724ba675SRob Herring <17>, 600724ba675SRob Herring <47>; 601724ba675SRob Herring clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; 602724ba675SRob Herring #dma-cells = <4>; 603724ba675SRob Herring status = "disabled"; 604724ba675SRob Herring }; 605724ba675SRob Herring 606724ba675SRob Herring dma2: dma-controller@40026400 { 607724ba675SRob Herring compatible = "st,stm32-dma"; 608724ba675SRob Herring reg = <0x40026400 0x400>; 609724ba675SRob Herring interrupts = <56>, 610724ba675SRob Herring <57>, 611724ba675SRob Herring <58>, 612724ba675SRob Herring <59>, 613724ba675SRob Herring <60>, 614724ba675SRob Herring <68>, 615724ba675SRob Herring <69>, 616724ba675SRob Herring <70>; 617724ba675SRob Herring clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; 618724ba675SRob Herring #dma-cells = <4>; 619724ba675SRob Herring st,mem2mem; 620724ba675SRob Herring status = "disabled"; 621724ba675SRob Herring }; 622724ba675SRob Herring 623724ba675SRob Herring usbotg_hs: usb@40040000 { 624724ba675SRob Herring compatible = "st,stm32f7-hsotg"; 625724ba675SRob Herring reg = <0x40040000 0x40000>; 626724ba675SRob Herring interrupts = <77>; 627724ba675SRob Herring clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; 628724ba675SRob Herring clock-names = "otg"; 629724ba675SRob Herring g-rx-fifo-size = <256>; 630724ba675SRob Herring g-np-tx-fifo-size = <32>; 631724ba675SRob Herring g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 632724ba675SRob Herring status = "disabled"; 633724ba675SRob Herring }; 634724ba675SRob Herring 635724ba675SRob Herring usbotg_fs: usb@50000000 { 636724ba675SRob Herring compatible = "st,stm32f4x9-fsotg"; 637724ba675SRob Herring reg = <0x50000000 0x40000>; 638724ba675SRob Herring interrupts = <67>; 639724ba675SRob Herring clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; 640724ba675SRob Herring clock-names = "otg"; 641724ba675SRob Herring status = "disabled"; 642724ba675SRob Herring }; 643724ba675SRob Herring }; 644724ba675SRob Herring}; 645724ba675SRob Herring 646724ba675SRob Herring&systick { 647724ba675SRob Herring clocks = <&rcc 1 0>; 648724ba675SRob Herring status = "okay"; 649724ba675SRob Herring}; 650