1*724ba675SRob Herring/* 2*724ba675SRob Herring * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3*724ba675SRob Herring * 4*724ba675SRob Herring * This file is dual-licensed: you can use it either under the terms 5*724ba675SRob Herring * of the GPL or the X11 license, at your option. Note that this dual 6*724ba675SRob Herring * licensing only applies to this file, and not this project as a 7*724ba675SRob Herring * whole. 8*724ba675SRob Herring * 9*724ba675SRob Herring * a) This file is free software; you can redistribute it and/or 10*724ba675SRob Herring * modify it under the terms of the GNU General Public License as 11*724ba675SRob Herring * published by the Free Software Foundation; either version 2 of the 12*724ba675SRob Herring * License, or (at your option) any later version. 13*724ba675SRob Herring * 14*724ba675SRob Herring * This file is distributed in the hope that it will be useful, 15*724ba675SRob Herring * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*724ba675SRob Herring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*724ba675SRob Herring * GNU General Public License for more details. 18*724ba675SRob Herring * 19*724ba675SRob Herring * You should have received a copy of the GNU General Public 20*724ba675SRob Herring * License along with this file; if not, write to the Free 21*724ba675SRob Herring * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22*724ba675SRob Herring * MA 02110-1301 USA 23*724ba675SRob Herring * 24*724ba675SRob Herring * Or, alternatively, 25*724ba675SRob Herring * 26*724ba675SRob Herring * b) Permission is hereby granted, free of charge, to any person 27*724ba675SRob Herring * obtaining a copy of this software and associated documentation 28*724ba675SRob Herring * files (the "Software"), to deal in the Software without 29*724ba675SRob Herring * restriction, including without limitation the rights to use, 30*724ba675SRob Herring * copy, modify, merge, publish, distribute, sublicense, and/or 31*724ba675SRob Herring * sell copies of the Software, and to permit persons to whom the 32*724ba675SRob Herring * Software is furnished to do so, subject to the following 33*724ba675SRob Herring * conditions: 34*724ba675SRob Herring * 35*724ba675SRob Herring * The above copyright notice and this permission notice shall be 36*724ba675SRob Herring * included in all copies or substantial portions of the Software. 37*724ba675SRob Herring * 38*724ba675SRob Herring * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39*724ba675SRob Herring * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40*724ba675SRob Herring * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41*724ba675SRob Herring * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42*724ba675SRob Herring * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43*724ba675SRob Herring * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44*724ba675SRob Herring * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45*724ba675SRob Herring * OTHER DEALINGS IN THE SOFTWARE. 46*724ba675SRob Herring */ 47*724ba675SRob Herring 48*724ba675SRob Herring#include "../armv7-m.dtsi" 49*724ba675SRob Herring#include <dt-bindings/clock/stm32fx-clock.h> 50*724ba675SRob Herring#include <dt-bindings/mfd/stm32f4-rcc.h> 51*724ba675SRob Herring 52*724ba675SRob Herring/ { 53*724ba675SRob Herring #address-cells = <1>; 54*724ba675SRob Herring #size-cells = <1>; 55*724ba675SRob Herring 56*724ba675SRob Herring clocks { 57*724ba675SRob Herring clk_hse: clk-hse { 58*724ba675SRob Herring #clock-cells = <0>; 59*724ba675SRob Herring compatible = "fixed-clock"; 60*724ba675SRob Herring clock-frequency = <0>; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring clk_lse: clk-lse { 64*724ba675SRob Herring #clock-cells = <0>; 65*724ba675SRob Herring compatible = "fixed-clock"; 66*724ba675SRob Herring clock-frequency = <32768>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring 69*724ba675SRob Herring clk_lsi: clk-lsi { 70*724ba675SRob Herring #clock-cells = <0>; 71*724ba675SRob Herring compatible = "fixed-clock"; 72*724ba675SRob Herring clock-frequency = <32000>; 73*724ba675SRob Herring }; 74*724ba675SRob Herring 75*724ba675SRob Herring clk_i2s_ckin: i2s-ckin { 76*724ba675SRob Herring #clock-cells = <0>; 77*724ba675SRob Herring compatible = "fixed-clock"; 78*724ba675SRob Herring clock-frequency = <0>; 79*724ba675SRob Herring }; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring soc { 83*724ba675SRob Herring romem: efuse@1fff7800 { 84*724ba675SRob Herring compatible = "st,stm32f4-otp"; 85*724ba675SRob Herring reg = <0x1fff7800 0x400>; 86*724ba675SRob Herring #address-cells = <1>; 87*724ba675SRob Herring #size-cells = <1>; 88*724ba675SRob Herring ts_cal1: calib@22c { 89*724ba675SRob Herring reg = <0x22c 0x2>; 90*724ba675SRob Herring }; 91*724ba675SRob Herring ts_cal2: calib@22e { 92*724ba675SRob Herring reg = <0x22e 0x2>; 93*724ba675SRob Herring }; 94*724ba675SRob Herring }; 95*724ba675SRob Herring 96*724ba675SRob Herring timers2: timers@40000000 { 97*724ba675SRob Herring #address-cells = <1>; 98*724ba675SRob Herring #size-cells = <0>; 99*724ba675SRob Herring compatible = "st,stm32-timers"; 100*724ba675SRob Herring reg = <0x40000000 0x400>; 101*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 102*724ba675SRob Herring clock-names = "int"; 103*724ba675SRob Herring status = "disabled"; 104*724ba675SRob Herring 105*724ba675SRob Herring pwm { 106*724ba675SRob Herring compatible = "st,stm32-pwm"; 107*724ba675SRob Herring #pwm-cells = <3>; 108*724ba675SRob Herring status = "disabled"; 109*724ba675SRob Herring }; 110*724ba675SRob Herring 111*724ba675SRob Herring timer@1 { 112*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 113*724ba675SRob Herring reg = <1>; 114*724ba675SRob Herring status = "disabled"; 115*724ba675SRob Herring }; 116*724ba675SRob Herring }; 117*724ba675SRob Herring 118*724ba675SRob Herring timers3: timers@40000400 { 119*724ba675SRob Herring #address-cells = <1>; 120*724ba675SRob Herring #size-cells = <0>; 121*724ba675SRob Herring compatible = "st,stm32-timers"; 122*724ba675SRob Herring reg = <0x40000400 0x400>; 123*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 124*724ba675SRob Herring clock-names = "int"; 125*724ba675SRob Herring status = "disabled"; 126*724ba675SRob Herring 127*724ba675SRob Herring pwm { 128*724ba675SRob Herring compatible = "st,stm32-pwm"; 129*724ba675SRob Herring #pwm-cells = <3>; 130*724ba675SRob Herring status = "disabled"; 131*724ba675SRob Herring }; 132*724ba675SRob Herring 133*724ba675SRob Herring timer@2 { 134*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 135*724ba675SRob Herring reg = <2>; 136*724ba675SRob Herring status = "disabled"; 137*724ba675SRob Herring }; 138*724ba675SRob Herring }; 139*724ba675SRob Herring 140*724ba675SRob Herring timers4: timers@40000800 { 141*724ba675SRob Herring #address-cells = <1>; 142*724ba675SRob Herring #size-cells = <0>; 143*724ba675SRob Herring compatible = "st,stm32-timers"; 144*724ba675SRob Herring reg = <0x40000800 0x400>; 145*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 146*724ba675SRob Herring clock-names = "int"; 147*724ba675SRob Herring status = "disabled"; 148*724ba675SRob Herring 149*724ba675SRob Herring pwm { 150*724ba675SRob Herring compatible = "st,stm32-pwm"; 151*724ba675SRob Herring #pwm-cells = <3>; 152*724ba675SRob Herring status = "disabled"; 153*724ba675SRob Herring }; 154*724ba675SRob Herring 155*724ba675SRob Herring timer@3 { 156*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 157*724ba675SRob Herring reg = <3>; 158*724ba675SRob Herring status = "disabled"; 159*724ba675SRob Herring }; 160*724ba675SRob Herring }; 161*724ba675SRob Herring 162*724ba675SRob Herring timers5: timers@40000c00 { 163*724ba675SRob Herring #address-cells = <1>; 164*724ba675SRob Herring #size-cells = <0>; 165*724ba675SRob Herring compatible = "st,stm32-timers"; 166*724ba675SRob Herring reg = <0x40000C00 0x400>; 167*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 168*724ba675SRob Herring clock-names = "int"; 169*724ba675SRob Herring status = "disabled"; 170*724ba675SRob Herring 171*724ba675SRob Herring pwm { 172*724ba675SRob Herring compatible = "st,stm32-pwm"; 173*724ba675SRob Herring #pwm-cells = <3>; 174*724ba675SRob Herring status = "disabled"; 175*724ba675SRob Herring }; 176*724ba675SRob Herring 177*724ba675SRob Herring timer@4 { 178*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 179*724ba675SRob Herring reg = <4>; 180*724ba675SRob Herring status = "disabled"; 181*724ba675SRob Herring }; 182*724ba675SRob Herring }; 183*724ba675SRob Herring 184*724ba675SRob Herring timers6: timers@40001000 { 185*724ba675SRob Herring #address-cells = <1>; 186*724ba675SRob Herring #size-cells = <0>; 187*724ba675SRob Herring compatible = "st,stm32-timers"; 188*724ba675SRob Herring reg = <0x40001000 0x400>; 189*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 190*724ba675SRob Herring clock-names = "int"; 191*724ba675SRob Herring status = "disabled"; 192*724ba675SRob Herring 193*724ba675SRob Herring timer@5 { 194*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 195*724ba675SRob Herring reg = <5>; 196*724ba675SRob Herring status = "disabled"; 197*724ba675SRob Herring }; 198*724ba675SRob Herring }; 199*724ba675SRob Herring 200*724ba675SRob Herring timers7: timers@40001400 { 201*724ba675SRob Herring #address-cells = <1>; 202*724ba675SRob Herring #size-cells = <0>; 203*724ba675SRob Herring compatible = "st,stm32-timers"; 204*724ba675SRob Herring reg = <0x40001400 0x400>; 205*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 206*724ba675SRob Herring clock-names = "int"; 207*724ba675SRob Herring status = "disabled"; 208*724ba675SRob Herring 209*724ba675SRob Herring timer@6 { 210*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 211*724ba675SRob Herring reg = <6>; 212*724ba675SRob Herring status = "disabled"; 213*724ba675SRob Herring }; 214*724ba675SRob Herring }; 215*724ba675SRob Herring 216*724ba675SRob Herring timers12: timers@40001800 { 217*724ba675SRob Herring #address-cells = <1>; 218*724ba675SRob Herring #size-cells = <0>; 219*724ba675SRob Herring compatible = "st,stm32-timers"; 220*724ba675SRob Herring reg = <0x40001800 0x400>; 221*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; 222*724ba675SRob Herring clock-names = "int"; 223*724ba675SRob Herring status = "disabled"; 224*724ba675SRob Herring 225*724ba675SRob Herring pwm { 226*724ba675SRob Herring compatible = "st,stm32-pwm"; 227*724ba675SRob Herring #pwm-cells = <3>; 228*724ba675SRob Herring status = "disabled"; 229*724ba675SRob Herring }; 230*724ba675SRob Herring 231*724ba675SRob Herring timer@11 { 232*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 233*724ba675SRob Herring reg = <11>; 234*724ba675SRob Herring status = "disabled"; 235*724ba675SRob Herring }; 236*724ba675SRob Herring }; 237*724ba675SRob Herring 238*724ba675SRob Herring timers13: timers@40001c00 { 239*724ba675SRob Herring compatible = "st,stm32-timers"; 240*724ba675SRob Herring reg = <0x40001C00 0x400>; 241*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; 242*724ba675SRob Herring clock-names = "int"; 243*724ba675SRob Herring status = "disabled"; 244*724ba675SRob Herring 245*724ba675SRob Herring pwm { 246*724ba675SRob Herring compatible = "st,stm32-pwm"; 247*724ba675SRob Herring #pwm-cells = <3>; 248*724ba675SRob Herring status = "disabled"; 249*724ba675SRob Herring }; 250*724ba675SRob Herring }; 251*724ba675SRob Herring 252*724ba675SRob Herring timers14: timers@40002000 { 253*724ba675SRob Herring compatible = "st,stm32-timers"; 254*724ba675SRob Herring reg = <0x40002000 0x400>; 255*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; 256*724ba675SRob Herring clock-names = "int"; 257*724ba675SRob Herring status = "disabled"; 258*724ba675SRob Herring 259*724ba675SRob Herring pwm { 260*724ba675SRob Herring compatible = "st,stm32-pwm"; 261*724ba675SRob Herring #pwm-cells = <3>; 262*724ba675SRob Herring status = "disabled"; 263*724ba675SRob Herring }; 264*724ba675SRob Herring }; 265*724ba675SRob Herring 266*724ba675SRob Herring rtc: rtc@40002800 { 267*724ba675SRob Herring compatible = "st,stm32-rtc"; 268*724ba675SRob Herring reg = <0x40002800 0x400>; 269*724ba675SRob Herring clocks = <&rcc 1 CLK_RTC>; 270*724ba675SRob Herring assigned-clocks = <&rcc 1 CLK_RTC>; 271*724ba675SRob Herring assigned-clock-parents = <&rcc 1 CLK_LSE>; 272*724ba675SRob Herring interrupt-parent = <&exti>; 273*724ba675SRob Herring interrupts = <17 1>; 274*724ba675SRob Herring st,syscfg = <&pwrcfg 0x00 0x100>; 275*724ba675SRob Herring status = "disabled"; 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring iwdg: watchdog@40003000 { 279*724ba675SRob Herring compatible = "st,stm32-iwdg"; 280*724ba675SRob Herring reg = <0x40003000 0x400>; 281*724ba675SRob Herring clocks = <&clk_lsi>; 282*724ba675SRob Herring clock-names = "lsi"; 283*724ba675SRob Herring status = "disabled"; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring spi2: spi@40003800 { 287*724ba675SRob Herring #address-cells = <1>; 288*724ba675SRob Herring #size-cells = <0>; 289*724ba675SRob Herring compatible = "st,stm32f4-spi"; 290*724ba675SRob Herring reg = <0x40003800 0x400>; 291*724ba675SRob Herring interrupts = <36>; 292*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; 293*724ba675SRob Herring status = "disabled"; 294*724ba675SRob Herring }; 295*724ba675SRob Herring 296*724ba675SRob Herring spi3: spi@40003c00 { 297*724ba675SRob Herring #address-cells = <1>; 298*724ba675SRob Herring #size-cells = <0>; 299*724ba675SRob Herring compatible = "st,stm32f4-spi"; 300*724ba675SRob Herring reg = <0x40003c00 0x400>; 301*724ba675SRob Herring interrupts = <51>; 302*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; 303*724ba675SRob Herring status = "disabled"; 304*724ba675SRob Herring }; 305*724ba675SRob Herring 306*724ba675SRob Herring usart2: serial@40004400 { 307*724ba675SRob Herring compatible = "st,stm32-uart"; 308*724ba675SRob Herring reg = <0x40004400 0x400>; 309*724ba675SRob Herring interrupts = <38>; 310*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; 311*724ba675SRob Herring status = "disabled"; 312*724ba675SRob Herring }; 313*724ba675SRob Herring 314*724ba675SRob Herring usart3: serial@40004800 { 315*724ba675SRob Herring compatible = "st,stm32-uart"; 316*724ba675SRob Herring reg = <0x40004800 0x400>; 317*724ba675SRob Herring interrupts = <39>; 318*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; 319*724ba675SRob Herring status = "disabled"; 320*724ba675SRob Herring dmas = <&dma1 1 4 0x400 0x0>, 321*724ba675SRob Herring <&dma1 3 4 0x400 0x0>; 322*724ba675SRob Herring dma-names = "rx", "tx"; 323*724ba675SRob Herring }; 324*724ba675SRob Herring 325*724ba675SRob Herring usart4: serial@40004c00 { 326*724ba675SRob Herring compatible = "st,stm32-uart"; 327*724ba675SRob Herring reg = <0x40004c00 0x400>; 328*724ba675SRob Herring interrupts = <52>; 329*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; 330*724ba675SRob Herring status = "disabled"; 331*724ba675SRob Herring }; 332*724ba675SRob Herring 333*724ba675SRob Herring usart5: serial@40005000 { 334*724ba675SRob Herring compatible = "st,stm32-uart"; 335*724ba675SRob Herring reg = <0x40005000 0x400>; 336*724ba675SRob Herring interrupts = <53>; 337*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; 338*724ba675SRob Herring status = "disabled"; 339*724ba675SRob Herring }; 340*724ba675SRob Herring 341*724ba675SRob Herring i2c1: i2c@40005400 { 342*724ba675SRob Herring compatible = "st,stm32f4-i2c"; 343*724ba675SRob Herring reg = <0x40005400 0x400>; 344*724ba675SRob Herring interrupts = <31>, 345*724ba675SRob Herring <32>; 346*724ba675SRob Herring resets = <&rcc STM32F4_APB1_RESET(I2C1)>; 347*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; 348*724ba675SRob Herring #address-cells = <1>; 349*724ba675SRob Herring #size-cells = <0>; 350*724ba675SRob Herring status = "disabled"; 351*724ba675SRob Herring }; 352*724ba675SRob Herring 353*724ba675SRob Herring i2c3: i2c@40005c00 { 354*724ba675SRob Herring compatible = "st,stm32f4-i2c"; 355*724ba675SRob Herring reg = <0x40005c00 0x400>; 356*724ba675SRob Herring interrupts = <72>, 357*724ba675SRob Herring <73>; 358*724ba675SRob Herring resets = <&rcc STM32F4_APB1_RESET(I2C3)>; 359*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>; 360*724ba675SRob Herring #address-cells = <1>; 361*724ba675SRob Herring #size-cells = <0>; 362*724ba675SRob Herring status = "disabled"; 363*724ba675SRob Herring }; 364*724ba675SRob Herring 365*724ba675SRob Herring can1: can@40006400 { 366*724ba675SRob Herring compatible = "st,stm32f4-bxcan"; 367*724ba675SRob Herring reg = <0x40006400 0x200>; 368*724ba675SRob Herring interrupts = <19>, <20>, <21>, <22>; 369*724ba675SRob Herring interrupt-names = "tx", "rx0", "rx1", "sce"; 370*724ba675SRob Herring resets = <&rcc STM32F4_APB1_RESET(CAN1)>; 371*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; 372*724ba675SRob Herring st,can-primary; 373*724ba675SRob Herring st,gcan = <&gcan>; 374*724ba675SRob Herring status = "disabled"; 375*724ba675SRob Herring }; 376*724ba675SRob Herring 377*724ba675SRob Herring gcan: gcan@40006600 { 378*724ba675SRob Herring compatible = "st,stm32f4-gcan", "syscon"; 379*724ba675SRob Herring reg = <0x40006600 0x200>; 380*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; 381*724ba675SRob Herring }; 382*724ba675SRob Herring 383*724ba675SRob Herring can2: can@40006800 { 384*724ba675SRob Herring compatible = "st,stm32f4-bxcan"; 385*724ba675SRob Herring reg = <0x40006800 0x200>; 386*724ba675SRob Herring interrupts = <63>, <64>, <65>, <66>; 387*724ba675SRob Herring interrupt-names = "tx", "rx0", "rx1", "sce"; 388*724ba675SRob Herring resets = <&rcc STM32F4_APB1_RESET(CAN2)>; 389*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; 390*724ba675SRob Herring st,can-secondary; 391*724ba675SRob Herring st,gcan = <&gcan>; 392*724ba675SRob Herring status = "disabled"; 393*724ba675SRob Herring }; 394*724ba675SRob Herring 395*724ba675SRob Herring dac: dac@40007400 { 396*724ba675SRob Herring compatible = "st,stm32f4-dac-core"; 397*724ba675SRob Herring reg = <0x40007400 0x400>; 398*724ba675SRob Herring resets = <&rcc STM32F4_APB1_RESET(DAC)>; 399*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; 400*724ba675SRob Herring clock-names = "pclk"; 401*724ba675SRob Herring #address-cells = <1>; 402*724ba675SRob Herring #size-cells = <0>; 403*724ba675SRob Herring status = "disabled"; 404*724ba675SRob Herring 405*724ba675SRob Herring dac1: dac@1 { 406*724ba675SRob Herring compatible = "st,stm32-dac"; 407*724ba675SRob Herring #io-channel-cells = <1>; 408*724ba675SRob Herring reg = <1>; 409*724ba675SRob Herring status = "disabled"; 410*724ba675SRob Herring }; 411*724ba675SRob Herring 412*724ba675SRob Herring dac2: dac@2 { 413*724ba675SRob Herring compatible = "st,stm32-dac"; 414*724ba675SRob Herring #io-channel-cells = <1>; 415*724ba675SRob Herring reg = <2>; 416*724ba675SRob Herring status = "disabled"; 417*724ba675SRob Herring }; 418*724ba675SRob Herring }; 419*724ba675SRob Herring 420*724ba675SRob Herring usart7: serial@40007800 { 421*724ba675SRob Herring compatible = "st,stm32-uart"; 422*724ba675SRob Herring reg = <0x40007800 0x400>; 423*724ba675SRob Herring interrupts = <82>; 424*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; 425*724ba675SRob Herring status = "disabled"; 426*724ba675SRob Herring }; 427*724ba675SRob Herring 428*724ba675SRob Herring usart8: serial@40007c00 { 429*724ba675SRob Herring compatible = "st,stm32-uart"; 430*724ba675SRob Herring reg = <0x40007c00 0x400>; 431*724ba675SRob Herring interrupts = <83>; 432*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; 433*724ba675SRob Herring status = "disabled"; 434*724ba675SRob Herring }; 435*724ba675SRob Herring 436*724ba675SRob Herring timers1: timers@40010000 { 437*724ba675SRob Herring #address-cells = <1>; 438*724ba675SRob Herring #size-cells = <0>; 439*724ba675SRob Herring compatible = "st,stm32-timers"; 440*724ba675SRob Herring reg = <0x40010000 0x400>; 441*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; 442*724ba675SRob Herring clock-names = "int"; 443*724ba675SRob Herring status = "disabled"; 444*724ba675SRob Herring 445*724ba675SRob Herring pwm { 446*724ba675SRob Herring compatible = "st,stm32-pwm"; 447*724ba675SRob Herring #pwm-cells = <3>; 448*724ba675SRob Herring status = "disabled"; 449*724ba675SRob Herring }; 450*724ba675SRob Herring 451*724ba675SRob Herring timer@0 { 452*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 453*724ba675SRob Herring reg = <0>; 454*724ba675SRob Herring status = "disabled"; 455*724ba675SRob Herring }; 456*724ba675SRob Herring }; 457*724ba675SRob Herring 458*724ba675SRob Herring timers8: timers@40010400 { 459*724ba675SRob Herring #address-cells = <1>; 460*724ba675SRob Herring #size-cells = <0>; 461*724ba675SRob Herring compatible = "st,stm32-timers"; 462*724ba675SRob Herring reg = <0x40010400 0x400>; 463*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; 464*724ba675SRob Herring clock-names = "int"; 465*724ba675SRob Herring status = "disabled"; 466*724ba675SRob Herring 467*724ba675SRob Herring pwm { 468*724ba675SRob Herring compatible = "st,stm32-pwm"; 469*724ba675SRob Herring #pwm-cells = <3>; 470*724ba675SRob Herring status = "disabled"; 471*724ba675SRob Herring }; 472*724ba675SRob Herring 473*724ba675SRob Herring timer@7 { 474*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 475*724ba675SRob Herring reg = <7>; 476*724ba675SRob Herring status = "disabled"; 477*724ba675SRob Herring }; 478*724ba675SRob Herring }; 479*724ba675SRob Herring 480*724ba675SRob Herring usart1: serial@40011000 { 481*724ba675SRob Herring compatible = "st,stm32-uart"; 482*724ba675SRob Herring reg = <0x40011000 0x400>; 483*724ba675SRob Herring interrupts = <37>; 484*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; 485*724ba675SRob Herring status = "disabled"; 486*724ba675SRob Herring dmas = <&dma2 2 4 0x400 0x0>, 487*724ba675SRob Herring <&dma2 7 4 0x400 0x0>; 488*724ba675SRob Herring dma-names = "rx", "tx"; 489*724ba675SRob Herring }; 490*724ba675SRob Herring 491*724ba675SRob Herring usart6: serial@40011400 { 492*724ba675SRob Herring compatible = "st,stm32-uart"; 493*724ba675SRob Herring reg = <0x40011400 0x400>; 494*724ba675SRob Herring interrupts = <71>; 495*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; 496*724ba675SRob Herring status = "disabled"; 497*724ba675SRob Herring }; 498*724ba675SRob Herring 499*724ba675SRob Herring adc: adc@40012000 { 500*724ba675SRob Herring compatible = "st,stm32f4-adc-core"; 501*724ba675SRob Herring reg = <0x40012000 0x400>; 502*724ba675SRob Herring interrupts = <18>; 503*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 504*724ba675SRob Herring clock-names = "adc"; 505*724ba675SRob Herring interrupt-controller; 506*724ba675SRob Herring #interrupt-cells = <1>; 507*724ba675SRob Herring #address-cells = <1>; 508*724ba675SRob Herring #size-cells = <0>; 509*724ba675SRob Herring status = "disabled"; 510*724ba675SRob Herring 511*724ba675SRob Herring adc1: adc@0 { 512*724ba675SRob Herring compatible = "st,stm32f4-adc"; 513*724ba675SRob Herring #io-channel-cells = <1>; 514*724ba675SRob Herring reg = <0x0>; 515*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 516*724ba675SRob Herring interrupt-parent = <&adc>; 517*724ba675SRob Herring interrupts = <0>; 518*724ba675SRob Herring dmas = <&dma2 0 0 0x400 0x0>; 519*724ba675SRob Herring dma-names = "rx"; 520*724ba675SRob Herring status = "disabled"; 521*724ba675SRob Herring }; 522*724ba675SRob Herring 523*724ba675SRob Herring adc2: adc@100 { 524*724ba675SRob Herring compatible = "st,stm32f4-adc"; 525*724ba675SRob Herring #io-channel-cells = <1>; 526*724ba675SRob Herring reg = <0x100>; 527*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; 528*724ba675SRob Herring interrupt-parent = <&adc>; 529*724ba675SRob Herring interrupts = <1>; 530*724ba675SRob Herring dmas = <&dma2 3 1 0x400 0x0>; 531*724ba675SRob Herring dma-names = "rx"; 532*724ba675SRob Herring status = "disabled"; 533*724ba675SRob Herring }; 534*724ba675SRob Herring 535*724ba675SRob Herring adc3: adc@200 { 536*724ba675SRob Herring compatible = "st,stm32f4-adc"; 537*724ba675SRob Herring #io-channel-cells = <1>; 538*724ba675SRob Herring reg = <0x200>; 539*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; 540*724ba675SRob Herring interrupt-parent = <&adc>; 541*724ba675SRob Herring interrupts = <2>; 542*724ba675SRob Herring dmas = <&dma2 1 2 0x400 0x0>; 543*724ba675SRob Herring dma-names = "rx"; 544*724ba675SRob Herring status = "disabled"; 545*724ba675SRob Herring }; 546*724ba675SRob Herring }; 547*724ba675SRob Herring 548*724ba675SRob Herring sdio: mmc@40012c00 { 549*724ba675SRob Herring compatible = "arm,pl180", "arm,primecell"; 550*724ba675SRob Herring arm,primecell-periphid = <0x00880180>; 551*724ba675SRob Herring reg = <0x40012c00 0x400>; 552*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; 553*724ba675SRob Herring clock-names = "apb_pclk"; 554*724ba675SRob Herring interrupts = <49>; 555*724ba675SRob Herring max-frequency = <48000000>; 556*724ba675SRob Herring status = "disabled"; 557*724ba675SRob Herring }; 558*724ba675SRob Herring 559*724ba675SRob Herring spi1: spi@40013000 { 560*724ba675SRob Herring #address-cells = <1>; 561*724ba675SRob Herring #size-cells = <0>; 562*724ba675SRob Herring compatible = "st,stm32f4-spi"; 563*724ba675SRob Herring reg = <0x40013000 0x400>; 564*724ba675SRob Herring interrupts = <35>; 565*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; 566*724ba675SRob Herring status = "disabled"; 567*724ba675SRob Herring }; 568*724ba675SRob Herring 569*724ba675SRob Herring spi4: spi@40013400 { 570*724ba675SRob Herring #address-cells = <1>; 571*724ba675SRob Herring #size-cells = <0>; 572*724ba675SRob Herring compatible = "st,stm32f4-spi"; 573*724ba675SRob Herring reg = <0x40013400 0x400>; 574*724ba675SRob Herring interrupts = <84>; 575*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; 576*724ba675SRob Herring status = "disabled"; 577*724ba675SRob Herring }; 578*724ba675SRob Herring 579*724ba675SRob Herring syscfg: syscon@40013800 { 580*724ba675SRob Herring compatible = "st,stm32-syscfg", "syscon"; 581*724ba675SRob Herring reg = <0x40013800 0x400>; 582*724ba675SRob Herring }; 583*724ba675SRob Herring 584*724ba675SRob Herring exti: interrupt-controller@40013c00 { 585*724ba675SRob Herring compatible = "st,stm32-exti"; 586*724ba675SRob Herring interrupt-controller; 587*724ba675SRob Herring #interrupt-cells = <2>; 588*724ba675SRob Herring reg = <0x40013C00 0x400>; 589*724ba675SRob Herring interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 590*724ba675SRob Herring }; 591*724ba675SRob Herring 592*724ba675SRob Herring timers9: timers@40014000 { 593*724ba675SRob Herring #address-cells = <1>; 594*724ba675SRob Herring #size-cells = <0>; 595*724ba675SRob Herring compatible = "st,stm32-timers"; 596*724ba675SRob Herring reg = <0x40014000 0x400>; 597*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; 598*724ba675SRob Herring clock-names = "int"; 599*724ba675SRob Herring status = "disabled"; 600*724ba675SRob Herring 601*724ba675SRob Herring pwm { 602*724ba675SRob Herring compatible = "st,stm32-pwm"; 603*724ba675SRob Herring #pwm-cells = <3>; 604*724ba675SRob Herring status = "disabled"; 605*724ba675SRob Herring }; 606*724ba675SRob Herring 607*724ba675SRob Herring timer@8 { 608*724ba675SRob Herring compatible = "st,stm32-timer-trigger"; 609*724ba675SRob Herring reg = <8>; 610*724ba675SRob Herring status = "disabled"; 611*724ba675SRob Herring }; 612*724ba675SRob Herring }; 613*724ba675SRob Herring 614*724ba675SRob Herring timers10: timers@40014400 { 615*724ba675SRob Herring compatible = "st,stm32-timers"; 616*724ba675SRob Herring reg = <0x40014400 0x400>; 617*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; 618*724ba675SRob Herring clock-names = "int"; 619*724ba675SRob Herring status = "disabled"; 620*724ba675SRob Herring 621*724ba675SRob Herring pwm { 622*724ba675SRob Herring compatible = "st,stm32-pwm"; 623*724ba675SRob Herring #pwm-cells = <3>; 624*724ba675SRob Herring status = "disabled"; 625*724ba675SRob Herring }; 626*724ba675SRob Herring }; 627*724ba675SRob Herring 628*724ba675SRob Herring timers11: timers@40014800 { 629*724ba675SRob Herring compatible = "st,stm32-timers"; 630*724ba675SRob Herring reg = <0x40014800 0x400>; 631*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; 632*724ba675SRob Herring clock-names = "int"; 633*724ba675SRob Herring status = "disabled"; 634*724ba675SRob Herring 635*724ba675SRob Herring pwm { 636*724ba675SRob Herring compatible = "st,stm32-pwm"; 637*724ba675SRob Herring #pwm-cells = <3>; 638*724ba675SRob Herring status = "disabled"; 639*724ba675SRob Herring }; 640*724ba675SRob Herring }; 641*724ba675SRob Herring 642*724ba675SRob Herring spi5: spi@40015000 { 643*724ba675SRob Herring #address-cells = <1>; 644*724ba675SRob Herring #size-cells = <0>; 645*724ba675SRob Herring compatible = "st,stm32f4-spi"; 646*724ba675SRob Herring reg = <0x40015000 0x400>; 647*724ba675SRob Herring interrupts = <85>; 648*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; 649*724ba675SRob Herring dmas = <&dma2 3 2 0x400 0x0>, 650*724ba675SRob Herring <&dma2 4 2 0x400 0x0>; 651*724ba675SRob Herring dma-names = "rx", "tx"; 652*724ba675SRob Herring status = "disabled"; 653*724ba675SRob Herring }; 654*724ba675SRob Herring 655*724ba675SRob Herring spi6: spi@40015400 { 656*724ba675SRob Herring #address-cells = <1>; 657*724ba675SRob Herring #size-cells = <0>; 658*724ba675SRob Herring compatible = "st,stm32f4-spi"; 659*724ba675SRob Herring reg = <0x40015400 0x400>; 660*724ba675SRob Herring interrupts = <86>; 661*724ba675SRob Herring clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; 662*724ba675SRob Herring status = "disabled"; 663*724ba675SRob Herring }; 664*724ba675SRob Herring 665*724ba675SRob Herring pwrcfg: power-config@40007000 { 666*724ba675SRob Herring compatible = "st,stm32-power-config", "syscon"; 667*724ba675SRob Herring reg = <0x40007000 0x400>; 668*724ba675SRob Herring }; 669*724ba675SRob Herring 670*724ba675SRob Herring ltdc: display-controller@40016800 { 671*724ba675SRob Herring compatible = "st,stm32-ltdc"; 672*724ba675SRob Herring reg = <0x40016800 0x200>; 673*724ba675SRob Herring interrupts = <88>, <89>; 674*724ba675SRob Herring resets = <&rcc STM32F4_APB2_RESET(LTDC)>; 675*724ba675SRob Herring clocks = <&rcc 1 CLK_LCD>; 676*724ba675SRob Herring clock-names = "lcd"; 677*724ba675SRob Herring status = "disabled"; 678*724ba675SRob Herring }; 679*724ba675SRob Herring 680*724ba675SRob Herring crc: crc@40023000 { 681*724ba675SRob Herring compatible = "st,stm32f4-crc"; 682*724ba675SRob Herring reg = <0x40023000 0x400>; 683*724ba675SRob Herring clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; 684*724ba675SRob Herring status = "disabled"; 685*724ba675SRob Herring }; 686*724ba675SRob Herring 687*724ba675SRob Herring rcc: rcc@40023800 { 688*724ba675SRob Herring #reset-cells = <1>; 689*724ba675SRob Herring #clock-cells = <2>; 690*724ba675SRob Herring compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; 691*724ba675SRob Herring reg = <0x40023800 0x400>; 692*724ba675SRob Herring clocks = <&clk_hse>, <&clk_i2s_ckin>; 693*724ba675SRob Herring st,syscfg = <&pwrcfg>; 694*724ba675SRob Herring assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 695*724ba675SRob Herring assigned-clock-rates = <1000000>; 696*724ba675SRob Herring }; 697*724ba675SRob Herring 698*724ba675SRob Herring dma1: dma-controller@40026000 { 699*724ba675SRob Herring compatible = "st,stm32-dma"; 700*724ba675SRob Herring reg = <0x40026000 0x400>; 701*724ba675SRob Herring interrupts = <11>, 702*724ba675SRob Herring <12>, 703*724ba675SRob Herring <13>, 704*724ba675SRob Herring <14>, 705*724ba675SRob Herring <15>, 706*724ba675SRob Herring <16>, 707*724ba675SRob Herring <17>, 708*724ba675SRob Herring <47>; 709*724ba675SRob Herring clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; 710*724ba675SRob Herring #dma-cells = <4>; 711*724ba675SRob Herring }; 712*724ba675SRob Herring 713*724ba675SRob Herring dma2: dma-controller@40026400 { 714*724ba675SRob Herring compatible = "st,stm32-dma"; 715*724ba675SRob Herring reg = <0x40026400 0x400>; 716*724ba675SRob Herring interrupts = <56>, 717*724ba675SRob Herring <57>, 718*724ba675SRob Herring <58>, 719*724ba675SRob Herring <59>, 720*724ba675SRob Herring <60>, 721*724ba675SRob Herring <68>, 722*724ba675SRob Herring <69>, 723*724ba675SRob Herring <70>; 724*724ba675SRob Herring clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; 725*724ba675SRob Herring #dma-cells = <4>; 726*724ba675SRob Herring st,mem2mem; 727*724ba675SRob Herring }; 728*724ba675SRob Herring 729*724ba675SRob Herring mac: ethernet@40028000 { 730*724ba675SRob Herring compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; 731*724ba675SRob Herring reg = <0x40028000 0x8000>; 732*724ba675SRob Herring reg-names = "stmmaceth"; 733*724ba675SRob Herring interrupts = <61>; 734*724ba675SRob Herring interrupt-names = "macirq"; 735*724ba675SRob Herring clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 736*724ba675SRob Herring clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, 737*724ba675SRob Herring <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, 738*724ba675SRob Herring <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; 739*724ba675SRob Herring st,syscon = <&syscfg 0x4>; 740*724ba675SRob Herring snps,pbl = <8>; 741*724ba675SRob Herring snps,mixed-burst; 742*724ba675SRob Herring status = "disabled"; 743*724ba675SRob Herring }; 744*724ba675SRob Herring 745*724ba675SRob Herring dma2d: dma2d@4002b000 { 746*724ba675SRob Herring compatible = "st,stm32-dma2d"; 747*724ba675SRob Herring reg = <0x4002b000 0xc00>; 748*724ba675SRob Herring interrupts = <90>; 749*724ba675SRob Herring resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; 750*724ba675SRob Herring clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; 751*724ba675SRob Herring clock-names = "dma2d"; 752*724ba675SRob Herring status = "disabled"; 753*724ba675SRob Herring }; 754*724ba675SRob Herring 755*724ba675SRob Herring usbotg_hs: usb@40040000 { 756*724ba675SRob Herring compatible = "snps,dwc2"; 757*724ba675SRob Herring reg = <0x40040000 0x40000>; 758*724ba675SRob Herring interrupts = <77>; 759*724ba675SRob Herring clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; 760*724ba675SRob Herring clock-names = "otg"; 761*724ba675SRob Herring status = "disabled"; 762*724ba675SRob Herring }; 763*724ba675SRob Herring 764*724ba675SRob Herring usbotg_fs: usb@50000000 { 765*724ba675SRob Herring compatible = "st,stm32f4x9-fsotg"; 766*724ba675SRob Herring reg = <0x50000000 0x40000>; 767*724ba675SRob Herring interrupts = <67>; 768*724ba675SRob Herring clocks = <&rcc 0 39>; 769*724ba675SRob Herring clock-names = "otg"; 770*724ba675SRob Herring status = "disabled"; 771*724ba675SRob Herring }; 772*724ba675SRob Herring 773*724ba675SRob Herring dcmi: dcmi@50050000 { 774*724ba675SRob Herring compatible = "st,stm32-dcmi"; 775*724ba675SRob Herring reg = <0x50050000 0x400>; 776*724ba675SRob Herring interrupts = <78>; 777*724ba675SRob Herring resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; 778*724ba675SRob Herring clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; 779*724ba675SRob Herring clock-names = "mclk"; 780*724ba675SRob Herring pinctrl-names = "default"; 781*724ba675SRob Herring pinctrl-0 = <&dcmi_pins>; 782*724ba675SRob Herring dmas = <&dma2 1 1 0x414 0x3>; 783*724ba675SRob Herring dma-names = "tx"; 784*724ba675SRob Herring status = "disabled"; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring rng: rng@50060800 { 788*724ba675SRob Herring compatible = "st,stm32-rng"; 789*724ba675SRob Herring reg = <0x50060800 0x400>; 790*724ba675SRob Herring clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; 791*724ba675SRob Herring 792*724ba675SRob Herring }; 793*724ba675SRob Herring }; 794*724ba675SRob Herring}; 795*724ba675SRob Herring 796*724ba675SRob Herring&systick { 797*724ba675SRob Herring clocks = <&rcc 1 SYSTICK>; 798*724ba675SRob Herring status = "okay"; 799*724ba675SRob Herring}; 800