1/* 2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/pinctrl/stm32-pinfunc.h> 44#include <dt-bindings/mfd/stm32f4-rcc.h> 45 46/ { 47 soc { 48 pinctrl: pinctrl@40020000 { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 ranges = <0 0x40020000 0x3000>; 52 interrupt-parent = <&exti>; 53 st,syscfg = <&syscfg 0x8>; 54 55 gpioa: gpio@40020000 { 56 gpio-controller; 57 #gpio-cells = <2>; 58 interrupt-controller; 59 #interrupt-cells = <2>; 60 reg = <0x0 0x400>; 61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; 62 st,bank-name = "GPIOA"; 63 }; 64 65 gpiob: gpio@40020400 { 66 gpio-controller; 67 #gpio-cells = <2>; 68 interrupt-controller; 69 #interrupt-cells = <2>; 70 reg = <0x400 0x400>; 71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; 72 st,bank-name = "GPIOB"; 73 }; 74 75 gpioc: gpio@40020800 { 76 gpio-controller; 77 #gpio-cells = <2>; 78 interrupt-controller; 79 #interrupt-cells = <2>; 80 reg = <0x800 0x400>; 81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; 82 st,bank-name = "GPIOC"; 83 }; 84 85 gpiod: gpio@40020c00 { 86 gpio-controller; 87 #gpio-cells = <2>; 88 interrupt-controller; 89 #interrupt-cells = <2>; 90 reg = <0xc00 0x400>; 91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; 92 st,bank-name = "GPIOD"; 93 }; 94 95 gpioe: gpio@40021000 { 96 gpio-controller; 97 #gpio-cells = <2>; 98 interrupt-controller; 99 #interrupt-cells = <2>; 100 reg = <0x1000 0x400>; 101 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; 102 st,bank-name = "GPIOE"; 103 }; 104 105 gpiof: gpio@40021400 { 106 gpio-controller; 107 #gpio-cells = <2>; 108 interrupt-controller; 109 #interrupt-cells = <2>; 110 reg = <0x1400 0x400>; 111 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; 112 st,bank-name = "GPIOF"; 113 }; 114 115 gpiog: gpio@40021800 { 116 gpio-controller; 117 #gpio-cells = <2>; 118 interrupt-controller; 119 #interrupt-cells = <2>; 120 reg = <0x1800 0x400>; 121 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; 122 st,bank-name = "GPIOG"; 123 }; 124 125 gpioh: gpio@40021c00 { 126 gpio-controller; 127 #gpio-cells = <2>; 128 interrupt-controller; 129 #interrupt-cells = <2>; 130 reg = <0x1c00 0x400>; 131 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; 132 st,bank-name = "GPIOH"; 133 }; 134 135 gpioi: gpio@40022000 { 136 gpio-controller; 137 #gpio-cells = <2>; 138 interrupt-controller; 139 #interrupt-cells = <2>; 140 reg = <0x2000 0x400>; 141 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; 142 st,bank-name = "GPIOI"; 143 }; 144 145 gpioj: gpio@40022400 { 146 gpio-controller; 147 #gpio-cells = <2>; 148 interrupt-controller; 149 #interrupt-cells = <2>; 150 reg = <0x2400 0x400>; 151 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; 152 st,bank-name = "GPIOJ"; 153 }; 154 155 gpiok: gpio@40022800 { 156 gpio-controller; 157 #gpio-cells = <2>; 158 interrupt-controller; 159 #interrupt-cells = <2>; 160 reg = <0x2800 0x400>; 161 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; 162 st,bank-name = "GPIOK"; 163 }; 164 165 usart1_pins_a: usart1-0 { 166 pins1 { 167 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ 168 bias-disable; 169 drive-push-pull; 170 slew-rate = <0>; 171 }; 172 pins2 { 173 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ 174 bias-disable; 175 }; 176 }; 177 178 usart3_pins_a: usart3-0 { 179 pins1 { 180 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ 181 bias-disable; 182 drive-push-pull; 183 slew-rate = <0>; 184 }; 185 pins2 { 186 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ 187 bias-disable; 188 }; 189 }; 190 191 usbotg_fs_pins_a: usbotg-fs-0 { 192 pins { 193 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ 194 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ 195 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */ 196 bias-disable; 197 drive-push-pull; 198 slew-rate = <2>; 199 }; 200 }; 201 202 usbotg_fs_pins_b: usbotg-fs-1 { 203 pins { 204 pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */ 205 <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */ 206 <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */ 207 bias-disable; 208 drive-push-pull; 209 slew-rate = <2>; 210 }; 211 }; 212 213 usbotg_hs_pins_a: usbotg-hs-0 { 214 pins { 215 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/ 216 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ 217 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ 218 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ 219 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ 220 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ 221 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ 222 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ 223 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ 224 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ 225 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ 226 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ 227 bias-disable; 228 drive-push-pull; 229 slew-rate = <2>; 230 }; 231 }; 232 233 ethernet_mii: mii-0 { 234 pins { 235 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */ 236 <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */ 237 <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */ 238 <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */ 239 <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */ 240 <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ 241 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ 242 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */ 243 <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ 244 <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ 245 <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */ 246 <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */ 247 <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */ 248 <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */ 249 slew-rate = <2>; 250 }; 251 }; 252 253 adc3_in8_pin: adc-200 { 254 pins { 255 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; 256 }; 257 }; 258 259 pwm1_pins: pwm1-0 { 260 pins { 261 pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */ 262 <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */ 263 <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */ 264 }; 265 }; 266 267 pwm3_pins: pwm3-0 { 268 pins { 269 pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */ 270 <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ 271 }; 272 }; 273 274 i2c1_pins: i2c1-0 { 275 pins { 276 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */ 277 <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */ 278 bias-disable; 279 drive-open-drain; 280 slew-rate = <3>; 281 }; 282 }; 283 284 ltdc_pins_a: ltdc-0 { 285 pins { 286 pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ 287 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ 288 <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ 289 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ 290 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ 291 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ 292 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ 293 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ 294 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ 295 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/ 296 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ 297 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ 298 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ 299 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ 300 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ 301 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ 302 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ 303 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ 304 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ 305 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/ 306 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ 307 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ 308 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ 309 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ 310 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ 311 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ 312 <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */ 313 <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */ 314 slew-rate = <2>; 315 }; 316 }; 317 318 ltdc_pins_b: ltdc-1 { 319 pins { 320 pinmux = <STM32_PINMUX('C', 6, AF14)>, 321 /* LCD_HSYNC */ 322 <STM32_PINMUX('A', 4, AF14)>, 323 /* LCD_VSYNC */ 324 <STM32_PINMUX('G', 7, AF14)>, 325 /* LCD_CLK */ 326 <STM32_PINMUX('C', 10, AF14)>, 327 /* LCD_R2 */ 328 <STM32_PINMUX('B', 0, AF9)>, 329 /* LCD_R3 */ 330 <STM32_PINMUX('A', 11, AF14)>, 331 /* LCD_R4 */ 332 <STM32_PINMUX('A', 12, AF14)>, 333 /* LCD_R5 */ 334 <STM32_PINMUX('B', 1, AF9)>, 335 /* LCD_R6*/ 336 <STM32_PINMUX('G', 6, AF14)>, 337 /* LCD_R7 */ 338 <STM32_PINMUX('A', 6, AF14)>, 339 /* LCD_G2 */ 340 <STM32_PINMUX('G', 10, AF9)>, 341 /* LCD_G3 */ 342 <STM32_PINMUX('B', 10, AF14)>, 343 /* LCD_G4 */ 344 <STM32_PINMUX('D', 6, AF14)>, 345 /* LCD_B2 */ 346 <STM32_PINMUX('G', 11, AF14)>, 347 /* LCD_B3*/ 348 <STM32_PINMUX('B', 11, AF14)>, 349 /* LCD_G5 */ 350 <STM32_PINMUX('C', 7, AF14)>, 351 /* LCD_G6 */ 352 <STM32_PINMUX('D', 3, AF14)>, 353 /* LCD_G7 */ 354 <STM32_PINMUX('G', 12, AF9)>, 355 /* LCD_B4 */ 356 <STM32_PINMUX('A', 3, AF14)>, 357 /* LCD_B5 */ 358 <STM32_PINMUX('B', 8, AF14)>, 359 /* LCD_B6 */ 360 <STM32_PINMUX('B', 9, AF14)>, 361 /* LCD_B7 */ 362 <STM32_PINMUX('F', 10, AF14)>; 363 /* LCD_DE */ 364 slew-rate = <2>; 365 }; 366 }; 367 368 spi5_pins: spi5-0 { 369 pins1 { 370 pinmux = <STM32_PINMUX('F', 7, AF5)>, 371 /* SPI5_CLK */ 372 <STM32_PINMUX('F', 9, AF5)>; 373 /* SPI5_MOSI */ 374 bias-disable; 375 drive-push-pull; 376 slew-rate = <0>; 377 }; 378 pins2 { 379 pinmux = <STM32_PINMUX('F', 8, AF5)>; 380 /* SPI5_MISO */ 381 bias-disable; 382 }; 383 }; 384 385 i2c3_pins: i2c3-0 { 386 pins { 387 pinmux = <STM32_PINMUX('C', 9, AF4)>, 388 /* I2C3_SDA */ 389 <STM32_PINMUX('A', 8, AF4)>; 390 /* I2C3_SCL */ 391 bias-disable; 392 drive-open-drain; 393 slew-rate = <3>; 394 }; 395 }; 396 397 dcmi_pins: dcmi-0 { 398 pins { 399 pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ 400 <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */ 401 <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */ 402 <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */ 403 <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */ 404 <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */ 405 <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */ 406 <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */ 407 <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */ 408 <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */ 409 <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */ 410 <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */ 411 <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */ 412 <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */ 413 <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */ 414 bias-disable; 415 drive-push-pull; 416 slew-rate = <3>; 417 }; 418 }; 419 420 sdio_pins: sdio-pins-0 { 421 pins { 422 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */ 423 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */ 424 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */ 425 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */ 426 <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */ 427 <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */ 428 drive-push-pull; 429 slew-rate = <2>; 430 }; 431 }; 432 433 sdio_pins_od: sdio-pins-od-0 { 434 pins1 { 435 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */ 436 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */ 437 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */ 438 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */ 439 <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */ 440 drive-push-pull; 441 slew-rate = <2>; 442 }; 443 444 pins2 { 445 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */ 446 drive-open-drain; 447 slew-rate = <2>; 448 }; 449 }; 450 451 can1_pins_a: can1-0 { 452 pins1 { 453 pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */ 454 }; 455 pins2 { 456 pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */ 457 bias-pull-up; 458 }; 459 }; 460 461 can2_pins_a: can2-0 { 462 pins1 { 463 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ 464 }; 465 pins2 { 466 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ 467 bias-pull-up; 468 }; 469 }; 470 471 can2_pins_b: can2-1 { 472 pins1 { 473 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ 474 }; 475 pins2 { 476 pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */ 477 bias-pull-up; 478 }; 479 }; 480 }; 481 }; 482}; 483