1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2014 STMicroelectronics Limited. 4*724ba675SRob Herring * Author: Peter Griffin <peter.griffin@linaro.org> 5*724ba675SRob Herring */ 6*724ba675SRob Herring#include "stih418-clock.dtsi" 7*724ba675SRob Herring#include "stih407-family.dtsi" 8*724ba675SRob Herring#include "stih410-pinctrl.dtsi" 9*724ba675SRob Herring/ { 10*724ba675SRob Herring cpus { 11*724ba675SRob Herring #address-cells = <1>; 12*724ba675SRob Herring #size-cells = <0>; 13*724ba675SRob Herring cpu@2 { 14*724ba675SRob Herring device_type = "cpu"; 15*724ba675SRob Herring compatible = "arm,cortex-a9"; 16*724ba675SRob Herring reg = <2>; 17*724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 18*724ba675SRob Herring cpu-release-addr = <0x94100A4>; 19*724ba675SRob Herring }; 20*724ba675SRob Herring cpu@3 { 21*724ba675SRob Herring device_type = "cpu"; 22*724ba675SRob Herring compatible = "arm,cortex-a9"; 23*724ba675SRob Herring reg = <3>; 24*724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 25*724ba675SRob Herring cpu-release-addr = <0x94100A4>; 26*724ba675SRob Herring }; 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring usb2_picophy1: phy2 { 30*724ba675SRob Herring compatible = "st,stih407-usb2-phy"; 31*724ba675SRob Herring #phy-cells = <0>; 32*724ba675SRob Herring st,syscfg = <&syscfg_core 0xf8 0xf4>; 33*724ba675SRob Herring resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 34*724ba675SRob Herring <&picophyreset STIH407_PICOPHY0_RESET>; 35*724ba675SRob Herring reset-names = "global", "port"; 36*724ba675SRob Herring }; 37*724ba675SRob Herring 38*724ba675SRob Herring usb2_picophy2: phy3 { 39*724ba675SRob Herring compatible = "st,stih407-usb2-phy"; 40*724ba675SRob Herring #phy-cells = <0>; 41*724ba675SRob Herring st,syscfg = <&syscfg_core 0xfc 0xf4>; 42*724ba675SRob Herring resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 43*724ba675SRob Herring <&picophyreset STIH407_PICOPHY1_RESET>; 44*724ba675SRob Herring reset-names = "global", "port"; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring soc { 48*724ba675SRob Herring rng11: rng@8a8a000 { 49*724ba675SRob Herring status = "disabled"; 50*724ba675SRob Herring }; 51*724ba675SRob Herring 52*724ba675SRob Herring ohci0: usb@9a03c00 { 53*724ba675SRob Herring compatible = "st,st-ohci-300x"; 54*724ba675SRob Herring reg = <0x9a03c00 0x100>; 55*724ba675SRob Herring interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 56*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; 57*724ba675SRob Herring resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, 58*724ba675SRob Herring <&softreset STIH407_USB2_PORT0_SOFTRESET>; 59*724ba675SRob Herring reset-names = "power", "softreset"; 60*724ba675SRob Herring phys = <&usb2_picophy1>; 61*724ba675SRob Herring phy-names = "usb"; 62*724ba675SRob Herring }; 63*724ba675SRob Herring 64*724ba675SRob Herring ehci0: usb@9a03e00 { 65*724ba675SRob Herring compatible = "st,st-ehci-300x"; 66*724ba675SRob Herring reg = <0x9a03e00 0x100>; 67*724ba675SRob Herring interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 68*724ba675SRob Herring pinctrl-names = "default"; 69*724ba675SRob Herring pinctrl-0 = <&pinctrl_usb0>; 70*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; 71*724ba675SRob Herring resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, 72*724ba675SRob Herring <&softreset STIH407_USB2_PORT0_SOFTRESET>; 73*724ba675SRob Herring reset-names = "power", "softreset"; 74*724ba675SRob Herring phys = <&usb2_picophy1>; 75*724ba675SRob Herring phy-names = "usb"; 76*724ba675SRob Herring }; 77*724ba675SRob Herring 78*724ba675SRob Herring ohci1: usb@9a83c00 { 79*724ba675SRob Herring compatible = "st,st-ohci-300x"; 80*724ba675SRob Herring reg = <0x9a83c00 0x100>; 81*724ba675SRob Herring interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 82*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; 83*724ba675SRob Herring resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, 84*724ba675SRob Herring <&softreset STIH407_USB2_PORT1_SOFTRESET>; 85*724ba675SRob Herring reset-names = "power", "softreset"; 86*724ba675SRob Herring phys = <&usb2_picophy2>; 87*724ba675SRob Herring phy-names = "usb"; 88*724ba675SRob Herring }; 89*724ba675SRob Herring 90*724ba675SRob Herring ehci1: usb@9a83e00 { 91*724ba675SRob Herring compatible = "st,st-ehci-300x"; 92*724ba675SRob Herring reg = <0x9a83e00 0x100>; 93*724ba675SRob Herring interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 94*724ba675SRob Herring pinctrl-names = "default"; 95*724ba675SRob Herring pinctrl-0 = <&pinctrl_usb1>; 96*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; 97*724ba675SRob Herring resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, 98*724ba675SRob Herring <&softreset STIH407_USB2_PORT1_SOFTRESET>; 99*724ba675SRob Herring reset-names = "power", "softreset"; 100*724ba675SRob Herring phys = <&usb2_picophy2>; 101*724ba675SRob Herring phy-names = "usb"; 102*724ba675SRob Herring }; 103*724ba675SRob Herring 104*724ba675SRob Herring mmc0: sdhci@9060000 { 105*724ba675SRob Herring assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; 106*724ba675SRob Herring assigned-clock-parents = <&clk_s_c0_pll1 0>; 107*724ba675SRob Herring assigned-clock-rates = <200000000>; 108*724ba675SRob Herring }; 109*724ba675SRob Herring 110*724ba675SRob Herring thermal@91a0000 { 111*724ba675SRob Herring compatible = "st,stih407-thermal"; 112*724ba675SRob Herring reg = <0x91a0000 0x28>; 113*724ba675SRob Herring clock-names = "thermal"; 114*724ba675SRob Herring clocks = <&clk_sysin>; 115*724ba675SRob Herring interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring }; 118*724ba675SRob Herring}; 119