1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2021 STMicroelectronics 4*724ba675SRob Herring * Author: Alain Volmat <avolmat@me.com> 5*724ba675SRob Herring */ 6*724ba675SRob Herring/dts-v1/; 7*724ba675SRob Herring#include "stih418.dtsi" 8*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 9*724ba675SRob Herring/ { 10*724ba675SRob Herring model = "STiH418 B2264"; 11*724ba675SRob Herring compatible = "st,stih418-b2264", "st,stih418"; 12*724ba675SRob Herring 13*724ba675SRob Herring chosen { 14*724ba675SRob Herring stdout-path = &sbc_serial0; 15*724ba675SRob Herring }; 16*724ba675SRob Herring 17*724ba675SRob Herring memory@40000000 { 18*724ba675SRob Herring device_type = "memory"; 19*724ba675SRob Herring reg = <0x40000000 0xc0000000>; 20*724ba675SRob Herring }; 21*724ba675SRob Herring 22*724ba675SRob Herring cpus { 23*724ba675SRob Herring cpu@0 { 24*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 25*724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xb8 offset */ 26*724ba675SRob Herring cpu-release-addr = <0x94100b8>; 27*724ba675SRob Herring }; 28*724ba675SRob Herring cpu@1 { 29*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 30*724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xb8 offset */ 31*724ba675SRob Herring cpu-release-addr = <0x94100b8>; 32*724ba675SRob Herring }; 33*724ba675SRob Herring cpu@2 { 34*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 35*724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xb8 offset */ 36*724ba675SRob Herring cpu-release-addr = <0x94100b8>; 37*724ba675SRob Herring }; 38*724ba675SRob Herring cpu@3 { 39*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 40*724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xb8 offset */ 41*724ba675SRob Herring cpu-release-addr = <0x94100b8>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring cpu_opp_table: opp-table { 46*724ba675SRob Herring compatible = "operating-points-v2"; 47*724ba675SRob Herring opp-shared; 48*724ba675SRob Herring 49*724ba675SRob Herring opp00 { 50*724ba675SRob Herring opp-hz = /bits/ 64 <300000000>; 51*724ba675SRob Herring opp-microvolt = <784000>; 52*724ba675SRob Herring }; 53*724ba675SRob Herring opp01 { 54*724ba675SRob Herring opp-hz = /bits/ 64 <500000000>; 55*724ba675SRob Herring opp-microvolt = <784000>; 56*724ba675SRob Herring }; 57*724ba675SRob Herring opp02 { 58*724ba675SRob Herring opp-hz = /bits/ 64 <800000000>; 59*724ba675SRob Herring opp-microvolt = <784000>; 60*724ba675SRob Herring }; 61*724ba675SRob Herring opp03 { 62*724ba675SRob Herring opp-hz = /bits/ 64 <1200000000>; 63*724ba675SRob Herring opp-microvolt = <784000>; 64*724ba675SRob Herring }; 65*724ba675SRob Herring opp04 { 66*724ba675SRob Herring opp-hz = /bits/ 64 <1500000000>; 67*724ba675SRob Herring opp-microvolt = <784000>; 68*724ba675SRob Herring }; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring aliases { 72*724ba675SRob Herring ttyAS0 = &sbc_serial0; 73*724ba675SRob Herring ethernet0 = ðernet0; 74*724ba675SRob Herring }; 75*724ba675SRob Herring 76*724ba675SRob Herring soc { 77*724ba675SRob Herring leds { 78*724ba675SRob Herring compatible = "gpio-leds"; 79*724ba675SRob Herring led-green { 80*724ba675SRob Herring gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; 81*724ba675SRob Herring default-state = "off"; 82*724ba675SRob Herring }; 83*724ba675SRob Herring }; 84*724ba675SRob Herring 85*724ba675SRob Herring pin-controller-sbc@961f080 { 86*724ba675SRob Herring gmac1 { 87*724ba675SRob Herring rgmii1-0 { 88*724ba675SRob Herring st,pins { 89*724ba675SRob Herring rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>; 90*724ba675SRob Herring rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>; 91*724ba675SRob Herring rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>; 92*724ba675SRob Herring rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>; 93*724ba675SRob Herring rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>; 94*724ba675SRob Herring }; 95*724ba675SRob Herring }; 96*724ba675SRob Herring }; 97*724ba675SRob Herring }; 98*724ba675SRob Herring 99*724ba675SRob Herring }; 100*724ba675SRob Herring}; 101*724ba675SRob Herring 102*724ba675SRob Herring&ehci0 { 103*724ba675SRob Herring status = "okay"; 104*724ba675SRob Herring}; 105*724ba675SRob Herring 106*724ba675SRob Herringðernet0 { 107*724ba675SRob Herring phy-mode = "rgmii"; 108*724ba675SRob Herring pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; 109*724ba675SRob Herring st,tx-retime-src = "clkgen"; 110*724ba675SRob Herring 111*724ba675SRob Herring snps,reset-gpio = <&pio0 7 0>; 112*724ba675SRob Herring snps,reset-active-low; 113*724ba675SRob Herring snps,reset-delays-us = <0 10000 1000000>; 114*724ba675SRob Herring 115*724ba675SRob Herring status = "okay"; 116*724ba675SRob Herring}; 117*724ba675SRob Herring 118*724ba675SRob Herring&miphy28lp_phy { 119*724ba675SRob Herring phy_port0: port@9b22000 { 120*724ba675SRob Herring st,sata-gen = <2>; /* SATA GEN3 */ 121*724ba675SRob Herring st,osc-rdy; 122*724ba675SRob Herring }; 123*724ba675SRob Herring}; 124*724ba675SRob Herring 125*724ba675SRob Herring&mmc0 { 126*724ba675SRob Herring status = "okay"; 127*724ba675SRob Herring}; 128*724ba675SRob Herring 129*724ba675SRob Herring&ohci1 { 130*724ba675SRob Herring status = "okay"; 131*724ba675SRob Herring}; 132*724ba675SRob Herring 133*724ba675SRob Herring&pwm1 { 134*724ba675SRob Herring status = "okay"; 135*724ba675SRob Herring}; 136*724ba675SRob Herring 137*724ba675SRob Herring&sata0 { 138*724ba675SRob Herring status = "okay"; 139*724ba675SRob Herring}; 140*724ba675SRob Herring 141*724ba675SRob Herring&sbc_serial0 { 142*724ba675SRob Herring status = "okay"; 143*724ba675SRob Herring}; 144*724ba675SRob Herring 145*724ba675SRob Herring&spifsm { 146*724ba675SRob Herring status = "okay"; 147*724ba675SRob Herring}; 148*724ba675SRob Herring 149*724ba675SRob Herring&st_dwc3 { 150*724ba675SRob Herring status = "okay"; 151*724ba675SRob Herring}; 152