1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2014 STMicroelectronics Limited. 4*724ba675SRob Herring * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 5*724ba675SRob Herring */ 6*724ba675SRob Herring#include "stih407-pinctrl.dtsi" 7*724ba675SRob Herring#include <dt-bindings/mfd/st-lpc.h> 8*724ba675SRob Herring#include <dt-bindings/phy/phy.h> 9*724ba675SRob Herring#include <dt-bindings/reset/stih407-resets.h> 10*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq-st.h> 11*724ba675SRob Herring/ { 12*724ba675SRob Herring #address-cells = <1>; 13*724ba675SRob Herring #size-cells = <1>; 14*724ba675SRob Herring 15*724ba675SRob Herring reserved-memory { 16*724ba675SRob Herring #address-cells = <1>; 17*724ba675SRob Herring #size-cells = <1>; 18*724ba675SRob Herring ranges; 19*724ba675SRob Herring 20*724ba675SRob Herring gp0_reserved: rproc@45000000 { 21*724ba675SRob Herring compatible = "shared-dma-pool"; 22*724ba675SRob Herring reg = <0x45000000 0x00400000>; 23*724ba675SRob Herring no-map; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring delta_reserved: rproc@44000000 { 27*724ba675SRob Herring compatible = "shared-dma-pool"; 28*724ba675SRob Herring reg = <0x44000000 0x01000000>; 29*724ba675SRob Herring no-map; 30*724ba675SRob Herring }; 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring cpus { 34*724ba675SRob Herring #address-cells = <1>; 35*724ba675SRob Herring #size-cells = <0>; 36*724ba675SRob Herring cpu@0 { 37*724ba675SRob Herring device_type = "cpu"; 38*724ba675SRob Herring compatible = "arm,cortex-a9"; 39*724ba675SRob Herring reg = <0>; 40*724ba675SRob Herring 41*724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 42*724ba675SRob Herring cpu-release-addr = <0x94100A4>; 43*724ba675SRob Herring 44*724ba675SRob Herring /* kHz uV */ 45*724ba675SRob Herring operating-points = <1500000 0 46*724ba675SRob Herring 1200000 0 47*724ba675SRob Herring 800000 0 48*724ba675SRob Herring 500000 0>; 49*724ba675SRob Herring 50*724ba675SRob Herring clocks = <&clk_m_a9>; 51*724ba675SRob Herring clock-names = "cpu"; 52*724ba675SRob Herring clock-latency = <100000>; 53*724ba675SRob Herring cpu0-supply = <&pwm_regulator>; 54*724ba675SRob Herring st,syscfg = <&syscfg_core 0x8e0>; 55*724ba675SRob Herring }; 56*724ba675SRob Herring cpu@1 { 57*724ba675SRob Herring device_type = "cpu"; 58*724ba675SRob Herring compatible = "arm,cortex-a9"; 59*724ba675SRob Herring reg = <1>; 60*724ba675SRob Herring 61*724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 62*724ba675SRob Herring cpu-release-addr = <0x94100A4>; 63*724ba675SRob Herring 64*724ba675SRob Herring /* kHz uV */ 65*724ba675SRob Herring operating-points = <1500000 0 66*724ba675SRob Herring 1200000 0 67*724ba675SRob Herring 800000 0 68*724ba675SRob Herring 500000 0>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring }; 71*724ba675SRob Herring 72*724ba675SRob Herring intc: interrupt-controller@8761000 { 73*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 74*724ba675SRob Herring #interrupt-cells = <3>; 75*724ba675SRob Herring interrupt-controller; 76*724ba675SRob Herring reg = <0x08761000 0x1000>, <0x08760100 0x100>; 77*724ba675SRob Herring }; 78*724ba675SRob Herring 79*724ba675SRob Herring scu@8760000 { 80*724ba675SRob Herring compatible = "arm,cortex-a9-scu"; 81*724ba675SRob Herring reg = <0x08760000 0x1000>; 82*724ba675SRob Herring }; 83*724ba675SRob Herring 84*724ba675SRob Herring timer@8760200 { 85*724ba675SRob Herring interrupt-parent = <&intc>; 86*724ba675SRob Herring compatible = "arm,cortex-a9-global-timer"; 87*724ba675SRob Herring reg = <0x08760200 0x100>; 88*724ba675SRob Herring interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 89*724ba675SRob Herring clocks = <&arm_periph_clk>; 90*724ba675SRob Herring }; 91*724ba675SRob Herring 92*724ba675SRob Herring l2: cache-controller@8762000 { 93*724ba675SRob Herring compatible = "arm,pl310-cache"; 94*724ba675SRob Herring reg = <0x08762000 0x1000>; 95*724ba675SRob Herring arm,data-latency = <3 3 3>; 96*724ba675SRob Herring arm,tag-latency = <2 2 2>; 97*724ba675SRob Herring cache-unified; 98*724ba675SRob Herring cache-level = <2>; 99*724ba675SRob Herring }; 100*724ba675SRob Herring 101*724ba675SRob Herring arm-pmu { 102*724ba675SRob Herring interrupt-parent = <&intc>; 103*724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 104*724ba675SRob Herring interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 105*724ba675SRob Herring }; 106*724ba675SRob Herring 107*724ba675SRob Herring pwm_regulator: pwm-regulator { 108*724ba675SRob Herring compatible = "pwm-regulator"; 109*724ba675SRob Herring pwms = <&pwm1 3 8448>; 110*724ba675SRob Herring regulator-name = "CPU_1V0_AVS"; 111*724ba675SRob Herring regulator-min-microvolt = <784000>; 112*724ba675SRob Herring regulator-max-microvolt = <1299000>; 113*724ba675SRob Herring regulator-always-on; 114*724ba675SRob Herring max-duty-cycle = <255>; 115*724ba675SRob Herring status = "okay"; 116*724ba675SRob Herring }; 117*724ba675SRob Herring 118*724ba675SRob Herring restart: restart-controller { 119*724ba675SRob Herring compatible = "st,stih407-restart"; 120*724ba675SRob Herring st,syscfg = <&syscfg_sbc_reg>; 121*724ba675SRob Herring status = "okay"; 122*724ba675SRob Herring }; 123*724ba675SRob Herring 124*724ba675SRob Herring powerdown: powerdown-controller { 125*724ba675SRob Herring compatible = "st,stih407-powerdown"; 126*724ba675SRob Herring #reset-cells = <1>; 127*724ba675SRob Herring }; 128*724ba675SRob Herring 129*724ba675SRob Herring softreset: softreset-controller { 130*724ba675SRob Herring compatible = "st,stih407-softreset"; 131*724ba675SRob Herring #reset-cells = <1>; 132*724ba675SRob Herring }; 133*724ba675SRob Herring 134*724ba675SRob Herring picophyreset: picophyreset-controller { 135*724ba675SRob Herring compatible = "st,stih407-picophyreset"; 136*724ba675SRob Herring #reset-cells = <1>; 137*724ba675SRob Herring }; 138*724ba675SRob Herring 139*724ba675SRob Herring irq-syscfg { 140*724ba675SRob Herring compatible = "st,stih407-irq-syscfg"; 141*724ba675SRob Herring st,syscfg = <&syscfg_core>; 142*724ba675SRob Herring st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 143*724ba675SRob Herring <ST_IRQ_SYSCFG_PMU_1>; 144*724ba675SRob Herring st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, 145*724ba675SRob Herring <ST_IRQ_SYSCFG_DISABLED>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring 148*724ba675SRob Herring usb2_picophy0: phy1 { 149*724ba675SRob Herring compatible = "st,stih407-usb2-phy"; 150*724ba675SRob Herring #phy-cells = <0>; 151*724ba675SRob Herring st,syscfg = <&syscfg_core 0x100 0xf4>; 152*724ba675SRob Herring resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 153*724ba675SRob Herring <&picophyreset STIH407_PICOPHY2_RESET>; 154*724ba675SRob Herring reset-names = "global", "port"; 155*724ba675SRob Herring }; 156*724ba675SRob Herring 157*724ba675SRob Herring miphy28lp_phy: miphy28lp { 158*724ba675SRob Herring compatible = "st,miphy28lp-phy"; 159*724ba675SRob Herring st,syscfg = <&syscfg_core>; 160*724ba675SRob Herring #address-cells = <1>; 161*724ba675SRob Herring #size-cells = <1>; 162*724ba675SRob Herring ranges; 163*724ba675SRob Herring 164*724ba675SRob Herring phy_port0: port@9b22000 { 165*724ba675SRob Herring reg = <0x9b22000 0xff>, 166*724ba675SRob Herring <0x9b09000 0xff>, 167*724ba675SRob Herring <0x9b04000 0xff>; 168*724ba675SRob Herring reg-names = "sata-up", 169*724ba675SRob Herring "pcie-up", 170*724ba675SRob Herring "pipew"; 171*724ba675SRob Herring 172*724ba675SRob Herring st,syscfg = <0x114 0x818 0xe0 0xec>; 173*724ba675SRob Herring #phy-cells = <1>; 174*724ba675SRob Herring 175*724ba675SRob Herring reset-names = "miphy-sw-rst"; 176*724ba675SRob Herring resets = <&softreset STIH407_MIPHY0_SOFTRESET>; 177*724ba675SRob Herring }; 178*724ba675SRob Herring 179*724ba675SRob Herring phy_port1: port@9b2a000 { 180*724ba675SRob Herring reg = <0x9b2a000 0xff>, 181*724ba675SRob Herring <0x9b19000 0xff>, 182*724ba675SRob Herring <0x9b14000 0xff>; 183*724ba675SRob Herring reg-names = "sata-up", 184*724ba675SRob Herring "pcie-up", 185*724ba675SRob Herring "pipew"; 186*724ba675SRob Herring 187*724ba675SRob Herring st,syscfg = <0x118 0x81c 0xe4 0xf0>; 188*724ba675SRob Herring 189*724ba675SRob Herring #phy-cells = <1>; 190*724ba675SRob Herring 191*724ba675SRob Herring reset-names = "miphy-sw-rst"; 192*724ba675SRob Herring resets = <&softreset STIH407_MIPHY1_SOFTRESET>; 193*724ba675SRob Herring }; 194*724ba675SRob Herring 195*724ba675SRob Herring phy_port2: port@8f95000 { 196*724ba675SRob Herring reg = <0x8f95000 0xff>, 197*724ba675SRob Herring <0x8f90000 0xff>; 198*724ba675SRob Herring reg-names = "pipew", 199*724ba675SRob Herring "usb3-up"; 200*724ba675SRob Herring 201*724ba675SRob Herring st,syscfg = <0x11c 0x820>; 202*724ba675SRob Herring 203*724ba675SRob Herring #phy-cells = <1>; 204*724ba675SRob Herring 205*724ba675SRob Herring reset-names = "miphy-sw-rst"; 206*724ba675SRob Herring resets = <&softreset STIH407_MIPHY2_SOFTRESET>; 207*724ba675SRob Herring }; 208*724ba675SRob Herring }; 209*724ba675SRob Herring 210*724ba675SRob Herring st231_gp0: st231-gp0 { 211*724ba675SRob Herring compatible = "st,st231-rproc"; 212*724ba675SRob Herring memory-region = <&gp0_reserved>; 213*724ba675SRob Herring resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; 214*724ba675SRob Herring reset-names = "sw_reset"; 215*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; 216*724ba675SRob Herring clock-frequency = <600000000>; 217*724ba675SRob Herring st,syscfg = <&syscfg_core 0x22c>; 218*724ba675SRob Herring #mbox-cells = <1>; 219*724ba675SRob Herring mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 220*724ba675SRob Herring mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; 221*724ba675SRob Herring }; 222*724ba675SRob Herring 223*724ba675SRob Herring st231_delta: st231-delta { 224*724ba675SRob Herring compatible = "st,st231-rproc"; 225*724ba675SRob Herring memory-region = <&delta_reserved>; 226*724ba675SRob Herring resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; 227*724ba675SRob Herring reset-names = "sw_reset"; 228*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; 229*724ba675SRob Herring clock-frequency = <600000000>; 230*724ba675SRob Herring st,syscfg = <&syscfg_core 0x224>; 231*724ba675SRob Herring #mbox-cells = <1>; 232*724ba675SRob Herring mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 233*724ba675SRob Herring mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; 234*724ba675SRob Herring }; 235*724ba675SRob Herring 236*724ba675SRob Herring delta0 { 237*724ba675SRob Herring compatible = "st,st-delta"; 238*724ba675SRob Herring clock-names = "delta", 239*724ba675SRob Herring "delta-st231", 240*724ba675SRob Herring "delta-flash-promip"; 241*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, 242*724ba675SRob Herring <&clk_s_c0_flexgen CLK_ST231_DMU>, 243*724ba675SRob Herring <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 244*724ba675SRob Herring }; 245*724ba675SRob Herring 246*724ba675SRob Herring soc { 247*724ba675SRob Herring #address-cells = <1>; 248*724ba675SRob Herring #size-cells = <1>; 249*724ba675SRob Herring interrupt-parent = <&intc>; 250*724ba675SRob Herring ranges; 251*724ba675SRob Herring compatible = "simple-bus"; 252*724ba675SRob Herring 253*724ba675SRob Herring syscfg_sbc: sbc-syscfg@9620000 { 254*724ba675SRob Herring compatible = "st,stih407-sbc-syscfg", "syscon"; 255*724ba675SRob Herring reg = <0x9620000 0x1000>; 256*724ba675SRob Herring }; 257*724ba675SRob Herring 258*724ba675SRob Herring syscfg_front: front-syscfg@9280000 { 259*724ba675SRob Herring compatible = "st,stih407-front-syscfg", "syscon"; 260*724ba675SRob Herring reg = <0x9280000 0x1000>; 261*724ba675SRob Herring }; 262*724ba675SRob Herring 263*724ba675SRob Herring syscfg_rear: rear-syscfg@9290000 { 264*724ba675SRob Herring compatible = "st,stih407-rear-syscfg", "syscon"; 265*724ba675SRob Herring reg = <0x9290000 0x1000>; 266*724ba675SRob Herring }; 267*724ba675SRob Herring 268*724ba675SRob Herring syscfg_flash: flash-syscfg@92a0000 { 269*724ba675SRob Herring compatible = "st,stih407-flash-syscfg", "syscon"; 270*724ba675SRob Herring reg = <0x92a0000 0x1000>; 271*724ba675SRob Herring }; 272*724ba675SRob Herring 273*724ba675SRob Herring syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { 274*724ba675SRob Herring compatible = "st,stih407-sbc-reg-syscfg", "syscon"; 275*724ba675SRob Herring reg = <0x9600000 0x1000>; 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring syscfg_core: core-syscfg@92b0000 { 279*724ba675SRob Herring compatible = "st,stih407-core-syscfg", "syscon"; 280*724ba675SRob Herring reg = <0x92b0000 0x1000>; 281*724ba675SRob Herring 282*724ba675SRob Herring sti_sasg_codec: sti-sasg-codec { 283*724ba675SRob Herring compatible = "st,stih407-sas-codec"; 284*724ba675SRob Herring #sound-dai-cells = <1>; 285*724ba675SRob Herring status = "disabled"; 286*724ba675SRob Herring st,syscfg = <&syscfg_core>; 287*724ba675SRob Herring }; 288*724ba675SRob Herring }; 289*724ba675SRob Herring 290*724ba675SRob Herring syscfg_lpm: lpm-syscfg@94b5100 { 291*724ba675SRob Herring compatible = "st,stih407-lpm-syscfg", "syscon"; 292*724ba675SRob Herring reg = <0x94b5100 0x1000>; 293*724ba675SRob Herring }; 294*724ba675SRob Herring 295*724ba675SRob Herring /* Display */ 296*724ba675SRob Herring vtg_main: sti-vtg-main@8d02800 { 297*724ba675SRob Herring compatible = "st,vtg"; 298*724ba675SRob Herring reg = <0x8d02800 0x200>; 299*724ba675SRob Herring interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 300*724ba675SRob Herring }; 301*724ba675SRob Herring 302*724ba675SRob Herring vtg_aux: sti-vtg-aux@8d00200 { 303*724ba675SRob Herring compatible = "st,vtg"; 304*724ba675SRob Herring reg = <0x8d00200 0x100>; 305*724ba675SRob Herring interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 306*724ba675SRob Herring }; 307*724ba675SRob Herring 308*724ba675SRob Herring serial@9830000 { 309*724ba675SRob Herring compatible = "st,asc"; 310*724ba675SRob Herring reg = <0x9830000 0x2c>; 311*724ba675SRob Herring interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 312*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 313*724ba675SRob Herring /* Pinctrl moved out to a per-board configuration */ 314*724ba675SRob Herring 315*724ba675SRob Herring status = "disabled"; 316*724ba675SRob Herring }; 317*724ba675SRob Herring 318*724ba675SRob Herring serial@9831000 { 319*724ba675SRob Herring compatible = "st,asc"; 320*724ba675SRob Herring reg = <0x9831000 0x2c>; 321*724ba675SRob Herring interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 322*724ba675SRob Herring pinctrl-names = "default"; 323*724ba675SRob Herring pinctrl-0 = <&pinctrl_serial1>; 324*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 325*724ba675SRob Herring 326*724ba675SRob Herring status = "disabled"; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring serial@9832000 { 330*724ba675SRob Herring compatible = "st,asc"; 331*724ba675SRob Herring reg = <0x9832000 0x2c>; 332*724ba675SRob Herring interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 333*724ba675SRob Herring pinctrl-names = "default"; 334*724ba675SRob Herring pinctrl-0 = <&pinctrl_serial2>; 335*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 336*724ba675SRob Herring 337*724ba675SRob Herring status = "disabled"; 338*724ba675SRob Herring }; 339*724ba675SRob Herring 340*724ba675SRob Herring /* SBC_ASC0 - UART10 */ 341*724ba675SRob Herring sbc_serial0: serial@9530000 { 342*724ba675SRob Herring compatible = "st,asc"; 343*724ba675SRob Herring reg = <0x9530000 0x2c>; 344*724ba675SRob Herring interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 345*724ba675SRob Herring pinctrl-names = "default"; 346*724ba675SRob Herring pinctrl-0 = <&pinctrl_sbc_serial0>; 347*724ba675SRob Herring clocks = <&clk_sysin>; 348*724ba675SRob Herring 349*724ba675SRob Herring status = "disabled"; 350*724ba675SRob Herring }; 351*724ba675SRob Herring 352*724ba675SRob Herring serial@9531000 { 353*724ba675SRob Herring compatible = "st,asc"; 354*724ba675SRob Herring reg = <0x9531000 0x2c>; 355*724ba675SRob Herring interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 356*724ba675SRob Herring pinctrl-names = "default"; 357*724ba675SRob Herring pinctrl-0 = <&pinctrl_sbc_serial1>; 358*724ba675SRob Herring clocks = <&clk_sysin>; 359*724ba675SRob Herring 360*724ba675SRob Herring status = "disabled"; 361*724ba675SRob Herring }; 362*724ba675SRob Herring 363*724ba675SRob Herring i2c@9840000 { 364*724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 365*724ba675SRob Herring interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 366*724ba675SRob Herring reg = <0x9840000 0x110>; 367*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 368*724ba675SRob Herring clock-names = "ssc"; 369*724ba675SRob Herring clock-frequency = <400000>; 370*724ba675SRob Herring pinctrl-names = "default"; 371*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c0_default>; 372*724ba675SRob Herring #address-cells = <1>; 373*724ba675SRob Herring #size-cells = <0>; 374*724ba675SRob Herring 375*724ba675SRob Herring status = "disabled"; 376*724ba675SRob Herring }; 377*724ba675SRob Herring 378*724ba675SRob Herring i2c@9841000 { 379*724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 380*724ba675SRob Herring reg = <0x9841000 0x110>; 381*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 382*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 383*724ba675SRob Herring clock-names = "ssc"; 384*724ba675SRob Herring clock-frequency = <400000>; 385*724ba675SRob Herring pinctrl-names = "default"; 386*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c1_default>; 387*724ba675SRob Herring #address-cells = <1>; 388*724ba675SRob Herring #size-cells = <0>; 389*724ba675SRob Herring 390*724ba675SRob Herring status = "disabled"; 391*724ba675SRob Herring }; 392*724ba675SRob Herring 393*724ba675SRob Herring i2c@9842000 { 394*724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 395*724ba675SRob Herring reg = <0x9842000 0x110>; 396*724ba675SRob Herring interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 397*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 398*724ba675SRob Herring clock-names = "ssc"; 399*724ba675SRob Herring clock-frequency = <400000>; 400*724ba675SRob Herring pinctrl-names = "default"; 401*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c2_default>; 402*724ba675SRob Herring #address-cells = <1>; 403*724ba675SRob Herring #size-cells = <0>; 404*724ba675SRob Herring 405*724ba675SRob Herring status = "disabled"; 406*724ba675SRob Herring }; 407*724ba675SRob Herring 408*724ba675SRob Herring i2c@9843000 { 409*724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 410*724ba675SRob Herring reg = <0x9843000 0x110>; 411*724ba675SRob Herring interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 412*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 413*724ba675SRob Herring clock-names = "ssc"; 414*724ba675SRob Herring clock-frequency = <400000>; 415*724ba675SRob Herring pinctrl-names = "default"; 416*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c3_default>; 417*724ba675SRob Herring #address-cells = <1>; 418*724ba675SRob Herring #size-cells = <0>; 419*724ba675SRob Herring 420*724ba675SRob Herring status = "disabled"; 421*724ba675SRob Herring }; 422*724ba675SRob Herring 423*724ba675SRob Herring i2c@9844000 { 424*724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 425*724ba675SRob Herring reg = <0x9844000 0x110>; 426*724ba675SRob Herring interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 427*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 428*724ba675SRob Herring clock-names = "ssc"; 429*724ba675SRob Herring clock-frequency = <400000>; 430*724ba675SRob Herring pinctrl-names = "default"; 431*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c4_default>; 432*724ba675SRob Herring #address-cells = <1>; 433*724ba675SRob Herring #size-cells = <0>; 434*724ba675SRob Herring 435*724ba675SRob Herring status = "disabled"; 436*724ba675SRob Herring }; 437*724ba675SRob Herring 438*724ba675SRob Herring i2c@9845000 { 439*724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 440*724ba675SRob Herring reg = <0x9845000 0x110>; 441*724ba675SRob Herring interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 442*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 443*724ba675SRob Herring clock-names = "ssc"; 444*724ba675SRob Herring clock-frequency = <400000>; 445*724ba675SRob Herring pinctrl-names = "default"; 446*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c5_default>; 447*724ba675SRob Herring #address-cells = <1>; 448*724ba675SRob Herring #size-cells = <0>; 449*724ba675SRob Herring 450*724ba675SRob Herring status = "disabled"; 451*724ba675SRob Herring }; 452*724ba675SRob Herring 453*724ba675SRob Herring 454*724ba675SRob Herring /* SSCs on SBC */ 455*724ba675SRob Herring i2c@9540000 { 456*724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 457*724ba675SRob Herring reg = <0x9540000 0x110>; 458*724ba675SRob Herring interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 459*724ba675SRob Herring clocks = <&clk_sysin>; 460*724ba675SRob Herring clock-names = "ssc"; 461*724ba675SRob Herring clock-frequency = <400000>; 462*724ba675SRob Herring pinctrl-names = "default"; 463*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c10_default>; 464*724ba675SRob Herring #address-cells = <1>; 465*724ba675SRob Herring #size-cells = <0>; 466*724ba675SRob Herring 467*724ba675SRob Herring status = "disabled"; 468*724ba675SRob Herring }; 469*724ba675SRob Herring 470*724ba675SRob Herring i2c@9541000 { 471*724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 472*724ba675SRob Herring reg = <0x9541000 0x110>; 473*724ba675SRob Herring interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 474*724ba675SRob Herring clocks = <&clk_sysin>; 475*724ba675SRob Herring clock-names = "ssc"; 476*724ba675SRob Herring clock-frequency = <400000>; 477*724ba675SRob Herring pinctrl-names = "default"; 478*724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c11_default>; 479*724ba675SRob Herring #address-cells = <1>; 480*724ba675SRob Herring #size-cells = <0>; 481*724ba675SRob Herring 482*724ba675SRob Herring status = "disabled"; 483*724ba675SRob Herring }; 484*724ba675SRob Herring 485*724ba675SRob Herring spi@9840000 { 486*724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 487*724ba675SRob Herring reg = <0x9840000 0x110>; 488*724ba675SRob Herring interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 489*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 490*724ba675SRob Herring clock-names = "ssc"; 491*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi0_default>; 492*724ba675SRob Herring pinctrl-names = "default"; 493*724ba675SRob Herring #address-cells = <1>; 494*724ba675SRob Herring #size-cells = <0>; 495*724ba675SRob Herring 496*724ba675SRob Herring status = "disabled"; 497*724ba675SRob Herring }; 498*724ba675SRob Herring 499*724ba675SRob Herring spi@9841000 { 500*724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 501*724ba675SRob Herring reg = <0x9841000 0x110>; 502*724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 503*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 504*724ba675SRob Herring clock-names = "ssc"; 505*724ba675SRob Herring pinctrl-names = "default"; 506*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi1_default>; 507*724ba675SRob Herring #address-cells = <1>; 508*724ba675SRob Herring #size-cells = <0>; 509*724ba675SRob Herring 510*724ba675SRob Herring status = "disabled"; 511*724ba675SRob Herring }; 512*724ba675SRob Herring 513*724ba675SRob Herring spi@9842000 { 514*724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 515*724ba675SRob Herring reg = <0x9842000 0x110>; 516*724ba675SRob Herring interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 517*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 518*724ba675SRob Herring clock-names = "ssc"; 519*724ba675SRob Herring pinctrl-names = "default"; 520*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi2_default>; 521*724ba675SRob Herring #address-cells = <1>; 522*724ba675SRob Herring #size-cells = <0>; 523*724ba675SRob Herring 524*724ba675SRob Herring status = "disabled"; 525*724ba675SRob Herring }; 526*724ba675SRob Herring 527*724ba675SRob Herring spi@9843000 { 528*724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 529*724ba675SRob Herring reg = <0x9843000 0x110>; 530*724ba675SRob Herring interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 531*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 532*724ba675SRob Herring clock-names = "ssc"; 533*724ba675SRob Herring pinctrl-names = "default"; 534*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi3_default>; 535*724ba675SRob Herring #address-cells = <1>; 536*724ba675SRob Herring #size-cells = <0>; 537*724ba675SRob Herring 538*724ba675SRob Herring status = "disabled"; 539*724ba675SRob Herring }; 540*724ba675SRob Herring 541*724ba675SRob Herring spi@9844000 { 542*724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 543*724ba675SRob Herring reg = <0x9844000 0x110>; 544*724ba675SRob Herring interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 545*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 546*724ba675SRob Herring clock-names = "ssc"; 547*724ba675SRob Herring pinctrl-names = "default"; 548*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi4_default>; 549*724ba675SRob Herring #address-cells = <1>; 550*724ba675SRob Herring #size-cells = <0>; 551*724ba675SRob Herring 552*724ba675SRob Herring status = "disabled"; 553*724ba675SRob Herring }; 554*724ba675SRob Herring 555*724ba675SRob Herring /* SBC SSC */ 556*724ba675SRob Herring spi@9540000 { 557*724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 558*724ba675SRob Herring reg = <0x9540000 0x110>; 559*724ba675SRob Herring interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 560*724ba675SRob Herring clocks = <&clk_sysin>; 561*724ba675SRob Herring clock-names = "ssc"; 562*724ba675SRob Herring pinctrl-names = "default"; 563*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi10_default>; 564*724ba675SRob Herring #address-cells = <1>; 565*724ba675SRob Herring #size-cells = <0>; 566*724ba675SRob Herring 567*724ba675SRob Herring status = "disabled"; 568*724ba675SRob Herring }; 569*724ba675SRob Herring 570*724ba675SRob Herring spi@9541000 { 571*724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 572*724ba675SRob Herring reg = <0x9541000 0x110>; 573*724ba675SRob Herring interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 574*724ba675SRob Herring clocks = <&clk_sysin>; 575*724ba675SRob Herring clock-names = "ssc"; 576*724ba675SRob Herring pinctrl-names = "default"; 577*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi11_default>; 578*724ba675SRob Herring #address-cells = <1>; 579*724ba675SRob Herring #size-cells = <0>; 580*724ba675SRob Herring 581*724ba675SRob Herring status = "disabled"; 582*724ba675SRob Herring }; 583*724ba675SRob Herring 584*724ba675SRob Herring spi@9542000 { 585*724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 586*724ba675SRob Herring reg = <0x9542000 0x110>; 587*724ba675SRob Herring interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 588*724ba675SRob Herring clocks = <&clk_sysin>; 589*724ba675SRob Herring clock-names = "ssc"; 590*724ba675SRob Herring pinctrl-names = "default"; 591*724ba675SRob Herring pinctrl-0 = <&pinctrl_spi12_default>; 592*724ba675SRob Herring #address-cells = <1>; 593*724ba675SRob Herring #size-cells = <0>; 594*724ba675SRob Herring 595*724ba675SRob Herring status = "disabled"; 596*724ba675SRob Herring }; 597*724ba675SRob Herring 598*724ba675SRob Herring mmc0: sdhci@9060000 { 599*724ba675SRob Herring compatible = "st,sdhci-stih407", "st,sdhci"; 600*724ba675SRob Herring status = "disabled"; 601*724ba675SRob Herring reg = <0x09060000 0x7ff>, <0x9061008 0x20>; 602*724ba675SRob Herring reg-names = "mmc", "top-mmc-delay"; 603*724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 604*724ba675SRob Herring interrupt-names = "mmcirq"; 605*724ba675SRob Herring pinctrl-names = "default"; 606*724ba675SRob Herring pinctrl-0 = <&pinctrl_mmc0>; 607*724ba675SRob Herring clock-names = "mmc", "icn"; 608*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_MMC_0>, 609*724ba675SRob Herring <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 610*724ba675SRob Herring bus-width = <8>; 611*724ba675SRob Herring }; 612*724ba675SRob Herring 613*724ba675SRob Herring mmc1: sdhci@9080000 { 614*724ba675SRob Herring compatible = "st,sdhci-stih407", "st,sdhci"; 615*724ba675SRob Herring status = "disabled"; 616*724ba675SRob Herring reg = <0x09080000 0x7ff>; 617*724ba675SRob Herring reg-names = "mmc"; 618*724ba675SRob Herring interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 619*724ba675SRob Herring interrupt-names = "mmcirq"; 620*724ba675SRob Herring pinctrl-names = "default"; 621*724ba675SRob Herring pinctrl-0 = <&pinctrl_sd1>; 622*724ba675SRob Herring clock-names = "mmc", "icn"; 623*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_MMC_1>, 624*724ba675SRob Herring <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 625*724ba675SRob Herring resets = <&softreset STIH407_MMC1_SOFTRESET>; 626*724ba675SRob Herring bus-width = <4>; 627*724ba675SRob Herring }; 628*724ba675SRob Herring 629*724ba675SRob Herring /* Watchdog and Real-Time Clock */ 630*724ba675SRob Herring lpc@8787000 { 631*724ba675SRob Herring compatible = "st,stih407-lpc"; 632*724ba675SRob Herring reg = <0x8787000 0x1000>; 633*724ba675SRob Herring interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; 634*724ba675SRob Herring clocks = <&clk_s_d3_flexgen CLK_LPC_0>; 635*724ba675SRob Herring timeout-sec = <120>; 636*724ba675SRob Herring st,syscfg = <&syscfg_core>; 637*724ba675SRob Herring st,lpc-mode = <ST_LPC_MODE_WDT>; 638*724ba675SRob Herring }; 639*724ba675SRob Herring 640*724ba675SRob Herring lpc@8788000 { 641*724ba675SRob Herring compatible = "st,stih407-lpc"; 642*724ba675SRob Herring reg = <0x8788000 0x1000>; 643*724ba675SRob Herring interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; 644*724ba675SRob Herring clocks = <&clk_s_d3_flexgen CLK_LPC_1>; 645*724ba675SRob Herring st,lpc-mode = <ST_LPC_MODE_CLKSRC>; 646*724ba675SRob Herring }; 647*724ba675SRob Herring 648*724ba675SRob Herring spifsm: spifsm@9022000 { 649*724ba675SRob Herring compatible = "st,spi-fsm"; 650*724ba675SRob Herring reg = <0x9022000 0x1000>; 651*724ba675SRob Herring reg-names = "spi-fsm"; 652*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 653*724ba675SRob Herring clock-names = "emi_clk"; 654*724ba675SRob Herring pinctrl-names = "default"; 655*724ba675SRob Herring pinctrl-0 = <&pinctrl_fsm>; 656*724ba675SRob Herring st,syscfg = <&syscfg_core>; 657*724ba675SRob Herring st,boot-device-reg = <0x8c4>; 658*724ba675SRob Herring st,boot-device-spi = <0x68>; 659*724ba675SRob Herring 660*724ba675SRob Herring status = "disabled"; 661*724ba675SRob Herring }; 662*724ba675SRob Herring 663*724ba675SRob Herring sata0: sata@9b20000 { 664*724ba675SRob Herring compatible = "st,ahci"; 665*724ba675SRob Herring reg = <0x9b20000 0x1000>; 666*724ba675SRob Herring 667*724ba675SRob Herring interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 668*724ba675SRob Herring interrupt-names = "hostc"; 669*724ba675SRob Herring 670*724ba675SRob Herring phys = <&phy_port0 PHY_TYPE_SATA>; 671*724ba675SRob Herring phy-names = "ahci_phy"; 672*724ba675SRob Herring 673*724ba675SRob Herring resets = <&powerdown STIH407_SATA0_POWERDOWN>, 674*724ba675SRob Herring <&softreset STIH407_SATA0_SOFTRESET>, 675*724ba675SRob Herring <&softreset STIH407_SATA0_PWR_SOFTRESET>; 676*724ba675SRob Herring reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; 677*724ba675SRob Herring 678*724ba675SRob Herring clock-names = "ahci_clk"; 679*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 680*724ba675SRob Herring 681*724ba675SRob Herring ports-implemented = <0x1>; 682*724ba675SRob Herring 683*724ba675SRob Herring status = "disabled"; 684*724ba675SRob Herring }; 685*724ba675SRob Herring 686*724ba675SRob Herring sata1: sata@9b28000 { 687*724ba675SRob Herring compatible = "st,ahci"; 688*724ba675SRob Herring reg = <0x9b28000 0x1000>; 689*724ba675SRob Herring 690*724ba675SRob Herring interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 691*724ba675SRob Herring interrupt-names = "hostc"; 692*724ba675SRob Herring 693*724ba675SRob Herring phys = <&phy_port1 PHY_TYPE_SATA>; 694*724ba675SRob Herring phy-names = "ahci_phy"; 695*724ba675SRob Herring 696*724ba675SRob Herring resets = <&powerdown STIH407_SATA1_POWERDOWN>, 697*724ba675SRob Herring <&softreset STIH407_SATA1_SOFTRESET>, 698*724ba675SRob Herring <&softreset STIH407_SATA1_PWR_SOFTRESET>; 699*724ba675SRob Herring reset-names = "pwr-dwn", 700*724ba675SRob Herring "sw-rst", 701*724ba675SRob Herring "pwr-rst"; 702*724ba675SRob Herring 703*724ba675SRob Herring clock-names = "ahci_clk"; 704*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 705*724ba675SRob Herring 706*724ba675SRob Herring ports-implemented = <0x1>; 707*724ba675SRob Herring 708*724ba675SRob Herring status = "disabled"; 709*724ba675SRob Herring }; 710*724ba675SRob Herring 711*724ba675SRob Herring 712*724ba675SRob Herring st_dwc3: dwc3@8f94000 { 713*724ba675SRob Herring compatible = "st,stih407-dwc3"; 714*724ba675SRob Herring reg = <0x08f94000 0x1000>, <0x110 0x4>; 715*724ba675SRob Herring reg-names = "reg-glue", "syscfg-reg"; 716*724ba675SRob Herring st,syscfg = <&syscfg_core>; 717*724ba675SRob Herring resets = <&powerdown STIH407_USB3_POWERDOWN>, 718*724ba675SRob Herring <&softreset STIH407_MIPHY2_SOFTRESET>; 719*724ba675SRob Herring reset-names = "powerdown", "softreset"; 720*724ba675SRob Herring #address-cells = <1>; 721*724ba675SRob Herring #size-cells = <1>; 722*724ba675SRob Herring pinctrl-names = "default"; 723*724ba675SRob Herring pinctrl-0 = <&pinctrl_usb3>; 724*724ba675SRob Herring ranges; 725*724ba675SRob Herring 726*724ba675SRob Herring status = "disabled"; 727*724ba675SRob Herring 728*724ba675SRob Herring dwc3: usb@9900000 { 729*724ba675SRob Herring compatible = "snps,dwc3"; 730*724ba675SRob Herring reg = <0x09900000 0x100000>; 731*724ba675SRob Herring interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 732*724ba675SRob Herring dr_mode = "host"; 733*724ba675SRob Herring phy-names = "usb2-phy", "usb3-phy"; 734*724ba675SRob Herring phys = <&usb2_picophy0>, 735*724ba675SRob Herring <&phy_port2 PHY_TYPE_USB3>; 736*724ba675SRob Herring snps,dis_u3_susphy_quirk; 737*724ba675SRob Herring }; 738*724ba675SRob Herring }; 739*724ba675SRob Herring 740*724ba675SRob Herring /* COMMS PWM Module */ 741*724ba675SRob Herring pwm0: pwm@9810000 { 742*724ba675SRob Herring compatible = "st,sti-pwm"; 743*724ba675SRob Herring #pwm-cells = <2>; 744*724ba675SRob Herring reg = <0x9810000 0x68>; 745*724ba675SRob Herring interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 746*724ba675SRob Herring pinctrl-names = "default"; 747*724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm0_chan0_default>; 748*724ba675SRob Herring clock-names = "pwm"; 749*724ba675SRob Herring clocks = <&clk_sysin>; 750*724ba675SRob Herring st,pwm-num-chan = <1>; 751*724ba675SRob Herring 752*724ba675SRob Herring status = "disabled"; 753*724ba675SRob Herring }; 754*724ba675SRob Herring 755*724ba675SRob Herring /* SBC PWM Module */ 756*724ba675SRob Herring pwm1: pwm@9510000 { 757*724ba675SRob Herring compatible = "st,sti-pwm"; 758*724ba675SRob Herring #pwm-cells = <2>; 759*724ba675SRob Herring reg = <0x9510000 0x68>; 760*724ba675SRob Herring interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 761*724ba675SRob Herring pinctrl-names = "default"; 762*724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm1_chan0_default 763*724ba675SRob Herring &pinctrl_pwm1_chan1_default 764*724ba675SRob Herring &pinctrl_pwm1_chan2_default 765*724ba675SRob Herring &pinctrl_pwm1_chan3_default>; 766*724ba675SRob Herring clock-names = "pwm"; 767*724ba675SRob Herring clocks = <&clk_sysin>; 768*724ba675SRob Herring st,pwm-num-chan = <4>; 769*724ba675SRob Herring 770*724ba675SRob Herring status = "disabled"; 771*724ba675SRob Herring }; 772*724ba675SRob Herring 773*724ba675SRob Herring rng10: rng@8a89000 { 774*724ba675SRob Herring compatible = "st,rng"; 775*724ba675SRob Herring reg = <0x08a89000 0x1000>; 776*724ba675SRob Herring clocks = <&clk_sysin>; 777*724ba675SRob Herring status = "okay"; 778*724ba675SRob Herring }; 779*724ba675SRob Herring 780*724ba675SRob Herring rng11: rng@8a8a000 { 781*724ba675SRob Herring compatible = "st,rng"; 782*724ba675SRob Herring reg = <0x08a8a000 0x1000>; 783*724ba675SRob Herring clocks = <&clk_sysin>; 784*724ba675SRob Herring status = "okay"; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring ethernet0: dwmac@9630000 { 788*724ba675SRob Herring device_type = "network"; 789*724ba675SRob Herring status = "disabled"; 790*724ba675SRob Herring compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 791*724ba675SRob Herring reg = <0x9630000 0x8000>, <0x80 0x4>; 792*724ba675SRob Herring reg-names = "stmmaceth", "sti-ethconf"; 793*724ba675SRob Herring 794*724ba675SRob Herring st,syscon = <&syscfg_sbc_reg 0x80>; 795*724ba675SRob Herring st,gmac_en; 796*724ba675SRob Herring resets = <&softreset STIH407_ETH1_SOFTRESET>; 797*724ba675SRob Herring reset-names = "stmmaceth"; 798*724ba675SRob Herring 799*724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 800*724ba675SRob Herring <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 801*724ba675SRob Herring interrupt-names = "macirq", "eth_wake_irq"; 802*724ba675SRob Herring 803*724ba675SRob Herring /* DMA Bus Mode */ 804*724ba675SRob Herring snps,pbl = <8>; 805*724ba675SRob Herring 806*724ba675SRob Herring pinctrl-names = "default"; 807*724ba675SRob Herring pinctrl-0 = <&pinctrl_rgmii1>; 808*724ba675SRob Herring 809*724ba675SRob Herring clock-names = "stmmaceth", "sti-ethclk"; 810*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, 811*724ba675SRob Herring <&clk_s_c0_flexgen CLK_ETH_PHY>; 812*724ba675SRob Herring }; 813*724ba675SRob Herring 814*724ba675SRob Herring mailbox0: mailbox@8f00000 { 815*724ba675SRob Herring compatible = "st,stih407-mailbox"; 816*724ba675SRob Herring reg = <0x8f00000 0x1000>; 817*724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 818*724ba675SRob Herring #mbox-cells = <2>; 819*724ba675SRob Herring mbox-name = "a9"; 820*724ba675SRob Herring status = "okay"; 821*724ba675SRob Herring }; 822*724ba675SRob Herring 823*724ba675SRob Herring mailbox1: mailbox@8f01000 { 824*724ba675SRob Herring compatible = "st,stih407-mailbox"; 825*724ba675SRob Herring reg = <0x8f01000 0x1000>; 826*724ba675SRob Herring #mbox-cells = <2>; 827*724ba675SRob Herring mbox-name = "st231_gp_1"; 828*724ba675SRob Herring status = "okay"; 829*724ba675SRob Herring }; 830*724ba675SRob Herring 831*724ba675SRob Herring mailbox2: mailbox@8f02000 { 832*724ba675SRob Herring compatible = "st,stih407-mailbox"; 833*724ba675SRob Herring reg = <0x8f02000 0x1000>; 834*724ba675SRob Herring #mbox-cells = <2>; 835*724ba675SRob Herring mbox-name = "st231_gp_0"; 836*724ba675SRob Herring status = "okay"; 837*724ba675SRob Herring }; 838*724ba675SRob Herring 839*724ba675SRob Herring mailbox3: mailbox@8f03000 { 840*724ba675SRob Herring compatible = "st,stih407-mailbox"; 841*724ba675SRob Herring reg = <0x8f03000 0x1000>; 842*724ba675SRob Herring #mbox-cells = <2>; 843*724ba675SRob Herring mbox-name = "st231_audio_video"; 844*724ba675SRob Herring status = "okay"; 845*724ba675SRob Herring }; 846*724ba675SRob Herring 847*724ba675SRob Herring /* fdma audio */ 848*724ba675SRob Herring fdma0: dma-controller@8e20000 { 849*724ba675SRob Herring compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; 850*724ba675SRob Herring reg = <0x8e20000 0x8000>, 851*724ba675SRob Herring <0x8e30000 0x3000>, 852*724ba675SRob Herring <0x8e37000 0x1000>, 853*724ba675SRob Herring <0x8e38000 0x8000>; 854*724ba675SRob Herring reg-names = "slimcore", "dmem", "peripherals", "imem"; 855*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_FDMA>, 856*724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>, 857*724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>, 858*724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>; 859*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 860*724ba675SRob Herring dma-channels = <16>; 861*724ba675SRob Herring #dma-cells = <3>; 862*724ba675SRob Herring }; 863*724ba675SRob Herring 864*724ba675SRob Herring /* fdma app */ 865*724ba675SRob Herring fdma1: dma-controller@8e40000 { 866*724ba675SRob Herring compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; 867*724ba675SRob Herring reg = <0x8e40000 0x8000>, 868*724ba675SRob Herring <0x8e50000 0x3000>, 869*724ba675SRob Herring <0x8e57000 0x1000>, 870*724ba675SRob Herring <0x8e58000 0x8000>; 871*724ba675SRob Herring reg-names = "slimcore", "dmem", "peripherals", "imem"; 872*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_FDMA>, 873*724ba675SRob Herring <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 874*724ba675SRob Herring <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 875*724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>; 876*724ba675SRob Herring 877*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 878*724ba675SRob Herring dma-channels = <16>; 879*724ba675SRob Herring #dma-cells = <3>; 880*724ba675SRob Herring 881*724ba675SRob Herring status = "disabled"; 882*724ba675SRob Herring }; 883*724ba675SRob Herring 884*724ba675SRob Herring /* fdma free running */ 885*724ba675SRob Herring fdma2: dma-controller@8e60000 { 886*724ba675SRob Herring compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; 887*724ba675SRob Herring reg = <0x8e60000 0x8000>, 888*724ba675SRob Herring <0x8e70000 0x3000>, 889*724ba675SRob Herring <0x8e77000 0x1000>, 890*724ba675SRob Herring <0x8e78000 0x8000>; 891*724ba675SRob Herring reg-names = "slimcore", "dmem", "peripherals", "imem"; 892*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 893*724ba675SRob Herring dma-channels = <16>; 894*724ba675SRob Herring #dma-cells = <3>; 895*724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_FDMA>, 896*724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>, 897*724ba675SRob Herring <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 898*724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>; 899*724ba675SRob Herring 900*724ba675SRob Herring status = "disabled"; 901*724ba675SRob Herring }; 902*724ba675SRob Herring 903*724ba675SRob Herring sti_uni_player0: sti-uni-player@8d80000 { 904*724ba675SRob Herring compatible = "st,stih407-uni-player-hdmi"; 905*724ba675SRob Herring #sound-dai-cells = <0>; 906*724ba675SRob Herring st,syscfg = <&syscfg_core>; 907*724ba675SRob Herring clocks = <&clk_s_d0_flexgen CLK_PCM_0>; 908*724ba675SRob Herring assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; 909*724ba675SRob Herring assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; 910*724ba675SRob Herring assigned-clock-rates = <50000000>; 911*724ba675SRob Herring reg = <0x8d80000 0x158>; 912*724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 913*724ba675SRob Herring dmas = <&fdma0 2 0 1>; 914*724ba675SRob Herring dma-names = "tx"; 915*724ba675SRob Herring 916*724ba675SRob Herring status = "disabled"; 917*724ba675SRob Herring }; 918*724ba675SRob Herring 919*724ba675SRob Herring sti_uni_player1: sti-uni-player@8d81000 { 920*724ba675SRob Herring compatible = "st,stih407-uni-player-pcm-out"; 921*724ba675SRob Herring #sound-dai-cells = <0>; 922*724ba675SRob Herring st,syscfg = <&syscfg_core>; 923*724ba675SRob Herring clocks = <&clk_s_d0_flexgen CLK_PCM_1>; 924*724ba675SRob Herring assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; 925*724ba675SRob Herring assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; 926*724ba675SRob Herring assigned-clock-rates = <50000000>; 927*724ba675SRob Herring reg = <0x8d81000 0x158>; 928*724ba675SRob Herring interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 929*724ba675SRob Herring dmas = <&fdma0 3 0 1>; 930*724ba675SRob Herring dma-names = "tx"; 931*724ba675SRob Herring 932*724ba675SRob Herring status = "disabled"; 933*724ba675SRob Herring }; 934*724ba675SRob Herring 935*724ba675SRob Herring sti_uni_player2: sti-uni-player@8d82000 { 936*724ba675SRob Herring compatible = "st,stih407-uni-player-dac"; 937*724ba675SRob Herring #sound-dai-cells = <0>; 938*724ba675SRob Herring st,syscfg = <&syscfg_core>; 939*724ba675SRob Herring clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 940*724ba675SRob Herring assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; 941*724ba675SRob Herring assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; 942*724ba675SRob Herring assigned-clock-rates = <50000000>; 943*724ba675SRob Herring reg = <0x8d82000 0x158>; 944*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 945*724ba675SRob Herring dmas = <&fdma0 4 0 1>; 946*724ba675SRob Herring dma-names = "tx"; 947*724ba675SRob Herring 948*724ba675SRob Herring status = "disabled"; 949*724ba675SRob Herring }; 950*724ba675SRob Herring 951*724ba675SRob Herring sti_uni_player3: sti-uni-player@8d85000 { 952*724ba675SRob Herring compatible = "st,stih407-uni-player-spdif"; 953*724ba675SRob Herring #sound-dai-cells = <0>; 954*724ba675SRob Herring st,syscfg = <&syscfg_core>; 955*724ba675SRob Herring clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; 956*724ba675SRob Herring assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; 957*724ba675SRob Herring assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; 958*724ba675SRob Herring assigned-clock-rates = <50000000>; 959*724ba675SRob Herring reg = <0x8d85000 0x158>; 960*724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 961*724ba675SRob Herring dmas = <&fdma0 7 0 1>; 962*724ba675SRob Herring dma-names = "tx"; 963*724ba675SRob Herring 964*724ba675SRob Herring status = "disabled"; 965*724ba675SRob Herring }; 966*724ba675SRob Herring 967*724ba675SRob Herring sti_uni_reader0: sti-uni-reader@8d83000 { 968*724ba675SRob Herring compatible = "st,stih407-uni-reader-pcm_in"; 969*724ba675SRob Herring #sound-dai-cells = <0>; 970*724ba675SRob Herring st,syscfg = <&syscfg_core>; 971*724ba675SRob Herring reg = <0x8d83000 0x158>; 972*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 973*724ba675SRob Herring dmas = <&fdma0 5 0 1>; 974*724ba675SRob Herring dma-names = "rx"; 975*724ba675SRob Herring 976*724ba675SRob Herring status = "disabled"; 977*724ba675SRob Herring }; 978*724ba675SRob Herring 979*724ba675SRob Herring sti_uni_reader1: sti-uni-reader@8d84000 { 980*724ba675SRob Herring compatible = "st,stih407-uni-reader-hdmi"; 981*724ba675SRob Herring #sound-dai-cells = <0>; 982*724ba675SRob Herring st,syscfg = <&syscfg_core>; 983*724ba675SRob Herring reg = <0x8d84000 0x158>; 984*724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 985*724ba675SRob Herring dmas = <&fdma0 6 0 1>; 986*724ba675SRob Herring dma-names = "rx"; 987*724ba675SRob Herring 988*724ba675SRob Herring status = "disabled"; 989*724ba675SRob Herring }; 990*724ba675SRob Herring }; 991*724ba675SRob Herring}; 992