1*724ba675SRob Herring /* SPDX-License-Identifier: GPL-2.0 */ 2*724ba675SRob Herring #ifndef _ST_PINCFG_H_ 3*724ba675SRob Herring #define _ST_PINCFG_H_ 4*724ba675SRob Herring 5*724ba675SRob Herring /* Alternate functions */ 6*724ba675SRob Herring #define ALT1 1 7*724ba675SRob Herring #define ALT2 2 8*724ba675SRob Herring #define ALT3 3 9*724ba675SRob Herring #define ALT4 4 10*724ba675SRob Herring #define ALT5 5 11*724ba675SRob Herring #define ALT6 6 12*724ba675SRob Herring #define ALT7 7 13*724ba675SRob Herring 14*724ba675SRob Herring /* Output enable */ 15*724ba675SRob Herring #define OE (1 << 27) 16*724ba675SRob Herring /* Pull Up */ 17*724ba675SRob Herring #define PU (1 << 26) 18*724ba675SRob Herring /* Open Drain */ 19*724ba675SRob Herring #define OD (1 << 25) 20*724ba675SRob Herring #define RT (1 << 23) 21*724ba675SRob Herring #define INVERTCLK (1 << 22) 22*724ba675SRob Herring #define CLKNOTDATA (1 << 21) 23*724ba675SRob Herring #define DOUBLE_EDGE (1 << 20) 24*724ba675SRob Herring #define CLK_A (0 << 18) 25*724ba675SRob Herring #define CLK_B (1 << 18) 26*724ba675SRob Herring #define CLK_C (2 << 18) 27*724ba675SRob Herring #define CLK_D (3 << 18) 28*724ba675SRob Herring 29*724ba675SRob Herring /* User-frendly defines for Pin Direction */ 30*724ba675SRob Herring /* oe = 0, pu = 0, od = 0 */ 31*724ba675SRob Herring #define IN (0) 32*724ba675SRob Herring /* oe = 0, pu = 1, od = 0 */ 33*724ba675SRob Herring #define IN_PU (PU) 34*724ba675SRob Herring /* oe = 1, pu = 0, od = 0 */ 35*724ba675SRob Herring #define OUT (OE) 36*724ba675SRob Herring /* oe = 1, pu = 0, od = 1 */ 37*724ba675SRob Herring #define BIDIR (OE | OD) 38*724ba675SRob Herring /* oe = 1, pu = 1, od = 1 */ 39*724ba675SRob Herring #define BIDIR_PU (OE | PU | OD) 40*724ba675SRob Herring 41*724ba675SRob Herring /* RETIME_TYPE */ 42*724ba675SRob Herring /* 43*724ba675SRob Herring * B Mode 44*724ba675SRob Herring * Bypass retime with optional delay parameter 45*724ba675SRob Herring */ 46*724ba675SRob Herring #define BYPASS (0) 47*724ba675SRob Herring /* 48*724ba675SRob Herring * R0, R1, R0D, R1D modes 49*724ba675SRob Herring * single-edge data non inverted clock, retime data with clk 50*724ba675SRob Herring */ 51*724ba675SRob Herring #define SE_NICLK_IO (RT) 52*724ba675SRob Herring /* 53*724ba675SRob Herring * RIV0, RIV1, RIV0D, RIV1D modes 54*724ba675SRob Herring * single-edge data inverted clock, retime data with clk 55*724ba675SRob Herring */ 56*724ba675SRob Herring #define SE_ICLK_IO (RT | INVERTCLK) 57*724ba675SRob Herring /* 58*724ba675SRob Herring * R0E, R1E, R0ED, R1ED modes 59*724ba675SRob Herring * double-edge data, retime data with clk 60*724ba675SRob Herring */ 61*724ba675SRob Herring #define DE_IO (RT | DOUBLE_EDGE) 62*724ba675SRob Herring /* 63*724ba675SRob Herring * CIV0, CIV1 modes with inverted clock 64*724ba675SRob Herring * Retiming the clk pins will park clock & reduce the noise within the core. 65*724ba675SRob Herring */ 66*724ba675SRob Herring #define ICLK (RT | CLKNOTDATA | INVERTCLK) 67*724ba675SRob Herring /* 68*724ba675SRob Herring * CLK0, CLK1 modes with non-inverted clock 69*724ba675SRob Herring * Retiming the clk pins will park clock & reduce the noise within the core. 70*724ba675SRob Herring */ 71*724ba675SRob Herring #define NICLK (RT | CLKNOTDATA) 72*724ba675SRob Herring #endif /* _ST_PINCFG_H_ */ 73